diff --git a/-Wall b/-Wall new file mode 100755 index 0000000..16fdf42 --- /dev/null +++ b/-Wall @@ -0,0 +1,281 @@ +#! /usr/bin/vvp +:ivl_version "0.9.7 " "(v0_9_7)"; +:vpi_time_precision + 0; +:vpi_module "system"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0xf3d8d0 .scope module, "FSM" "FSM" 2 8; + .timescale 0 0; +P_0xf16e58 .param/l "counterwidth" 2 23, +C4<0101>; +P_0xf16e80 .param/l "width" 2 22, +C4<01000>; +v0xf15020_0 .var "ADDR_WE", 0 0; +v0xf683a0_0 .net "ChipSelCond", 0 0, C4; 0 drivers +v0xf68440_0 .var "DM_WE", 0 0; +v0xf684e0_0 .var "MISO_BUFE", 0 0; +v0xf68590_0 .net "SCLKEdge", 0 0, C4; 0 drivers +v0xf68630_0 .var "SR_WE", 0 0; +v0xf68710_0 .var "WriteController", 0 0; +v0xf687b0_0 .net "clk", 0 0, C4; 0 drivers +v0xf688a0_0 .var "counter", 4 0; +v0xf68940_0 .net "shiftRegOutPZero", 0 0, C4; 0 drivers +E_0xf3db00 .event posedge, v0xf687b0_0; +S_0xf51110 .scope module, "inputconditioner" "inputconditioner" 3 9; + .timescale 0 0; +P_0xf51208 .param/l "counterwidth" 3 18, +C4<011>; +P_0xf51230 .param/l "waittime" 3 19, +C4<011>; +v0xf68a80_0 .net "clk", 0 0, C4; 0 drivers +v0xf68b40_0 .var "conditioned", 0 0; +v0xf68be0_0 .var "counter", 2 0; +v0xf68c80_0 .var "negativeedge", 0 0; +v0xf68d30_0 .net "noisysignal", 0 0, C4; 0 drivers +v0xf68dd0_0 .var "positiveedge", 0 0; +v0xf68e70_0 .var "synchronizer0", 0 0; +v0xf68f10_0 .var "synchronizer1", 0 0; +E_0xf68560 .event posedge, v0xf68a80_0; +S_0xf51260 .scope module, "shiftregister" "shiftregister" 4 9; + .timescale 0 0; +P_0xf4eb58 .param/l "width" 4 10, +C4<01000>; +L_0xf69570 .functor BUFZ 8, v0xf69480_0, C4<00000000>, C4<00000000>, C4<00000000>; +v0xf68ff0_0 .net "clk", 0 0, C4; 0 drivers +v0xf690b0_0 .net "parallelDataIn", 7 0, C4; 0 drivers +v0xf69150_0 .net "parallelDataOut", 7 0, L_0xf69570; 1 drivers +v0xf691f0_0 .net "parallelLoad", 0 0, C4; 0 drivers +v0xf692a0_0 .net "peripheralClkEdge", 0 0, C4; 0 drivers +v0xf69340_0 .net "serialDataIn", 0 0, C4; 0 drivers +v0xf693e0_0 .net "serialDataOut", 0 0, L_0xf69620; 1 drivers +v0xf69480_0 .var "shiftregistermem", 7 0; +E_0xf68d00 .event posedge, v0xf68ff0_0; +L_0xf69620 .part v0xf69480_0, 7, 1; + .scope S_0xf3d8d0; +T_0 ; + %set/v v0xf688a0_0, 0, 5; + %end; + .thread T_0; + .scope S_0xf3d8d0; +T_1 ; + %set/v v0xf68710_0, 0, 1; + %end; + .thread T_1; + .scope S_0xf3d8d0; +T_2 ; + %wait E_0xf3db00; + %load/v 8, v0xf68590_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_2.0, 4; + %load/v 8, v0xf683a0_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %jmp/0xz T_2.2, 4; + %load/v 8, v0xf688a0_0, 5; + %mov 13, 0, 27; + %addi 8, 1, 32; + %ix/load 0, 5, 0; + %assign/v0 v0xf688a0_0, 0, 8; + %load/v 8, v0xf688a0_0, 5; + %mov 13, 0, 2; + %cmpi/u 8, 7, 7; + %jmp/0xz T_2.4, 4; + %ix/load 0, 1, 0; + %assign/v0 v0xf15020_0, 0, 1; +T_2.4 ; + %load/v 8, v0xf688a0_0, 5; + %mov 13, 0, 1; + %cmpi/u 8, 8, 6; + %jmp/0xz T_2.6, 4; + %ix/load 0, 1, 0; + %assign/v0 v0xf15020_0, 0, 0; + %load/v 8, v0xf68940_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %jmp/0xz T_2.8, 4; + %ix/load 0, 1, 0; + %assign/v0 v0xf68710_0, 0, 1; + %jmp T_2.9; +T_2.8 ; + %load/v 8, v0xf68940_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_2.10, 4; + %ix/load 0, 1, 0; + %assign/v0 v0xf68630_0, 0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0xf684e0_0, 0, 1; +T_2.10 ; +T_2.9 ; + %jmp T_2.7; +T_2.6 ; + %movi 8, 7, 7; + %load/v 15, v0xf688a0_0, 5; + %mov 20, 0, 2; + %cmp/u 8, 15, 7; + %jmp/0xz T_2.12, 5; + %ix/load 0, 1, 0; + %assign/v0 v0xf15020_0, 0, 0; + %jmp T_2.13; +T_2.12 ; + %load/v 8, v0xf688a0_0, 5; + %mov 13, 0, 1; + %cmpi/u 8, 15, 6; + %jmp/0xz T_2.14, 4; + %ix/load 0, 5, 0; + %assign/v0 v0xf688a0_0, 0, 0; + %load/v 8, v0xf68710_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_2.16, 4; + %ix/load 0, 1, 0; + %assign/v0 v0xf68440_0, 0, 1; +T_2.16 ; +T_2.14 ; +T_2.13 ; +T_2.7 ; + %jmp T_2.3; +T_2.2 ; + %load/v 8, v0xf683a0_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_2.18, 4; + %ix/load 0, 5, 0; + %assign/v0 v0xf688a0_0, 0, 0; + %ix/load 0, 1, 0; + %assign/v0 v0xf68440_0, 0, 0; + %ix/load 0, 1, 0; + %assign/v0 v0xf15020_0, 0, 0; + %ix/load 0, 1, 0; + %assign/v0 v0xf68630_0, 0, 0; + %ix/load 0, 1, 0; + %assign/v0 v0xf684e0_0, 0, 0; +T_2.18 ; +T_2.3 ; +T_2.0 ; + %jmp T_2; + .thread T_2; + .scope S_0xf51110; +T_3 ; + %set/v v0xf68be0_0, 0, 3; + %end; + .thread T_3; + .scope S_0xf51110; +T_4 ; + %set/v v0xf68e70_0, 0, 1; + %end; + .thread T_4; + .scope S_0xf51110; +T_5 ; + %set/v v0xf68f10_0, 0, 1; + %end; + .thread T_5; + .scope S_0xf51110; +T_6 ; + %wait E_0xf68560; + %load/v 8, v0xf68b40_0, 1; + %load/v 9, v0xf68f10_0, 1; + %cmp/u 8, 9, 1; + %jmp/0xz T_6.0, 4; + %ix/load 0, 3, 0; + %assign/v0 v0xf68be0_0, 0, 0; + %jmp T_6.1; +T_6.0 ; + %load/v 8, v0xf68be0_0, 3; + %mov 11, 0, 1; + %cmpi/u 8, 3, 4; + %jmp/0xz T_6.2, 4; + %ix/load 0, 3, 0; + %assign/v0 v0xf68be0_0, 0, 0; + %load/v 8, v0xf68f10_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0xf68b40_0, 0, 8; + %load/v 8, v0xf68b40_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %mov 8, 4, 1; + %load/v 9, v0xf68f10_0, 1; + %mov 10, 0, 2; + %cmpi/u 9, 1, 3; + %mov 9, 4, 1; + %and 8, 9, 1; + %jmp/0xz T_6.4, 8; + %ix/load 0, 1, 0; + %assign/v0 v0xf68dd0_0, 0, 1; +T_6.4 ; + %load/v 8, v0xf68b40_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %mov 8, 4, 1; + %load/v 9, v0xf68f10_0, 1; + %mov 10, 0, 1; + %cmpi/u 9, 0, 2; + %mov 9, 4, 1; + %and 8, 9, 1; + %jmp/0xz T_6.6, 8; + %ix/load 0, 1, 0; + %assign/v0 v0xf68c80_0, 0, 1; +T_6.6 ; + %jmp T_6.3; +T_6.2 ; + %load/v 8, v0xf68be0_0, 3; + %mov 11, 0, 29; + %addi 8, 1, 32; + %ix/load 0, 3, 0; + %assign/v0 v0xf68be0_0, 0, 8; +T_6.3 ; +T_6.1 ; + %load/v 8, v0xf68dd0_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_6.8, 4; + %ix/load 0, 1, 0; + %assign/v0 v0xf68dd0_0, 0, 0; +T_6.8 ; + %load/v 8, v0xf68c80_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_6.10, 4; + %ix/load 0, 1, 0; + %assign/v0 v0xf68c80_0, 0, 0; +T_6.10 ; + %load/v 8, v0xf68d30_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0xf68e70_0, 0, 8; + %load/v 8, v0xf68e70_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0xf68f10_0, 0, 8; + %jmp T_6; + .thread T_6; + .scope S_0xf51260; +T_7 ; + %wait E_0xf68d00; + %load/v 8, v0xf691f0_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_7.0, 4; + %load/v 8, v0xf690b0_0, 8; + %ix/load 0, 8, 0; + %assign/v0 v0xf69480_0, 0, 8; + %jmp T_7.1; +T_7.0 ; + %load/v 8, v0xf691f0_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %jmp/0xz T_7.2, 4; + %load/v 8, v0xf692a0_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_7.4, 4; + %load/v 8, v0xf69340_0, 1; + %load/v 9, v0xf69480_0, 7; Select 7 out of 8 bits + %ix/load 0, 8, 0; + %assign/v0 v0xf69480_0, 0, 8; +T_7.4 ; +T_7.2 ; +T_7.1 ; + %jmp T_7; + .thread T_7; +# The file index is used to find the file name in the following table. +:file_names 5; + "N/A"; + ""; + "FSM.v"; + "./inputconditioner.v"; + "./shiftregister.v"; diff --git a/CompArch_Lab_2_FinalWriteup.pdf b/CompArch_Lab_2_FinalWriteup.pdf new file mode 100644 index 0000000..c5767ca Binary files /dev/null and b/CompArch_Lab_2_FinalWriteup.pdf differ diff --git a/FSM.t.v b/FSM.t.v new file mode 100644 index 0000000..b57b71b --- /dev/null +++ b/FSM.t.v @@ -0,0 +1,59 @@ +//`timescale 1 ns/ 1 ps +`include "FSM.v" + +module FSMtest(); + + reg clk; + reg SCLKEdge; + reg ChipSelCond; + reg shiftRegOutPZero; + wire MISO_BUFE; + wire DM_WE; + wire ADDR_WE; + wire SR_WE; +// wire counter; + +FSM trial1(clk, SCLKEdge, ChipSelCond, shiftRegOutPZero, MISO_BUFE, DM_WE, ADDR_WE, SR_WE); + + initial clk=0; + always #10 clk=!clk; // 50MHz Clock + + + +initial begin + +$dumpfile("FSM.vcd"); +$dumpvars(); + +// trial 1. Chip Sel = 1, SCLKEdge = 1, everything else should be zero. +$display("CS | MISO_BUFE | DM_WE | ADDR_WE | SR_WE"); +ChipSelCond = 1; SCLKEdge = 1; #200 +$display("%b | %b | %b | %b | %b ", ChipSelCond, MISO_BUFE, DM_WE, ADDR_WE, SR_WE); + + +// trial 2. Chip Sel = 0, SCLKEdge = 1, shiftRegOutPZero = 0 (write), everything else is zero +ChipSelCond = 0; SCLKEdge = 1; shiftRegOutPZero = 0; #200 +$display("%b | %b | %b | %b | %b ", ChipSelCond, MISO_BUFE, DM_WE, ADDR_WE, SR_WE); + +// intermediate. Chip Sel = 1, SCLKEdge = 1, shiftRegOutPZero = 1 (read), everything else is zero +ChipSelCond = 1; SCLKEdge = 1; shiftRegOutPZero = 1; #200 +$display("%b | %b | %b | %b | %b ", ChipSelCond, MISO_BUFE, DM_WE, ADDR_WE, SR_WE); + + +// trial 3. Chip Sel = 0, SCLKEdge = 1, shiftRegOutPZero = 1 (read), everything else is zero +ChipSelCond = 0; SCLKEdge = 1; shiftRegOutPZero = 1; #200 +$display("%b | %b | %b | %b | %b ", ChipSelCond, MISO_BUFE, DM_WE, ADDR_WE, SR_WE); + +// intermediate. Chip Sel = 1, SCLKEdge = 1, shiftRegOutPZero = 1 (read), everything else is zero +ChipSelCond = 1; SCLKEdge = 1; shiftRegOutPZero = 1; #200 +$display("%b | %b | %b | %b | %b ", ChipSelCond, MISO_BUFE, DM_WE, ADDR_WE, SR_WE); + +// trial 3. Chip Sel = 0, SCLKEdge = 1, shiftRegOutPZero = 1 (write), DM_WE should turn on, everything else is zero +ChipSelCond = 0; SCLKEdge = 1; shiftRegOutPZero = 0; #600 +$display("%b | %b | %b | %b | %b ", ChipSelCond, MISO_BUFE, DM_WE, ADDR_WE, SR_WE); + +$finish; +end + + +endmodule diff --git a/FSM.v b/FSM.v new file mode 100644 index 0000000..982f772 --- /dev/null +++ b/FSM.v @@ -0,0 +1,67 @@ +//------------------------------------------------------------------------ +// Finite State Machine +//------------------------------------------------------------------------ + +`include "inputconditioner.v" +`include "shiftregister.v" + +module FSM +( + input clk, // internal + input SCLKEdge, // positive edge of sclk from input cond #2 + input ChipSelCond, // conditioned chip select from input cond #3 + input shiftRegOutPZero, // parallelDataOut[0], tells us to read or write + output reg MISO_BUFE, // controls "valve". 1 if we are reading, 0 otherwise. + output reg DM_WE, // data memory write enable + output reg ADDR_WE, // write enable for address latch + output reg SR_WE // shift register write enable + +); + +//reg counter; +parameter width = 8; +parameter counterwidth = 5; // Counter size, in bits, >= log2(waittime) +reg[counterwidth-1:0] counter = 0; +reg WriteController; +reg restart; + +always @(posedge clk) begin + + if (SCLKEdge == 1) begin + if (ChipSelCond == 0) begin + counter <= counter + 1; + if (counter == width-1) + ADDR_WE <= 1; + else if (counter == width) begin + ADDR_WE <= 0; + if (shiftRegOutPZero == 0) // if you are writing to datamemory + WriteController <= 1; + else if (shiftRegOutPZero == 1) begin // if you are reading to datamemory + SR_WE <= 1; + MISO_BUFE <= 1; + end + end + else if (counter > width) begin + ADDR_WE <= 0; + if (counter == 4'b1111) begin + counter <= 0; + if (WriteController == 1) + DM_WE <= 1; + end + end + + end + + else if (ChipSelCond == 1) begin + counter <= 0; + WriteController <= 0; + DM_WE <= 0; + ADDR_WE <= 0; + SR_WE <= 0; + MISO_BUFE <= 0; // to get Z + end + end + + +end +endmodule diff --git a/FSM.vcd b/FSM.vcd new file mode 100644 index 0000000..05141a0 --- /dev/null +++ b/FSM.vcd @@ -0,0 +1,672 @@ +$date + Tue Oct 31 17:43:59 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module FSMtest $end +$var wire 1 ! ADDR_WE $end +$var wire 1 " DM_WE $end +$var wire 1 # MISO_BUFE $end +$var wire 1 $ SR_WE $end +$var reg 1 % ChipSelCond $end +$var reg 1 & SCLKEdge $end +$var reg 1 ' clk $end +$var reg 1 ( shiftRegOutPZero $end +$scope module trial1 $end +$var wire 1 ) ChipSelCond $end +$var wire 1 * SCLKEdge $end +$var wire 1 + clk $end +$var wire 1 , shiftRegOutPZero $end +$var reg 1 - ADDR_WE $end +$var reg 1 . DM_WE $end +$var reg 1 / MISO_BUFE $end +$var reg 1 0 SR_WE $end +$var reg 1 1 WriteController $end +$var reg 5 2 counter [4:0] $end +$upscope $end +$upscope $end +$scope module inputconditioner $end +$var wire 1 3 clk $end +$var wire 1 4 noisysignal $end +$var reg 1 5 conditioned $end +$var reg 3 6 counter [2:0] $end +$var reg 1 7 negativeedge $end +$var reg 1 8 positiveedge $end +$var reg 1 9 synchronizer0 $end +$var reg 1 : synchronizer1 $end +$upscope $end +$scope module shiftregister $end +$var wire 1 ; clk $end +$var wire 8 < parallelDataIn [7:0] $end +$var wire 8 = parallelDataOut [7:0] $end +$var wire 1 > parallelLoad $end +$var wire 1 ? peripheralClkEdge $end +$var wire 1 @ serialDataIn $end +$var wire 1 A serialDataOut $end +$var reg 8 B shiftregistermem [7:0] $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +bx B +xA +z@ +z? +z> +bx = +bz < +z; +0: +09 +x8 +x7 +b0 6 +x5 +z4 +z3 +b0 2 +x1 +x0 +x/ +x. +x- +x, +0+ +1* +1) +x( +0' +1& +1% +x$ +x# +x" +x! +$end +#10 +0/ +0# +00 +0$ +0- +0! +0. +0" +1' +1+ +#20 +0' +0+ +#30 +1' +1+ +#40 +0' +0+ +#50 +1' +1+ +#60 +0' +0+ +#70 +1' +1+ +#80 +0' +0+ +#90 +1' +1+ +#100 +0' +0+ +#110 +1' +1+ +#120 +0' +0+ +#130 +1' +1+ +#140 +0' +0+ +#150 +1' +1+ +#160 +0' +0+ +#170 +1' +1+ +#180 +0' +0+ +#190 +1' +1+ +#200 +0' +0+ +0( +0, +0% +0) +#210 +b1 2 +1' +1+ +#220 +0' +0+ +#230 +b10 2 +1' +1+ +#240 +0' +0+ +#250 +b11 2 +1' +1+ +#260 +0' +0+ +#270 +b100 2 +1' +1+ +#280 +0' +0+ +#290 +b101 2 +1' +1+ +#300 +0' +0+ +#310 +b110 2 +1' +1+ +#320 +0' +0+ +#330 +b111 2 +1' +1+ +#340 +0' +0+ +#350 +1- +1! +b1000 2 +1' +1+ +#360 +0' +0+ +#370 +11 +0- +0! +b1001 2 +1' +1+ +#380 +0' +0+ +#390 +b1010 2 +1' +1+ +#400 +0' +0+ +1( +1, +1% +1) +#410 +b0 2 +1' +1+ +#420 +0' +0+ +#430 +1' +1+ +#440 +0' +0+ +#450 +1' +1+ +#460 +0' +0+ +#470 +1' +1+ +#480 +0' +0+ +#490 +1' +1+ +#500 +0' +0+ +#510 +1' +1+ +#520 +0' +0+ +#530 +1' +1+ +#540 +0' +0+ +#550 +1' +1+ +#560 +0' +0+ +#570 +1' +1+ +#580 +0' +0+ +#590 +1' +1+ +#600 +0' +0+ +0% +0) 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b/Lab2Vivado/Lab2Vivado.cache/wt/synthesis_details.wdf @@ -0,0 +1,3 @@ +version:1 +73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 +eof:2511430288 diff --git a/Lab2Vivado/Lab2Vivado.cache/wt/webtalk_pa.xml b/Lab2Vivado/Lab2Vivado.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..68f4e21 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.cache/wt/webtalk_pa.xml @@ -0,0 +1,94 @@ + + + + +
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+ + diff --git a/Lab2Vivado/Lab2Vivado.hw/Lab2Vivado.lpr b/Lab2Vivado/Lab2Vivado.hw/Lab2Vivado.lpr new file mode 100644 index 0000000..e87eed2 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.hw/Lab2Vivado.lpr @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Lab2Vivado/Lab2Vivado.hw/hw_1/hw.xml b/Lab2Vivado/Lab2Vivado.hw/hw_1/hw.xml new file mode 100644 index 0000000..2f8d4f9 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.hw/hw_1/hw.xml @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/Lab2Vivado/Lab2Vivado.hw/webtalk/.xsim_webtallk.info b/Lab2Vivado/Lab2Vivado.hw/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..705ed82 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.hw/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1508981863 +0 +2 +0 +2d9661a0-0f57-4ec8-aa41-ea786656a33b diff --git a/Lab2Vivado/Lab2Vivado.hw/webtalk/labtool_webtalk.log b/Lab2Vivado/Lab2Vivado.hw/webtalk/labtool_webtalk.log new file mode 100644 index 0000000..7a9751e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.hw/webtalk/labtool_webtalk.log @@ -0,0 +1,9 @@ + +****** Webtalk v2017.2 (64-bit) + **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 + **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 + ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + +source /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.hw/webtalk/labtool_webtalk.tcl -notrace +webtalk_transmit: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:05 . Memory (MB): peak = 221.098 ; gain = 0.000 ; free physical = 526 ; free virtual = 1723 +INFO: [Common 17-206] Exiting Webtalk at Wed Oct 25 21:37:49 2017... diff --git a/Lab2Vivado/Lab2Vivado.hw/webtalk/usage_statistics_ext_labtool.html b/Lab2Vivado/Lab2Vivado.hw/webtalk/usage_statistics_ext_labtool.html new file mode 100644 index 0000000..6992e59 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.hw/webtalk/usage_statistics_ext_labtool.html @@ -0,0 +1,45 @@ +Device Usage Statistics Report +

LABTOOL Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version1909853
date_generatedWed Oct 25 21:37:43 2017os_platformLIN64
product_versionVivado v2017.2 (64-bit)project_id2d9661a0-0f57-4ec8-aa41-ea786656a33b
project_iteration1random_id354f826d690a59e2a60ede43a3c03094
registration_id354f826d690a59e2a60ede43a3c03094route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowlabtool

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Core(TM) i7-4610M CPU @ 3.00GHzcpu_speed2993.344 MHz
os_nameUbuntuos_releaseUbuntu 16.04.3 LTS
system_ram2.000 GBtotal_processors1

+ + +
vivado_usage

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labtool
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usage
cable=Digilent/Zybo/15000000:chain=0000400013722093pgmcnt=02:00:00
+

+ + diff --git a/Lab2Vivado/Lab2Vivado.hw/webtalk/usage_statistics_ext_labtool.xml b/Lab2Vivado/Lab2Vivado.hw/webtalk/usage_statistics_ext_labtool.xml new file mode 100644 index 0000000..bdf78f8 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.hw/webtalk/usage_statistics_ext_labtool.xml @@ -0,0 +1,39 @@ + + +
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+ diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_1.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..bfeee7e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_10.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000..18c7038 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_11.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_11.xml new file mode 100644 index 0000000..18c7038 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_11.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_12.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_12.xml new file mode 100644 index 0000000..bfeee7e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_12.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_13.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_13.xml new file mode 100644 index 0000000..bfeee7e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_13.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_14.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_14.xml new file mode 100644 index 0000000..65271ee --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_14.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_15.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_15.xml new file mode 100644 index 0000000..18c7038 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_15.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_16.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_16.xml new file mode 100644 index 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b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..bfeee7e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_20.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_20.xml new file mode 100644 index 0000000..bfeee7e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_20.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_21.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_21.xml new file mode 100644 index 0000000..bfeee7e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_21.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_22.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_22.xml new file mode 100644 index 0000000..bfeee7e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_22.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_23.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_23.xml new file mode 100644 index 0000000..bfeee7e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_23.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_24.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_24.xml new file mode 100644 index 0000000..bfeee7e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_24.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_25.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_25.xml new file mode 100644 index 0000000..bfeee7e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_25.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_26.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_26.xml new file mode 100644 index 0000000..bfeee7e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_26.xml @@ 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b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_30.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_30.xml new file mode 100644 index 0000000..bfeee7e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_30.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_31.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_31.xml new file mode 100644 index 0000000..65271ee --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_31.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_32.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_32.xml new file mode 100644 index 0000000..18c7038 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_32.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_33.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_33.xml new file mode 100644 index 0000000..bfeee7e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_33.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_34.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_34.xml new file mode 100644 index 0000000..bfeee7e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_34.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_35.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_35.xml new file mode 100644 index 0000000..bfeee7e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_35.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_36.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_36.xml new file mode 100644 index 0000000..65271ee --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_36.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_37.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_37.xml new file mode 100644 index 0000000..18c7038 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_37.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_38.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_38.xml new file mode 100644 index 0000000..bfeee7e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_38.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_39.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_39.xml new file mode 100644 index 0000000..65271ee --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_39.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_4.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..18c7038 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_40.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_40.xml new file mode 100644 index 0000000..18c7038 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_40.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_5.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..18c7038 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_6.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..50c1caf --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_7.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..18c7038 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_8.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..bfeee7e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_9.xml b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..65271ee --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/.Vivado_Implementation.queue.rst b/Lab2Vivado/Lab2Vivado.runs/impl_1/.Vivado_Implementation.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/.init_design.begin.rst b/Lab2Vivado/Lab2Vivado.runs/impl_1/.init_design.begin.rst new file mode 100644 index 0000000..a45f87a --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/.init_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/.init_design.end.rst b/Lab2Vivado/Lab2Vivado.runs/impl_1/.init_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/.opt_design.begin.rst b/Lab2Vivado/Lab2Vivado.runs/impl_1/.opt_design.begin.rst new file mode 100644 index 0000000..a45f87a --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/.opt_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/.opt_design.end.rst b/Lab2Vivado/Lab2Vivado.runs/impl_1/.opt_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/.place_design.begin.rst b/Lab2Vivado/Lab2Vivado.runs/impl_1/.place_design.begin.rst new file mode 100644 index 0000000..a45f87a --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/.place_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/.place_design.end.rst b/Lab2Vivado/Lab2Vivado.runs/impl_1/.place_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/.route_design.begin.rst b/Lab2Vivado/Lab2Vivado.runs/impl_1/.route_design.begin.rst new file mode 100644 index 0000000..a45f87a --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/.route_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/.route_design.end.rst b/Lab2Vivado/Lab2Vivado.runs/impl_1/.route_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/.vivado.begin.rst b/Lab2Vivado/Lab2Vivado.runs/impl_1/.vivado.begin.rst new file mode 100644 index 0000000..fcedc1e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/.vivado.begin.rst @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/.vivado.end.rst b/Lab2Vivado/Lab2Vivado.runs/impl_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/.write_bitstream.begin.rst b/Lab2Vivado/Lab2Vivado.runs/impl_1/.write_bitstream.begin.rst new file mode 100644 index 0000000..9767612 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/.write_bitstream.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/.write_bitstream.end.rst b/Lab2Vivado/Lab2Vivado.runs/impl_1/.write_bitstream.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/ISEWrap.js b/Lab2Vivado/Lab2Vivado.runs/impl_1/ISEWrap.js new file mode 100755 index 0000000..8284d2d --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/ISEWrap.js @@ -0,0 +1,244 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/ISEWrap.sh b/Lab2Vivado/Lab2Vivado.runs/impl_1/ISEWrap.sh new file mode 100755 index 0000000..e1a8f5d --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/gen_run.xml b/Lab2Vivado/Lab2Vivado.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..8c329d9 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/gen_run.xml @@ -0,0 +1,133 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/htr.txt b/Lab2Vivado/Lab2Vivado.runs/impl_1/htr.txt new file mode 100644 index 0000000..5cc1a54 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# + +vivado -log lab2_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/init_design.pb b/Lab2Vivado/Lab2Vivado.runs/impl_1/init_design.pb new file mode 100644 index 0000000..6d07593 Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/impl_1/init_design.pb differ diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.bit b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.bit new file mode 100644 index 0000000..e1c8110 Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.bit differ diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.tcl b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.tcl new file mode 100644 index 0000000..2f21535 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.tcl @@ -0,0 +1,66 @@ +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + set_param xicom.use_bs_reader 1 + open_checkpoint lab2_wrapper_routed.dcp + set_property webtalk.parent_dir /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.cache/wt [current_project] + catch { write_mem_info -force lab2_wrapper.mmi } + write_bitstream -force lab2_wrapper.bit + catch {write_debug_probes -no_partial_ltxfile -quiet -force debug_nets} + catch {file copy -force debug_nets.ltx lab2_wrapper.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.vdi b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.vdi new file mode 100644 index 0000000..4894faa --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.vdi @@ -0,0 +1,423 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:20:09 2017 +# Process ID: 13005 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1 +# Command line: vivado -log lab2_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1307.199 ; gain = 222.145 ; free physical = 162 ; free virtual = 1287 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1316.203 ; gain = 9.004 ; free physical = 159 ; free virtual = 1284 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1f6118efe + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 80 ; free virtual = 919 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1f6118efe + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 79 ; free virtual = 919 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 24777af58 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 78 ; free virtual = 918 +INFO: [Opt 31-389] Phase Sweep created 6 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 24777af58 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 78 ; free virtual = 918 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 24777af58 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 78 ; free virtual = 918 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 78 ; free virtual = 919 +Ending Logic Optimization Task | Checksum: 24777af58 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 78 ; free virtual = 919 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: a7fa1050 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 77 ; free virtual = 918 +20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:14 . Memory (MB): peak = 1772.695 ; gain = 465.496 ; free physical = 77 ; free virtual = 918 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 73 ; free virtual = 918 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_opt.dcp' has been generated. +Command: report_drc -file lab2_wrapper_drc_opted.rpt +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_opted.rpt. +report_drc completed successfully +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 84 ; free virtual = 909 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 7dc0413c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 84 ; free virtual = 909 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 84 ; free virtual = 909 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1a13da61f + +Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.80 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 77 ; free virtual = 908 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1defd2d5b + +Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.85 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 75 ; free virtual = 908 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1defd2d5b + +Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.86 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 75 ; free virtual = 908 +Phase 1 Placer Initialization | Checksum: 1defd2d5b + +Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.87 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 75 ; free virtual = 908 + +Phase 2 Global Placement +WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 1abb4e82c + +Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.98 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 72 ; free virtual = 907 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1abb4e82c + +Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.98 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 72 ; free virtual = 907 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1ad71ff1d + +Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.99 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 71 ; free virtual = 907 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 296e1b60f + +Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 71 ; free virtual = 907 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 296e1b60f + +Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 71 ; free virtual = 907 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 +Phase 3 Detail Placement | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: b1249ec2 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: b1249ec2 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 +Ending Placer Task | Checksum: 82161d0e + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 907 +31 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 909 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.31 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 90 ; free virtual = 899 +report_utilization: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 97 ; free virtual = 907 +report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 97 ; free virtual = 907 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +Checksum: PlaceDB: 76ee6c0b ConstDB: 0 ShapeSum: b27b103 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 114eef21f + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1818.699 ; gain = 38.000 ; free physical = 85 ; free virtual = 825 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 114eef21f + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1822.699 ; gain = 42.000 ; free physical = 78 ; free virtual = 821 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 114eef21f + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1822.699 ; gain = 42.000 ; free physical = 78 ; free virtual = 821 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 14284a479 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 816 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 1d66c625a + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 +Phase 4 Rip-up And Reroute | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 +Phase 6 Post Hold Fix | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0319538 % + Global Horizontal Routing Utilization = 0.0078125 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 14.4144%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. +Phase 7 Route finalize | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1829.699 ; gain = 49.000 ; free physical = 71 ; free virtual = 817 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 16e397c04 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1829.699 ; gain = 49.000 ; free physical = 71 ; free virtual = 818 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1829.699 ; gain = 49.000 ; free physical = 75 ; free virtual = 822 + +Routing Is Done. +37 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1863.590 ; gain = 82.891 ; free physical = 71 ; free virtual = 822 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1863.590 ; gain = 0.000 ; free physical = 70 ; free virtual = 823 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_routed.dcp' has been generated. +Command: report_drc -file lab2_wrapper_drc_routed.rpt -pb lab2_wrapper_drc_routed.pb -rpx lab2_wrapper_drc_routed.rpx +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file lab2_wrapper_methodology_drc_routed.rpt -rpx lab2_wrapper_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file lab2_wrapper_power_routed.rpt -pb lab2_wrapper_power_summary_routed.pb -rpx lab2_wrapper_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +42 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:21:16 2017... +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:21:29 2017 +# Process ID: 13118 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1 +# Command line: vivado -log lab2_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace +Command: open_checkpoint lab2_wrapper_routed.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1083.043 ; gain = 0.000 ; free physical = 489 ; free virtual = 1545 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/.Xil/Vivado-13118-comparch-VirtualBox/dcp3/lab2_wrapper.xdc] +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/.Xil/Vivado-13118-comparch-VirtualBox/dcp3/lab2_wrapper.xdc] +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1304.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 1293 +Restored from archive | CPU: 0.020000 secs | Memory: 0.048538 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1304.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 1293 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2017.2 (64-bit) build 1909853 +open_checkpoint: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1304.203 ; gain = 221.160 ; free physical = 190 ; free virtual = 1292 +Command: write_bitstream -force lab2_wrapper.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command write_bitstream +Command: report_drc (run_mandatory_drcs) for: bitstream_checks +WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./lab2_wrapper.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-186] '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Wed Oct 25 21:22:12 2017. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. +14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:16 . Memory (MB): peak = 1718.023 ; gain = 413.820 ; free physical = 375 ; free virtual = 1270 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:22:13 2017... diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_11694.backup.vdi b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_11694.backup.vdi new file mode 100644 index 0000000..acf10eb --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_11694.backup.vdi @@ -0,0 +1,364 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:10:47 2017 +# Process ID: 11694 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1 +# Command line: vivado -log lab2_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1307.203 ; gain = 222.145 ; free physical = 74 ; free virtual = 1286 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.31 . Memory (MB): peak = 1316.207 ; gain = 9.004 ; free physical = 71 ; free virtual = 1284 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1f6118efe + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1772.699 ; gain = 0.000 ; free physical = 99 ; free virtual = 927 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1f6118efe + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1772.699 ; gain = 0.000 ; free physical = 98 ; free virtual = 927 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 24777af58 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1772.699 ; gain = 0.000 ; free physical = 94 ; free virtual = 927 +INFO: [Opt 31-389] Phase Sweep created 6 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 24777af58 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1772.699 ; gain = 0.000 ; free physical = 94 ; free virtual = 927 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 24777af58 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1772.699 ; gain = 0.000 ; free physical = 94 ; free virtual = 927 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1772.699 ; gain = 0.000 ; free physical = 94 ; free virtual = 927 +Ending Logic Optimization Task | Checksum: 24777af58 + +Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1772.699 ; gain = 0.000 ; free physical = 94 ; free virtual = 927 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: a7fa1050 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1772.699 ; gain = 0.000 ; free physical = 90 ; free virtual = 927 +20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:16 . Memory (MB): peak = 1772.699 ; gain = 465.496 ; free physical = 89 ; free virtual = 926 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1772.699 ; gain = 0.000 ; free physical = 80 ; free virtual = 926 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_opt.dcp' has been generated. +Command: report_drc -file lab2_wrapper_drc_opted.rpt +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_opted.rpt. +report_drc completed successfully +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 85 ; free virtual = 917 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 7dc0413c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 85 ; free virtual = 917 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 84 ; free virtual = 917 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1a13da61f + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.77 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 76 ; free virtual = 917 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1defd2d5b + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.89 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 72 ; free virtual = 917 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1defd2d5b + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.90 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 72 ; free virtual = 917 +Phase 1 Placer Initialization | Checksum: 1defd2d5b + +Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.91 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 71 ; free virtual = 917 + +Phase 2 Global Placement +WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 1abb4e82c + +Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 67 ; free virtual = 916 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1abb4e82c + +Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 67 ; free virtual = 916 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1ad71ff1d + +Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 67 ; free virtual = 915 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 296e1b60f + +Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 67 ; free virtual = 915 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 296e1b60f + +Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 67 ; free virtual = 915 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 82 ; free virtual = 914 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 82 ; free virtual = 914 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 82 ; free virtual = 914 +Phase 3 Detail Placement | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 82 ; free virtual = 914 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 82 ; free virtual = 914 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 82 ; free virtual = 914 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 82 ; free virtual = 915 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: b1249ec2 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 82 ; free virtual = 915 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: b1249ec2 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 82 ; free virtual = 915 +Ending Placer Task | Checksum: 82161d0e + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 83 ; free virtual = 916 +31 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 83 ; free virtual = 917 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.32 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 106 ; free virtual = 906 +report_utilization: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.36 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 109 ; free virtual = 915 +report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1780.703 ; gain = 0.000 ; free physical = 109 ; free virtual = 914 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +Checksum: PlaceDB: 76ee6c0b ConstDB: 0 ShapeSum: b27b103 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 114eef21f + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1818.703 ; gain = 38.000 ; free physical = 68 ; free virtual = 824 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 114eef21f + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1822.703 ; gain = 42.000 ; free physical = 87 ; free virtual = 813 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 114eef21f + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1822.703 ; gain = 42.000 ; free physical = 88 ; free virtual = 814 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 14284a479 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1827.703 ; gain = 47.000 ; free physical = 82 ; free virtual = 810 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 1d66c625a + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1827.703 ; gain = 47.000 ; free physical = 83 ; free virtual = 810 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1827.703 ; gain = 47.000 ; free physical = 82 ; free virtual = 810 +Phase 4 Rip-up And Reroute | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1827.703 ; gain = 47.000 ; free physical = 82 ; free virtual = 810 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1827.703 ; gain = 47.000 ; free physical = 82 ; free virtual = 810 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1827.703 ; gain = 47.000 ; free physical = 82 ; free virtual = 810 +Phase 6 Post Hold Fix | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1827.703 ; gain = 47.000 ; free physical = 82 ; free virtual = 810 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0319538 % + Global Horizontal Routing Utilization = 0.0078125 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 14.4144%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. +Phase 7 Route finalize | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1827.703 ; gain = 47.000 ; free physical = 82 ; free virtual = 810 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1829.703 ; gain = 49.000 ; free physical = 82 ; free virtual = 810 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 16e397c04 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1829.703 ; gain = 49.000 ; free physical = 82 ; free virtual = 811 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1829.703 ; gain = 49.000 ; free physical = 86 ; free virtual = 815 + +Routing Is Done. +37 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:19 . Memory (MB): peak = 1863.594 ; gain = 82.891 ; free physical = 81 ; free virtual = 815 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1863.594 ; gain = 0.000 ; free physical = 80 ; free virtual = 816 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_routed.dcp' has been generated. +Command: report_drc -file lab2_wrapper_drc_routed.rpt -pb lab2_wrapper_drc_routed.pb -rpx lab2_wrapper_drc_routed.rpx +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file lab2_wrapper_methodology_drc_routed.rpt -rpx lab2_wrapper_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file lab2_wrapper_power_routed.rpt -pb lab2_wrapper_power_summary_routed.pb -rpx lab2_wrapper_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +42 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:12:07 2017... diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_13005.backup.vdi b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_13005.backup.vdi new file mode 100644 index 0000000..46fe208 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_13005.backup.vdi @@ -0,0 +1,364 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:20:09 2017 +# Process ID: 13005 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1 +# Command line: vivado -log lab2_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1307.199 ; gain = 222.145 ; free physical = 162 ; free virtual = 1287 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1316.203 ; gain = 9.004 ; free physical = 159 ; free virtual = 1284 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1f6118efe + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 80 ; free virtual = 919 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1f6118efe + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 79 ; free virtual = 919 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 24777af58 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 78 ; free virtual = 918 +INFO: [Opt 31-389] Phase Sweep created 6 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 24777af58 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 78 ; free virtual = 918 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 24777af58 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 78 ; free virtual = 918 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 78 ; free virtual = 919 +Ending Logic Optimization Task | Checksum: 24777af58 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 78 ; free virtual = 919 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: a7fa1050 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 77 ; free virtual = 918 +20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:14 . Memory (MB): peak = 1772.695 ; gain = 465.496 ; free physical = 77 ; free virtual = 918 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 73 ; free virtual = 918 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_opt.dcp' has been generated. +Command: report_drc -file lab2_wrapper_drc_opted.rpt +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_opted.rpt. +report_drc completed successfully +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 84 ; free virtual = 909 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 7dc0413c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 84 ; free virtual = 909 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 84 ; free virtual = 909 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1a13da61f + +Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.80 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 77 ; free virtual = 908 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1defd2d5b + +Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.85 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 75 ; free virtual = 908 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1defd2d5b + +Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.86 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 75 ; free virtual = 908 +Phase 1 Placer Initialization | Checksum: 1defd2d5b + +Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.87 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 75 ; free virtual = 908 + +Phase 2 Global Placement +WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 1abb4e82c + +Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.98 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 72 ; free virtual = 907 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1abb4e82c + +Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.98 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 72 ; free virtual = 907 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1ad71ff1d + +Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.99 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 71 ; free virtual = 907 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 296e1b60f + +Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 71 ; free virtual = 907 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 296e1b60f + +Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 71 ; free virtual = 907 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 +Phase 3 Detail Placement | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: b1249ec2 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: b1249ec2 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 +Ending Placer Task | Checksum: 82161d0e + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 907 +31 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 909 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.31 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 90 ; free virtual = 899 +report_utilization: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 97 ; free virtual = 907 +report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 97 ; free virtual = 907 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +Checksum: PlaceDB: 76ee6c0b ConstDB: 0 ShapeSum: b27b103 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 114eef21f + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1818.699 ; gain = 38.000 ; free physical = 85 ; free virtual = 825 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 114eef21f + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1822.699 ; gain = 42.000 ; free physical = 78 ; free virtual = 821 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 114eef21f + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1822.699 ; gain = 42.000 ; free physical = 78 ; free virtual = 821 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 14284a479 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 816 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 1d66c625a + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 +Phase 4 Rip-up And Reroute | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 +Phase 6 Post Hold Fix | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0319538 % + Global Horizontal Routing Utilization = 0.0078125 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 14.4144%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. +Phase 7 Route finalize | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1829.699 ; gain = 49.000 ; free physical = 71 ; free virtual = 817 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 16e397c04 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1829.699 ; gain = 49.000 ; free physical = 71 ; free virtual = 818 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1829.699 ; gain = 49.000 ; free physical = 75 ; free virtual = 822 + +Routing Is Done. +37 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1863.590 ; gain = 82.891 ; free physical = 71 ; free virtual = 822 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1863.590 ; gain = 0.000 ; free physical = 70 ; free virtual = 823 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_routed.dcp' has been generated. +Command: report_drc -file lab2_wrapper_drc_routed.rpt -pb lab2_wrapper_drc_routed.pb -rpx lab2_wrapper_drc_routed.rpx +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file lab2_wrapper_methodology_drc_routed.rpt -rpx lab2_wrapper_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file lab2_wrapper_power_routed.rpt -pb lab2_wrapper_power_summary_routed.pb -rpx lab2_wrapper_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +42 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:21:16 2017... diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_7236.backup.vdi b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_7236.backup.vdi new file mode 100644 index 0000000..851aded --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_7236.backup.vdi @@ -0,0 +1,362 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 19:57:10 2017 +# Process ID: 7236 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1 +# Command line: vivado -log lab2_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1307.203 ; gain = 222.145 ; free physical = 78 ; free virtual = 2286 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.34 . Memory (MB): peak = 1316.207 ; gain = 9.004 ; free physical = 75 ; free virtual = 2284 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1172a4803 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.32 . Memory (MB): peak = 1766.699 ; gain = 0.000 ; free physical = 93 ; free virtual = 1920 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1172a4803 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.64 . Memory (MB): peak = 1766.699 ; gain = 0.000 ; free physical = 90 ; free virtual = 1920 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1172a4803 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.68 . Memory (MB): peak = 1766.699 ; gain = 0.000 ; free physical = 90 ; free virtual = 1920 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 1172a4803 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.68 . Memory (MB): peak = 1766.699 ; gain = 0.000 ; free physical = 90 ; free virtual = 1920 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 1172a4803 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.68 . Memory (MB): peak = 1766.699 ; gain = 0.000 ; free physical = 90 ; free virtual = 1920 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1766.699 ; gain = 0.000 ; free physical = 90 ; free virtual = 1920 +Ending Logic Optimization Task | Checksum: 1172a4803 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.70 . Memory (MB): peak = 1766.699 ; gain = 0.000 ; free physical = 90 ; free virtual = 1920 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1172a4803 + +Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1766.699 ; gain = 0.000 ; free physical = 88 ; free virtual = 1919 +20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:15 . Memory (MB): peak = 1766.699 ; gain = 459.496 ; free physical = 87 ; free virtual = 1919 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1766.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 1919 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_opt.dcp' has been generated. +Command: report_drc -file lab2_wrapper_drc_opted.rpt +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_opted.rpt. +report_drc completed successfully +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 80 ; free virtual = 1915 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: e6c5a2e5 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 80 ; free virtual = 1915 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 80 ; free virtual = 1915 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 149442d85 + +Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:01 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 66 ; free virtual = 1915 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 22e6dd286 + +Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:01 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 63 ; free virtual = 1915 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 22e6dd286 + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:01 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 63 ; free virtual = 1915 +Phase 1 Placer Initialization | Checksum: 22e6dd286 + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:01 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 63 ; free virtual = 1915 + +Phase 2 Global Placement +WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 1e8a1cd15 + +Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:02 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 78 ; free virtual = 1876 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1e8a1cd15 + +Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:02 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 78 ; free virtual = 1876 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1968c6871 + +Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:02 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 77 ; free virtual = 1876 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 2012aee20 + +Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:02 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 77 ; free virtual = 1876 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 2012aee20 + +Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:02 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 77 ; free virtual = 1876 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 2476ba32c + +Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:03 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 72 ; free virtual = 1875 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 2476ba32c + +Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:03 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 72 ; free virtual = 1875 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 2476ba32c + +Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:03 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 72 ; free virtual = 1875 +Phase 3 Detail Placement | Checksum: 2476ba32c + +Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:03 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 72 ; free virtual = 1875 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 2476ba32c + +Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:03 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 72 ; free virtual = 1875 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 2476ba32c + +Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:03 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 72 ; free virtual = 1876 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 2476ba32c + +Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:03 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 72 ; free virtual = 1876 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 25b8dfaaa + +Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:03 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 72 ; free virtual = 1876 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 25b8dfaaa + +Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:03 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 72 ; free virtual = 1876 +Ending Placer Task | Checksum: 1a9be4742 + +Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:03 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 73 ; free virtual = 1876 +29 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 73 ; free virtual = 1878 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.30 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 89 ; free virtual = 1892 +report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 96 ; free virtual = 1900 +report_control_sets: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1774.703 ; gain = 0.000 ; free physical = 96 ; free virtual = 1900 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +Checksum: PlaceDB: f3b4d1b3 ConstDB: 0 ShapeSum: b609758f RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: fe4fea66 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1818.703 ; gain = 44.000 ; free physical = 70 ; free virtual = 1794 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: fe4fea66 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1821.703 ; gain = 47.000 ; free physical = 63 ; free virtual = 1790 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: fe4fea66 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1821.703 ; gain = 47.000 ; free physical = 62 ; free virtual = 1790 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 12a59437b + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1827.703 ; gain = 53.000 ; free physical = 75 ; free virtual = 1799 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 1329c4183 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1827.703 ; gain = 53.000 ; free physical = 76 ; free virtual = 1800 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 3 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 4a441b22 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1827.703 ; gain = 53.000 ; free physical = 75 ; free virtual = 1800 +Phase 4 Rip-up And Reroute | Checksum: 4a441b22 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1827.703 ; gain = 53.000 ; free physical = 75 ; free virtual = 1800 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 4a441b22 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1827.703 ; gain = 53.000 ; free physical = 75 ; free virtual = 1800 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 4a441b22 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1827.703 ; gain = 53.000 ; free physical = 75 ; free virtual = 1800 +Phase 6 Post Hold Fix | Checksum: 4a441b22 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1827.703 ; gain = 53.000 ; free physical = 75 ; free virtual = 1800 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.015625 % + Global Horizontal Routing Utilization = 0.00275735 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. +Phase 7 Route finalize | Checksum: 4a441b22 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1827.703 ; gain = 53.000 ; free physical = 75 ; free virtual = 1800 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 4a441b22 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1829.703 ; gain = 55.000 ; free physical = 74 ; free virtual = 1799 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: c5968e34 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1829.703 ; gain = 55.000 ; free physical = 74 ; free virtual = 1800 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1829.703 ; gain = 55.000 ; free physical = 80 ; free virtual = 1805 + +Routing Is Done. +35 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1863.594 ; gain = 88.891 ; free physical = 75 ; free virtual = 1805 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1863.594 ; gain = 0.000 ; free physical = 74 ; free virtual = 1805 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_routed.dcp' has been generated. +Command: report_drc -file lab2_wrapper_drc_routed.rpt -pb lab2_wrapper_drc_routed.pb -rpx lab2_wrapper_drc_routed.rpx +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file lab2_wrapper_methodology_drc_routed.rpt -rpx lab2_wrapper_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file lab2_wrapper_power_routed.rpt -pb lab2_wrapper_power_summary_routed.pb -rpx lab2_wrapper_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +40 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 19:58:25 2017... diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_9254.backup.vdi b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_9254.backup.vdi new file mode 100644 index 0000000..fae9dae --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_9254.backup.vdi @@ -0,0 +1,362 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 20:34:16 2017 +# Process ID: 9254 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1 +# Command line: vivado -log lab2_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1307.199 ; gain = 222.145 ; free physical = 74 ; free virtual = 1371 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1316.203 ; gain = 9.004 ; free physical = 71 ; free virtual = 1369 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 17fdb5d3b + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.33 . Memory (MB): peak = 1773.695 ; gain = 0.000 ; free physical = 122 ; free virtual = 990 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 17fdb5d3b + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1773.695 ; gain = 0.000 ; free physical = 120 ; free virtual = 990 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 17fdb5d3b + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.38 . Memory (MB): peak = 1773.695 ; gain = 0.000 ; free physical = 119 ; free virtual = 990 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 17fdb5d3b + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.41 . Memory (MB): peak = 1773.695 ; gain = 0.000 ; free physical = 118 ; free virtual = 990 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 17fdb5d3b + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.41 . Memory (MB): peak = 1773.695 ; gain = 0.000 ; free physical = 118 ; free virtual = 990 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1773.695 ; gain = 0.000 ; free physical = 118 ; free virtual = 990 +Ending Logic Optimization Task | Checksum: 17fdb5d3b + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1773.695 ; gain = 0.000 ; free physical = 118 ; free virtual = 990 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 17fdb5d3b + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1773.695 ; gain = 0.000 ; free physical = 113 ; free virtual = 990 +20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:16 . Memory (MB): peak = 1773.695 ; gain = 466.496 ; free physical = 109 ; free virtual = 990 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1773.695 ; gain = 0.000 ; free physical = 95 ; free virtual = 989 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_opt.dcp' has been generated. +Command: report_drc -file lab2_wrapper_drc_opted.rpt +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_opted.rpt. +report_drc completed successfully +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 77 ; free virtual = 981 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 17358335b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 77 ; free virtual = 981 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 77 ; free virtual = 981 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 14886c215 + +Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.90 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 65 ; free virtual = 980 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 16e1c616f + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:01 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 989 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 16e1c616f + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:01 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 989 +Phase 1 Placer Initialization | Checksum: 16e1c616f + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:01 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 989 + +Phase 2 Global Placement +WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 1a6d067a2 + +Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:01 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 988 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1a6d067a2 + +Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:01 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 988 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 20a0c5778 + +Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:01 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 988 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 18b03c196 + +Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 72 ; free virtual = 988 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 18b03c196 + +Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 72 ; free virtual = 988 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 13faffb1a + +Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:02 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 982 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 13faffb1a + +Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:02 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 982 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 13faffb1a + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:02 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 982 +Phase 3 Detail Placement | Checksum: 13faffb1a + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:02 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 982 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 13faffb1a + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:02 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 982 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 13faffb1a + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:02 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 983 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 13faffb1a + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:02 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 983 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: f1f9ea1c + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:02 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 983 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: f1f9ea1c + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:02 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 983 +Ending Placer Task | Checksum: 8f087fe0 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:02 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 984 +29 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 72 ; free virtual = 985 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.36 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 80 ; free virtual = 970 +report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 87 ; free virtual = 978 +report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1781.699 ; gain = 0.000 ; free physical = 86 ; free virtual = 977 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +Checksum: PlaceDB: 80035223 ConstDB: 0 ShapeSum: f052dbd RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: fc56ad4b + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1820.699 ; gain = 39.000 ; free physical = 73 ; free virtual = 903 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: fc56ad4b + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1823.699 ; gain = 42.000 ; free physical = 68 ; free virtual = 900 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: fc56ad4b + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1823.699 ; gain = 42.000 ; free physical = 68 ; free virtual = 900 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 147624dbf + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1829.699 ; gain = 48.000 ; free physical = 75 ; free virtual = 902 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: a8bbb633 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1829.699 ; gain = 48.000 ; free physical = 76 ; free virtual = 902 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 1c1648c3c + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1829.699 ; gain = 48.000 ; free physical = 75 ; free virtual = 902 +Phase 4 Rip-up And Reroute | Checksum: 1c1648c3c + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1829.699 ; gain = 48.000 ; free physical = 75 ; free virtual = 902 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 1c1648c3c + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1829.699 ; gain = 48.000 ; free physical = 75 ; free virtual = 902 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 1c1648c3c + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1829.699 ; gain = 48.000 ; free physical = 75 ; free virtual = 902 +Phase 6 Post Hold Fix | Checksum: 1c1648c3c + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1829.699 ; gain = 48.000 ; free physical = 75 ; free virtual = 902 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0318131 % + Global Horizontal Routing Utilization = 0.0105699 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 18.018%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 5.88235%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 5.88235%, No Congested Regions. +Phase 7 Route finalize | Checksum: 1c1648c3c + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1829.699 ; gain = 48.000 ; free physical = 75 ; free virtual = 902 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 1c1648c3c + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1831.699 ; gain = 50.000 ; free physical = 74 ; free virtual = 901 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 16e94c267 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1831.699 ; gain = 50.000 ; free physical = 75 ; free virtual = 902 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1831.699 ; gain = 50.000 ; free physical = 80 ; free virtual = 907 + +Routing Is Done. +35 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1865.590 ; gain = 83.891 ; free physical = 74 ; free virtual = 908 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1865.590 ; gain = 0.000 ; free physical = 72 ; free virtual = 907 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_routed.dcp' has been generated. +Command: report_drc -file lab2_wrapper_drc_routed.rpt -pb lab2_wrapper_drc_routed.pb -rpx lab2_wrapper_drc_routed.rpx +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file lab2_wrapper_methodology_drc_routed.rpt -rpx lab2_wrapper_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file lab2_wrapper_power_routed.rpt -pb lab2_wrapper_power_summary_routed.pb -rpx lab2_wrapper_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +40 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 20:35:33 2017... diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_clock_utilization_routed.rpt b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_clock_utilization_routed.rpt new file mode 100644 index 0000000..19c6d76 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_clock_utilization_routed.rpt @@ -0,0 +1,140 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:21:16 2017 +| Host : comparch-VirtualBox running 64-bit unknown +| Command : report_clock_utilization -file lab2_wrapper_clock_utilization_routed.rpt +| Design : lab2_wrapper +| Device : 7z010-clg400 +| Speed File : -1 PRODUCTION 1.11 2014-09-11 +------------------------------------------------------------------------------------------ + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X1Y0 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 48 | 0 | 0 | 0 | +| BUFIO | 0 | 8 | 0 | 0 | 0 | +| BUFMR | 0 | 4 | 0 | 0 | 0 | +| BUFR | 0 | 8 | 0 | 0 | 0 | +| MMCM | 0 | 2 | 0 | 0 | 0 | +| PLL | 0 | 2 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 1 | 26 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| src0 | g0 | IBUF/O | IOB_X0Y78 | IOB_X0Y78 | X1Y1 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 26 | 1100 | 15 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1100 | 0 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y1 | 0 | 0 | +| Y0 | 0 | 1 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| g0 | BUFG/O | n/a | | | | 26 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+-----+ +| | X0 | X1 | ++----+----+-----+ +| Y1 | 0 | 0 | +| Y0 | 0 | 26 | ++----+----+-----+ + + +7. Clock Region Cell Placement per Global Clock: Region X1Y0 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 26 | 0 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y16 [get_cells clk_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X0Y78 [get_ports clk] + +# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y16" +#startgroup +create_pblock {CLKAG_clk_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0} +#endgroup diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_control_sets_placed.rpt b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_control_sets_placed.rpt new file mode 100644 index 0000000..e0e0743 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_control_sets_placed.rpt @@ -0,0 +1,63 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:20:54 2017 +| Host : comparch-VirtualBox running 64-bit Ubuntu 16.04.3 LTS +| Command : report_control_sets -verbose -file lab2_wrapper_control_sets_placed.rpt +| Design : lab2_wrapper +| Device : xc7z010 +----------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Flip-Flop Distribution +3. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 2 | +| Unused register locations in slices containing registers | 6 | ++----------------------------------------------------------+-------+ + + +2. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 14 | 5 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 12 | 2 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +3. Detailed Control Set Information +----------------------------------- + ++----------------+---------------------------------------+------------------------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++----------------+---------------------------------------+------------------------------------+------------------+----------------+ +| clk_IBUF_BUFG | mid/parallelLoadCond/shiftregistermem | mid/parallelLoadCond/negativeedge0 | 2 | 12 | +| clk_IBUF_BUFG | | | 5 | 14 | ++----------------+---------------------------------------+------------------------------------+------------------+----------------+ + + ++--------+-----------------------+ +| Fanout | Number of ControlSets | ++--------+-----------------------+ +| 12 | 1 | +| 14 | 1 | ++--------+-----------------------+ + + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_opted.rpt b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_opted.rpt new file mode 100644 index 0000000..ce2e595 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_opted.rpt @@ -0,0 +1,41 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:20:52 2017 +| Host : comparch-VirtualBox running 64-bit Ubuntu 16.04.3 LTS +| Command : report_drc -file lab2_wrapper_drc_opted.rpt +| Design : lab2_wrapper +| Device : xc7z010clg400-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++--------+----------+--------------------+------------+ +| Rule | Severity | Description | Violations | ++--------+----------+--------------------+------------+ +| ZPS7-1 | Warning | PS7 block required | 1 | ++--------+----------+--------------------+------------+ + +2. REPORT DETAILS +----------------- +ZPS7-1#1 Warning +PS7 block required +The PS7 cell must be used in this Zynq design in order to enable correct default configuration. +Related violations: + + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_routed.pb b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_routed.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_routed.pb differ diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_routed.rpt b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_routed.rpt new file mode 100644 index 0000000..8dfdfd0 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_routed.rpt @@ -0,0 +1,41 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:21:14 2017 +| Host : comparch-VirtualBox running 64-bit unknown +| Command : report_drc -file lab2_wrapper_drc_routed.rpt -pb lab2_wrapper_drc_routed.pb -rpx lab2_wrapper_drc_routed.rpx +| Design : lab2_wrapper +| Device : xc7z010clg400-1 +| Speed File : -1 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++--------+----------+--------------------+------------+ +| Rule | Severity | Description | Violations | ++--------+----------+--------------------+------------+ +| ZPS7-1 | Warning | PS7 block required | 1 | ++--------+----------+--------------------+------------+ + +2. REPORT DETAILS +----------------- +ZPS7-1#1 Warning +PS7 block required +The PS7 cell must be used in this Zynq design in order to enable correct default configuration. +Related violations: + + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_routed.rpx b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_routed.rpx new file mode 100644 index 0000000..9c15c7c Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_routed.rpx differ diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_io_placed.rpt b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_io_placed.rpt new file mode 100644 index 0000000..ba74333 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_io_placed.rpt @@ -0,0 +1,442 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:20:54 2017 +| Host : comparch-VirtualBox running 64-bit Ubuntu 16.04.3 LTS +| Command : report_io -file lab2_wrapper_io_placed.rpt +| Design : lab2_wrapper +| Device : xc7z010 +| Speed File : -1 +| Package : clg400 +| Package Version : FINAL 2012-10-23 +| Package Pin Delay Version : VERS. 2.0 2012-10-23 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 21 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | ++------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+ +| A1 | | | PS_DDR_DM0_502 | PSS IO | | | | | | | | | | | | | +| A2 | | | PS_DDR_DQ2_502 | PSS IO | | | | | | | | | | | | | +| A3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| A4 | | | PS_DDR_DQ3_502 | PSS IO | | | | | | | | | | | | | +| A5 | | | PS_MIO6_500 | PSS IO | | | | | | | | | | | | | +| A6 | | | PS_MIO5_500 | PSS IO | | | | | | | | | | | | | +| A7 | | | PS_MIO1_500 | PSS IO | | | | | | | | | | | | | +| A8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| A9 | | | PS_MIO43_501 | PSS IO | | | | | | | | | | | | | +| A10 | | | PS_MIO37_501 | PSS IO | | | | | | | | | | | | | +| A11 | | | PS_MIO36_501 | PSS IO | | | | | | | | | | | | | +| A12 | | | PS_MIO34_501 | PSS IO | | | | | | | | | | | | | +| A13 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| A14 | | | PS_MIO32_501 | PSS IO | | | | | | | | | | | | | +| A15 | | | PS_MIO26_501 | PSS IO | | | | | | | | | | | | | +| A16 | | | PS_MIO24_501 | PSS IO | | | | | | | | | | | | | +| A17 | | | PS_MIO20_501 | PSS IO | | | | | | | | | | | | | +| A18 | | | GND | GND | | | | | | | 0.0 | | | | | | +| A19 | | | PS_MIO16_501 | PSS IO | | | | | | | | | | | | | +| A20 | | High Range | IO_L2N_T0_AD8N_35 | User IO | | 35 | | | | | | | | | | | +| B1 | | | GND | GND | | | | | | | 0.0 | | | | | | +| B2 | | | PS_DDR_DQS_N0_502 | PSS IO | | | | | | | | | | | | | +| B3 | | | PS_DDR_DQ1_502 | PSS IO | | | | | | | | | | | | | +| B4 | | | PS_DDR_DRST_B_502 | PSS IO | | | | | | | | | | | | | +| B5 | | | PS_MIO9_500 | PSS IO | | | | | | | | | | | | | +| B6 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | +| B7 | | | PS_MIO4_500 | PSS IO | | | | | | | | | | | | | +| B8 | | | PS_MIO2_500 | PSS IO | | | | | | | | | | | | | +| B9 | | | PS_MIO51_501 | PSS IO | | | | | | | | | | | | | +| B10 | | | PS_SRST_B_501 | PSS IO | | | | | | | | | | | | | +| B11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| B12 | | | PS_MIO48_501 | PSS IO | | | | | | | | | | | | | +| B13 | | | PS_MIO50_501 | PSS IO | | | | | | | | | | | | | +| B14 | | | PS_MIO47_501 | PSS IO | | | | | | | | | | | | | +| B15 | | | PS_MIO45_501 | PSS IO | | | | | | | | | | | | | +| B16 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| B17 | | | PS_MIO22_501 | PSS IO | | | | | | | | | | | | | +| B18 | | | PS_MIO18_501 | PSS IO | | | | | | | | | | | | | +| B19 | | High Range | IO_L2P_T0_AD8P_35 | User IO | | 35 | | | | | | | | | | | +| B20 | | High Range | IO_L1N_T0_AD0N_35 | User IO | | 35 | | | | | | | | | | | +| C1 | | | PS_DDR_DQ6_502 | PSS IO | | | | | | | | | | | | | +| C2 | | | PS_DDR_DQS_P0_502 | PSS IO | | | | | | | | | | | | | +| C3 | | | PS_DDR_DQ0_502 | PSS IO | | | | | | | | | | | | | +| C4 | | | GND | GND | | | | | | | 0.0 | | | | | | +| C5 | | | PS_MIO14_500 | PSS IO | | | | | | | | | | | | | +| C6 | | | PS_MIO11_500 | PSS IO | | | | | | | | | | | | | +| C7 | | | PS_POR_B_500 | PSS IO | | | | | | | | | | | | | +| C8 | | | PS_MIO15_500 | PSS IO | | | | | | | | | | | | | +| C9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| C10 | | | PS_MIO52_501 | PSS IO | | | | | | | | | | | | | +| C11 | | | PS_MIO53_501 | PSS IO | | | | | | | | | | | | | +| C12 | | | PS_MIO49_501 | PSS IO | | | | | | | | | | | | | +| C13 | | | PS_MIO29_501 | PSS IO | | | | | | | | | | | | | +| C14 | | | GND | GND | | | | | | | 0.0 | | | | | | +| C15 | | | PS_MIO30_501 | PSS IO | | | | | | | | | | | | | +| C16 | | | PS_MIO28_501 | PSS IO | | | | | | | | | | | | | +| C17 | | | PS_MIO41_501 | PSS IO | | | | | | | | | | | | | +| C18 | | | PS_MIO39_501 | PSS IO | | | | | | | | | | | | | +| C19 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| C20 | | High Range | IO_L1P_T0_AD0P_35 | User IO | | 35 | | | | | | | | | | | +| D1 | | | PS_DDR_DQ5_502 | PSS IO | | | | | | | | | | | | | +| D2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| D3 | | | PS_DDR_DQ4_502 | PSS IO | | | | | | | | | | | | | +| D4 | | | PS_DDR_A13_502 | PSS IO | | | | | | | | | | | | | +| D5 | | | PS_MIO8_500 | PSS IO | | | | | | | | | | | | | +| D6 | | | PS_MIO3_500 | PSS IO | | | | | | | | | | | | | +| D7 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | +| D8 | | | PS_MIO7_500 | PSS IO | | | | | | | | | | | | | +| D9 | | | PS_MIO12_500 | PSS IO | | | | | | | | | | | | | +| D10 | | | PS_MIO19_501 | PSS IO | | | | | | | | | | | | | +| D11 | | | PS_MIO23_501 | PSS IO | | | | | | | | | | | | | +| D12 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| D13 | | | PS_MIO27_501 | PSS IO | | | | | | | | | | | | | +| D14 | | | PS_MIO40_501 | PSS IO | | | | | | | | | | | | | +| D15 | | | PS_MIO33_501 | PSS IO | | | | | | | | | | | | | +| D16 | | | PS_MIO46_501 | PSS IO | | | | | | | | | | | | | +| D17 | | | GND | GND | | | | | | | 0.0 | | | | | | +| D18 | led[3] | High Range | IO_L3N_T0_DQS_AD1N_35 | TRISTATE | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| D19 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | +| D20 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | +| E1 | | | PS_DDR_DQ7_502 | PSS IO | | | | | | | | | | | | | +| E2 | | | PS_DDR_DQ8_502 | PSS IO | | | | | | | | | | | | | +| E3 | | | PS_DDR_DQ9_502 | PSS IO | | | | | | | | | | | | | +| E4 | | | PS_DDR_A12_502 | PSS IO | | | | | | | | | | | | | +| E5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| E6 | | | PS_MIO0_500 | PSS IO | | | | | | | | | | | | | +| E7 | | | PS_CLK_500 | PSS Clock | | | | | | | | | | | | | +| E8 | | | PS_MIO13_500 | PSS IO | | | | | | | | | | | | | +| E9 | | | PS_MIO10_500 | PSS IO | | | | | | | | | | | | | +| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| E11 | | | PS_MIO_VREF_501 | PSS IO | | | | | | | | | | | | | +| E12 | | | PS_MIO42_501 | PSS IO | | | | | | | | | | | | | +| E13 | | | PS_MIO38_501 | PSS IO | | | | | | | | | | | | | +| E14 | | | PS_MIO17_501 | PSS IO | | | | | | | | | | | | | +| E15 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| E16 | | | PS_MIO31_501 | PSS IO | | | | | | | | | | | | | +| E17 | | High Range | IO_L3P_T0_DQS_AD1P_35 | User IO | | 35 | | | | | | | | | | | +| E18 | | High Range | IO_L5P_T0_AD9P_35 | User IO | | 35 | | | | | | | | | | | +| E19 | | High Range | IO_L5N_T0_AD9N_35 | User IO | | 35 | | | | | | | | | | | +| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | +| F1 | | | PS_DDR_DM1_502 | PSS IO | | | | | | | | | | | | | +| F2 | | | PS_DDR_DQS_N1_502 | PSS IO | | | | | | | | | | | | | +| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | +| F4 | | | PS_DDR_A14_502 | PSS IO | | | | | | | | | | | | | +| F5 | | | PS_DDR_A10_502 | PSS IO | | | | | | | | | | | | | +| F6 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| F8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| F9 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | +| F10 | | | RSVDGND | GND | | | | | | | | | | | | | +| F11 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | +| F12 | | | PS_MIO35_501 | PSS IO | | | | | | | | | | | | | +| F13 | | | PS_MIO44_501 | PSS IO | | | | | | | | | | | | | +| F14 | | | PS_MIO21_501 | PSS IO | | | | | | | | | | | | | +| F15 | | | PS_MIO25_501 | PSS IO | | | | | | | | | | | | | +| F16 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | +| F17 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | +| F18 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| F19 | | High Range | IO_L15P_T2_DQS_AD12P_35 | User IO | | 35 | | | | | | | | | | | +| F20 | | High Range | IO_L15N_T2_DQS_AD12N_35 | User IO | | 35 | | | | | | | | | | | +| G1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| G2 | | | PS_DDR_DQS_P1_502 | PSS IO | | | | | | | | | | | | | +| G3 | | | PS_DDR_DQ10_502 | PSS IO | | | | | | | | | | | | | +| G4 | | | PS_DDR_A11_502 | PSS IO | | | | | | | | | | | | | +| G5 | | | PS_DDR_VRN_502 | PSS IO | | | | | | | | | | | | | +| G6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | +| G7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| G8 | | | VCCPLL | PSS VCCPLL | | | | | | | | | | | | | +| G9 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| G14 | led[2] | High Range | IO_0_35 | TRISTATE | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| G15 | sw[0] | High Range | IO_L19N_T3_VREF_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | +| G16 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G17 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | +| G18 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | +| G19 | | High Range | IO_L18P_T2_AD13P_35 | User IO | | 35 | | | | | | | | | | | +| G20 | | High Range | IO_L18N_T2_AD13N_35 | User IO | | 35 | | | | | | | | | | | +| H1 | | | PS_DDR_DQ14_502 | PSS IO | | | | | | | | | | | | | +| H2 | | | PS_DDR_DQ13_502 | PSS IO | | | | | | | | | | | | | +| H3 | | | PS_DDR_DQ11_502 | PSS IO | | | | | | | | | | | | | +| H4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| H5 | | | PS_DDR_VRP_502 | PSS IO | | | | | | | | | | | | | +| H6 | | | PS_DDR_VREF0_502 | PSS IO | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| H9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H12 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H14 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| H15 | je[3] | High Range | IO_L19P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H16 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | +| H17 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | +| H18 | | High Range | IO_L14N_T2_AD4N_SRCC_35 | User IO | | 35 | | | | | | | | | | | +| H19 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H20 | | High Range | IO_L17N_T2_AD5N_35 | User IO | | 35 | | | | | | | | | | | +| J1 | | | PS_DDR_DQ15_502 | PSS IO | | | | | | | | | | | | | +| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J3 | | | PS_DDR_DQ12_502 | PSS IO | | | | | | | | | | | | | +| J4 | | | PS_DDR_A9_502 | PSS IO | | | | | | | | | | | | | +| J5 | | | PS_DDR_BA2_502 | PSS IO | | | | | | | | | | | | | +| J6 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | +| J7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J9 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | +| J10 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | +| J11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| J14 | | High Range | IO_L20N_T3_AD6N_35 | User IO | | 35 | | | | | | | | | | | +| J15 | je[2] | High Range | IO_25_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J16 | | High Range | IO_L24N_T3_AD15N_35 | User IO | | 35 | | | | | | | | | | | +| J17 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| J18 | | High Range | IO_L14P_T2_AD4P_SRCC_35 | User IO | | 35 | | | | | | | | | | | +| J19 | | High Range | IO_L10N_T1_AD11N_35 | User IO | | 35 | | | | | | | | | | | +| J20 | | High Range | IO_L17P_T2_AD5P_35 | User IO | | 35 | | | | | | | | | | | +| K1 | | | PS_DDR_A8_502 | PSS IO | | | | | | | | | | | | | +| K2 | | | PS_DDR_A1_502 | PSS IO | | | | | | | | | | | | | +| K3 | | | PS_DDR_A3_502 | PSS IO | | | | | | | | | | | | | +| K4 | | | PS_DDR_A7_502 | PSS IO | | | | | | | | | | | | | +| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K6 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| K9 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | +| K10 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K12 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K14 | | High Range | IO_L20P_T3_AD6P_35 | User IO | | 35 | | | | | | | | | | | +| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K16 | | High Range | IO_L24P_T3_AD15P_35 | User IO | | 35 | | | | | | | | | | | +| K17 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | +| K18 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | +| K19 | | High Range | IO_L10P_T1_AD11P_35 | User IO | | 35 | | | | | | | | | | | +| K20 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| L1 | | | PS_DDR_A5_502 | PSS IO | | | | | | | | | | | | | +| L2 | | | PS_DDR_CKP_502 | PSS IO | | | | | | | | | | | | | +| L3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| L4 | | | PS_DDR_A6_502 | PSS IO | | | | | | | | | | | | | +| L5 | | | PS_DDR_BA0_502 | PSS IO | | | | | | | | | | | | | +| L6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | +| L7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L9 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | +| L10 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | +| L11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| L14 | | High Range | IO_L22P_T3_AD7P_35 | User IO | | 35 | | | | | | | | | | | +| L15 | | High Range | IO_L22N_T3_AD7N_35 | User IO | | 35 | | | | | | | | | | | +| L16 | clk | High Range | IO_L11P_T1_SRCC_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | +| L17 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | +| L18 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L19 | | High Range | IO_L9P_T1_DQS_AD3P_35 | User IO | | 35 | | | | | | | | | | | +| L20 | | High Range | IO_L9N_T1_DQS_AD3N_35 | User IO | | 35 | | | | | | | | | | | +| M1 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M2 | | | PS_DDR_CKN_502 | PSS IO | | | | | | | | | | | | | +| M3 | | | PS_DDR_A2_502 | PSS IO | | | | | | | | | | | | | +| M4 | | | PS_DDR_A4_502 | PSS IO | | | | | | | | | | | | | +| M5 | | | PS_DDR_WE_B_502 | PSS IO | | | | | | | | | | | | | +| M6 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| M9 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | +| M10 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M12 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M14 | led[0] | High Range | IO_L23P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M15 | led[1] | High Range | IO_L23N_T3_35 | TRISTATE | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M16 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| M17 | | High Range | IO_L8P_T1_AD10P_35 | User IO | | 35 | | | | | | | | | | | +| M18 | | High Range | IO_L8N_T1_AD10N_35 | User IO | | 35 | | | | | | | | | | | +| M19 | | High Range | IO_L7P_T1_AD2P_35 | User IO | | 35 | | | | | | | | | | | +| M20 | | High Range | IO_L7N_T1_AD2N_35 | User IO | | 35 | | | | | | | | | | | +| N1 | | | PS_DDR_CS_B_502 | PSS IO | | | | | | | | | | | | | +| N2 | | | PS_DDR_A0_502 | PSS IO | | | | | | | | | | | | | +| N3 | | | PS_DDR_CKE_502 | PSS IO | | | | | | | | | | | | | +| N4 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N5 | | | PS_DDR_ODT_502 | PSS IO | | | | | | | | | | | | | +| N6 | | | RSVDVCC3 | Reserved | | | | | | | | | | | | | +| N7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N15 | | High Range | IO_L21P_T3_DQS_AD14P_35 | User IO | | 35 | | | | | | | | | | | +| N16 | | High Range | IO_L21N_T3_DQS_AD14N_35 | User IO | | 35 | | | | | | | | | | | +| N17 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | +| N18 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | +| N19 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| N20 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | +| P1 | | | PS_DDR_DQ16_502 | PSS IO | | | | | | | | | | | | | +| P2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| P3 | | | PS_DDR_DQ17_502 | PSS IO | | | | | | | | | | | | | +| P4 | | | PS_DDR_RAS_B_502 | PSS IO | | | | | | | | | | | | | +| P5 | | | PS_DDR_CAS_B_502 | PSS IO | | | | | | | | | | | | | +| P6 | | | PS_DDR_VREF1_502 | PSS IO | | | | | | | | | | | | | +| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P8 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P12 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P14 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | +| P15 | sw[1] | High Range | IO_L24P_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | +| P16 | btn[1] | High Range | IO_L24N_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | +| P17 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P18 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | +| P19 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | +| P20 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | +| R1 | | | PS_DDR_DQ19_502 | PSS IO | | | | | | | | | | | | | +| R2 | | | PS_DDR_DQS_P2_502 | PSS IO | | | | | | | | | | | | | +| R3 | | | PS_DDR_DQ18_502 | PSS IO | | | | | | | | | | | | | +| R4 | | | PS_DDR_BA1_502 | PSS IO | | | | | | | | | | | | | +| R5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| R6 | | | RSVDVCC2 | Reserved | | | | | | | | | | | | | +| R7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| R10 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | +| R11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | +| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| R13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| R14 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | +| R15 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| R16 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | +| R17 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | +| R18 | btn[0] | High Range | IO_L20N_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | +| R19 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | +| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | +| T1 | | | PS_DDR_DM2_502 | PSS IO | | | | | | | | | | | | | +| T2 | | | PS_DDR_DQS_N2_502 | PSS IO | | | | | | | | | | | | | +| T3 | | | GND | GND | | | | | | | 0.0 | | | | | | +| T4 | | | PS_DDR_DQ20_502 | PSS IO | | | | | | | | | | | | | +| T5 | | | NC | Not Connected | | | | | | | | | | | | | +| T6 | | | RSVDVCC1 | Reserved | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| T8 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | +| T9 | | | NC | Not Connected | | | | | | | | | | | | | +| T10 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | +| T11 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | +| T12 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | +| T13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| T14 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | +| T15 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | +| T16 | sw[3] | High Range | IO_L9P_T1_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | +| T17 | je[6] | High Range | IO_L20P_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| T18 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| T19 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | +| T20 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | +| U1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| U2 | | | PS_DDR_DQ22_502 | PSS IO | | | | | | | | | | | | | +| U3 | | | PS_DDR_DQ23_502 | PSS IO | | | | | | | | | | | | | +| U4 | | | PS_DDR_DQ21_502 | PSS IO | | | | | | | | | | | | | +| U5 | | | NC | Not Connected | | | | | | | | | | | | | +| U6 | | | GND | GND | | | | | | | 0.0 | | | | | | +| U7 | | | NC | Not Connected | | | | | | | | | | | | | +| U8 | | | NC | Not Connected | | | | | | | | | | | | | +| U9 | | | NC | Not Connected | | | | | | | | | | | | | +| U10 | | | NC | Not Connected | | | | | | | | | | | | | +| U11 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | +| U12 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | +| U13 | | High Range | IO_L3P_T0_DQS_PUDC_B_34 | User IO | | 34 | | | | | | | | | | | +| U14 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | +| U15 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | +| U16 | | | GND | GND | | | | | | | 0.0 | | | | | | +| U17 | je[5] | High Range | IO_L9N_T1_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| U18 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | +| U19 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | +| U20 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | +| V1 | | | PS_DDR_DQ24_502 | PSS IO | | | | | | | | | | | | | +| V2 | | | PS_DDR_DQ30_502 | PSS IO | | | | | | | | | | | | | +| V3 | | | PS_DDR_DQ31_502 | PSS IO | | | | | | | | | | | | | +| V4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| V5 | | | NC | Not Connected | | | | | | | | | | | | | +| V6 | | | NC | Not Connected | | | | | | | | | | | | | +| V7 | | | NC | Not Connected | | | | | | | | | | | | | +| V8 | | | NC | Not Connected | | | | | | | | | | | | | +| V9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| V10 | | | NC | Not Connected | | | | | | | | | | | | | +| V11 | | | NC | Not Connected | | | | | | | | | | | | | +| V12 | je[0] | High Range | IO_L4P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| V13 | je[4] | High Range | IO_L3N_T0_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| V14 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| V15 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | +| V16 | btn[2] | High Range | IO_L18P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | +| V17 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | +| V18 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | +| V19 | | | GND | GND | | | | | | | 0.0 | | | | | | +| V20 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | +| W1 | | | PS_DDR_DQ26_502 | PSS IO | | | | | | | | | | | | | +| W2 | | | GND | GND | | | | | | | 0.0 | | | | | | +| W3 | | | PS_DDR_DQ29_502 | PSS IO | | | | | | | | | | | | | +| W4 | | | PS_DDR_DQS_N3_502 | PSS IO | | | | | | | | | | | | | +| W5 | | | PS_DDR_DQS_P3_502 | PSS IO | | | | | | | | | | | | | +| W6 | | | NC | Not Connected | | | | | | | | | | | | | +| W7 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | +| W8 | | | NC | Not Connected | | | | | | | | | | | | | +| W9 | | | NC | Not Connected | | | | | | | | | | | | | +| W10 | | | NC | Not Connected | | | | | | | | | | | | | +| W11 | | | NC | Not Connected | | | | | | | | | | | | | +| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| W13 | sw[2] | High Range | IO_L4N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | +| W14 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | +| W15 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | +| W16 | je[1] | High Range | IO_L18N_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| W17 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| W18 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | +| W19 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | +| W20 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | +| Y1 | | | PS_DDR_DM3_502 | PSS IO | | | | | | | | | | | | | +| Y2 | | | PS_DDR_DQ28_502 | PSS IO | | | | | | | | | | | | | +| Y3 | | | PS_DDR_DQ25_502 | PSS IO | | | | | | | | | | | | | +| Y4 | | | PS_DDR_DQ27_502 | PSS IO | | | | | | | | | | | | | +| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| Y6 | | | NC | Not Connected | | | | | | | | | | | | | +| Y7 | | | NC | Not Connected | | | | | | | | | | | | | +| Y8 | | | NC | Not Connected | | | | | | | | | | | | | +| Y9 | | | NC | Not Connected | | | | | | | | | | | | | +| Y10 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | +| Y11 | | | NC | Not Connected | | | | | | | | | | | | | +| Y12 | | | NC | Not Connected | | | | | | | | | | | | | +| Y13 | | | NC | Not Connected | | | | | | | | | | | | | +| Y14 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | +| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | +| Y16 | btn[3] | High Range | IO_L7P_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | +| Y17 | je[7] | High Range | IO_L7N_T1_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| Y18 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | +| Y19 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | +| Y20 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | ++------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpt b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpt new file mode 100644 index 0000000..fe783ba --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpt @@ -0,0 +1,165 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:21:15 2017 +| Host : comparch-VirtualBox running 64-bit unknown +| Command : report_methodology -file lab2_wrapper_methodology_drc_routed.rpt -rpx lab2_wrapper_methodology_drc_routed.rpx +| Design : lab2_wrapper +| Device : xc7z010clg400-1 +| Speed File : -1 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 26 ++-----------+----------+-----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-----------------------------+------------+ +| TIMING-17 | Warning | Non-clocked sequential cell | 26 | ++-----------+----------+-----------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-17#1 Warning +Non-clocked sequential cell +The clock pin mid/SCLKCond/conditioned_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Warning +Non-clocked sequential cell +The clock pin mid/SCLKCond/counter_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Warning +Non-clocked sequential cell +The clock pin mid/SCLKCond/counter_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#4 Warning +Non-clocked sequential cell +The clock pin mid/SCLKCond/positiveedge_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#5 Warning +Non-clocked sequential cell +The clock pin mid/SCLKCond/synchronizer0_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#6 Warning +Non-clocked sequential cell +The clock pin mid/SCLKCond/synchronizer1_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#7 Warning +Non-clocked sequential cell +The clock pin mid/parallelLoadCond/conditioned_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#8 Warning +Non-clocked sequential cell +The clock pin mid/parallelLoadCond/counter_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#9 Warning +Non-clocked sequential cell +The clock pin mid/parallelLoadCond/counter_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#10 Warning +Non-clocked sequential cell +The clock pin mid/parallelLoadCond/negativeedge_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#11 Warning +Non-clocked sequential cell +The clock pin mid/parallelLoadCond/synchronizer0_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#12 Warning +Non-clocked sequential cell +The clock pin mid/parallelLoadCond/synchronizer1_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#13 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#14 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[0]_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#15 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#16 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#17 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[2]_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#18 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#19 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[3]_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#20 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#21 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#22 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[5]_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#23 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#24 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[6]_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#25 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#26 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[7]_lopt_replica/C is not reached by a timing clock +Related violations: + + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpx b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpx new file mode 100644 index 0000000..dab7510 Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpx differ diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_opt.dcp b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_opt.dcp new file mode 100644 index 0000000..8132400 Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_opt.dcp differ diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_placed.dcp b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_placed.dcp new file mode 100644 index 0000000..0154b2f Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_placed.dcp differ diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_power_routed.rpt b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_power_routed.rpt new file mode 100644 index 0000000..e060fc7 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_power_routed.rpt @@ -0,0 +1,151 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:21:15 2017 +| Host : comparch-VirtualBox running 64-bit unknown +| Command : report_power -file lab2_wrapper_power_routed.rpt -pb lab2_wrapper_power_summary_routed.pb -rpx lab2_wrapper_power_routed.rpx +| Design : lab2_wrapper +| Device : xc7z010clg400-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+-------+ +| Total On-Chip Power (W) | 0.879 | +| Dynamic (W) | 0.768 | +| Device Static (W) | 0.111 | +| Effective TJA (C/W) | 11.5 | +| Max Ambient (C) | 74.9 | +| Junction Temperature (C) | 35.1 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+-------+ + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.067 | 46 | --- | --- | +| LUT as Logic | 0.056 | 7 | 17600 | 0.04 | +| BUFG | 0.006 | 1 | 32 | 3.13 | +| Register | 0.005 | 26 | 35200 | 0.07 | +| Others | 0.000 | 8 | --- | --- | +| Signals | 0.045 | 32 | --- | --- | +| I/O | 0.657 | 16 | 100 | 16.00 | +| Static Power | 0.111 | | | | +| Total | 0.879 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.133 | 0.128 | 0.005 | +| Vccaux | 1.800 | 0.035 | 0.023 | 0.011 | +| Vcco33 | 3.300 | 0.182 | 0.181 | 0.001 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccpint | 1.000 | 0.022 | 0.000 | 0.022 | +| Vccpaux | 1.800 | 0.010 | 0.000 | 0.010 | +| Vccpll | 1.800 | 0.003 | 0.000 | 0.003 | +| Vcco_ddr | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco_mio0 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco_mio1 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 11.5 | +| Airflow (LFM) | 250 | +| Heat Sink | none | +| ThetaSA (C/W) | 0.0 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 8to11 (8 to 11 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++----------------------+-----------+ +| Name | Power (W) | ++----------------------+-----------+ +| lab2_wrapper | 0.768 | +| mid | 0.085 | +| SCLKCond | 0.039 | +| parallelLoadCond | 0.040 | +| shift | 0.006 | ++----------------------+-----------+ + + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_power_routed.rpx b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_power_routed.rpx new file mode 100644 index 0000000..017bb70 Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_power_routed.rpx differ diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_power_summary_routed.pb b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_power_summary_routed.pb new file mode 100644 index 0000000..e6aaa66 Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_power_summary_routed.pb differ diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_route_status.pb b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_route_status.pb new file mode 100644 index 0000000..c910528 Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_route_status.pb differ diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_route_status.rpt b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_route_status.rpt new file mode 100644 index 0000000..5987278 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 61 : + # of nets not needing routing.......... : 27 : + # of internally routed nets........ : 27 : + # of routable nets..................... : 34 : + # of fully routed nets............. : 34 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_routed.dcp b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_routed.dcp new file mode 100644 index 0000000..dc7b321 Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_routed.dcp differ diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_timing_summary_routed.rpt b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_timing_summary_routed.rpt new file mode 100644 index 0000000..4685ba4 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_timing_summary_routed.rpt @@ -0,0 +1,173 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:21:16 2017 +| Host : comparch-VirtualBox running 64-bit unknown +| Command : report_timing_summary -warn_on_violation -max_paths 10 -file lab2_wrapper_timing_summary_routed.rpt -rpx lab2_wrapper_timing_summary_routed.rpx +| Design : lab2_wrapper +| Device : 7z010-clg400 +| Speed File : -1 PRODUCTION 1.11 2014-09-11 +----------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 26 register/latch pins with no clock driven by root clock pin: clk (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 50 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 3 input ports with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 9 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_timing_summary_routed.rpx b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_timing_summary_routed.rpx new file mode 100644 index 0000000..deb3c04 Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_timing_summary_routed.rpx differ diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_utilization_placed.pb b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_utilization_placed.pb new file mode 100644 index 0000000..ebef8bc Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_utilization_placed.pb differ diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_utilization_placed.rpt b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_utilization_placed.rpt new file mode 100644 index 0000000..e0c9ce1 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_utilization_placed.rpt @@ -0,0 +1,204 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:20:54 2017 +| Host : comparch-VirtualBox running 64-bit Ubuntu 16.04.3 LTS +| Command : report_utilization -file lab2_wrapper_utilization_placed.rpt -pb lab2_wrapper_utilization_placed.pb +| Design : lab2_wrapper +| Device : 7z010clg400-1 +| Design State : Fully Placed +--------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 7 | 0 | 17600 | 0.04 | +| LUT as Logic | 7 | 0 | 17600 | 0.04 | +| LUT as Memory | 0 | 0 | 6000 | 0.00 | +| Slice Registers | 26 | 0 | 35200 | 0.07 | +| Register as Flip Flop | 26 | 0 | 35200 | 0.07 | +| Register as Latch | 0 | 0 | 35200 | 0.00 | +| F7 Muxes | 0 | 0 | 8800 | 0.00 | +| F8 Muxes | 0 | 0 | 4400 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 4 | Yes | Set | - | +| 22 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++-------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------------------------+------+-------+-----------+-------+ +| Slice | 7 | 0 | 4400 | 0.16 | +| SLICEL | 3 | 0 | | | +| SLICEM | 4 | 0 | | | +| LUT as Logic | 7 | 0 | 17600 | 0.04 | +| using O5 output only | 0 | | | | +| using O6 output only | 3 | | | | +| using O5 and O6 | 4 | | | | +| LUT as Memory | 0 | 0 | 6000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 6 | 0 | 17600 | 0.03 | +| fully used LUT-FF pairs | 4 | | | | +| LUT-FF pairs with one unused LUT output | 2 | | | | +| LUT-FF pairs with one unused Flip Flop | 2 | | | | +| Unique Control Sets | 2 | | | | ++-------------------------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 60 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 60 | 0.00 | +| RAMB18 | 0 | 0 | 120 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 80 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 16 | 16 | 100 | 16.00 | +| IOB Master Pads | 6 | | | | +| IOB Slave Pads | 8 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 2 | 0.00 | +| PHASER_REF | 0 | 0 | 2 | 0.00 | +| OUT_FIFO | 0 | 0 | 8 | 0.00 | +| IN_FIFO | 0 | 0 | 8 | 0.00 | +| IDELAYCTRL | 0 | 0 | 2 | 0.00 | +| IBUFDS | 0 | 0 | 96 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 | +| ILOGIC | 0 | 0 | 100 | 0.00 | +| OLOGIC | 0 | 0 | 100 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 8 | 0.00 | +| MMCME2_ADV | 0 | 0 | 2 | 0.00 | +| PLLE2_ADV | 0 | 0 | 2 | 0.00 | +| BUFMRCE | 0 | 0 | 4 | 0.00 | +| BUFHCE | 0 | 0 | 48 | 0.00 | +| BUFR | 0 | 0 | 8 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 22 | Flop & Latch | +| OBUF | 9 | IO | +| LUT4 | 6 | LUT | +| IBUF | 4 | IO | +| FDSE | 4 | Flop & Latch | +| OBUFT | 3 | IO | +| LUT5 | 2 | LUT | +| LUT3 | 2 | LUT | +| LUT2 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_5313.backup.vdi b/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_5313.backup.vdi new file mode 100644 index 0000000..0292db6 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_5313.backup.vdi @@ -0,0 +1,387 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Tue Oct 24 19:30:07 2017 +# Process ID: 5313 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1 +# Command line: vivado -log midpoint.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source midpoint.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source midpoint.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 12 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +WARNING: [Vivado 12-584] No ports matched 'sw[0]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:13] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:13] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[1]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:14] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:14] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[2]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:15] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:15] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[3]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:16] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:16] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[0]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:27] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:27] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[1]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:28] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:28] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[2]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:29] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:29] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[3]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:30] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:30] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +link_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1307.199 ; gain = 222.145 ; free physical = 80 ; free virtual = 1904 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.41 . Memory (MB): peak = 1316.203 ; gain = 9.004 ; free physical = 77 ; free virtual = 1902 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 87 ; free virtual = 1553 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.30 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 86 ; free virtual = 1553 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.32 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 85 ; free virtual = 1553 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.33 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 85 ; free virtual = 1553 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.33 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 85 ; free virtual = 1553 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 85 ; free virtual = 1553 +Ending Logic Optimization Task | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.33 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 85 ; free virtual = 1553 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 83 ; free virtual = 1552 +20 Infos, 8 Warnings, 8 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 1778.695 ; gain = 471.496 ; free physical = 82 ; free virtual = 1552 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 71 ; free virtual = 1551 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_opt.dcp' has been generated. +Command: report_drc -file midpoint_drc_opted.rpt +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_drc_opted.rpt. +report_drc completed successfully +report_drc: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 1786.699 ; gain = 8.004 ; free physical = 82 ; free virtual = 1546 +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 77 ; free virtual = 1545 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: f27d35d8 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 77 ; free virtual = 1545 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 77 ; free virtual = 1545 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15763cadc + +Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 65 ; free virtual = 1545 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1987a6687 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:02 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 76 ; free virtual = 1540 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1987a6687 + +Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:02 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 76 ; free virtual = 1540 +Phase 1 Placer Initialization | Checksum: 1987a6687 + +Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:02 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 75 ; free virtual = 1540 + +Phase 2 Global Placement +WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 15d447770 + +Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:02 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 1539 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 15d447770 + +Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:02 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 1539 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c56a8611 + +Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:02 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 1539 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1d8926030 + +Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:02 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 1539 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1d8926030 + +Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:02 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 1539 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:04 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 84 ; free virtual = 1525 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:04 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 84 ; free virtual = 1525 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:04 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 84 ; free virtual = 1525 +Phase 3 Detail Placement | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:04 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 84 ; free virtual = 1525 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:04 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 84 ; free virtual = 1525 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:04 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 81 ; free virtual = 1525 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:04 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 81 ; free virtual = 1525 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 26c736591 + +Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:04 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 81 ; free virtual = 1525 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 26c736591 + +Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:04 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 81 ; free virtual = 1525 +Ending Placer Task | Checksum: 17f82e77e + +Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:04 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 82 ; free virtual = 1527 +29 Infos, 9 Warnings, 8 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 1525 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:02 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 98 ; free virtual = 1527 +report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 103 ; free virtual = 1534 +report_control_sets: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 101 ; free virtual = 1534 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +Checksum: PlaceDB: d7bd3c54 ConstDB: 0 ShapeSum: a7c5ab2a RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 1a15202c3 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1823.699 ; gain = 37.000 ; free physical = 70 ; free virtual = 1461 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 1a15202c3 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1826.699 ; gain = 40.000 ; free physical = 85 ; free virtual = 1469 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 1a15202c3 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1826.699 ; gain = 40.000 ; free physical = 85 ; free virtual = 1469 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 1953b07aa + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 79 ; free virtual = 1464 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: a2f6b296 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 79 ; free virtual = 1465 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 79 ; free virtual = 1465 +Phase 4 Rip-up And Reroute | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 79 ; free virtual = 1465 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 79 ; free virtual = 1465 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 79 ; free virtual = 1465 +Phase 6 Post Hold Fix | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 79 ; free virtual = 1465 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0147804 % + Global Horizontal Routing Utilization = 0.0112592 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 10.2941%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 5.88235%, No Congested Regions. +Phase 7 Route finalize | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 78 ; free virtual = 1465 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1834.699 ; gain = 48.000 ; free physical = 77 ; free virtual = 1464 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: e4d20086 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1834.699 ; gain = 48.000 ; free physical = 77 ; free virtual = 1465 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1834.699 ; gain = 48.000 ; free physical = 82 ; free virtual = 1470 + +Routing Is Done. +35 Infos, 9 Warnings, 8 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1868.590 ; gain = 81.891 ; free physical = 76 ; free virtual = 1470 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1868.590 ; gain = 0.000 ; free physical = 74 ; free virtual = 1470 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_routed.dcp' has been generated. +Command: report_drc -file midpoint_drc_routed.rpt -pb midpoint_drc_routed.pb -rpx midpoint_drc_routed.rpx +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file midpoint_methodology_drc_routed.rpt -rpx midpoint_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file midpoint_power_routed.rpt -pb midpoint_power_summary_routed.pb -rpx midpoint_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +40 Infos, 10 Warnings, 8 Critical Warnings and 0 Errors encountered. +report_power completed successfully +report_power: Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:07 . Memory (MB): peak = 1928.531 ; gain = 0.000 ; free physical = 90 ; free virtual = 1333 +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Common 17-206] Exiting Vivado at Tue Oct 24 19:31:33 2017... diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_5832.backup.vdi b/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_5832.backup.vdi new file mode 100644 index 0000000..d99cdc1 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_5832.backup.vdi @@ -0,0 +1,388 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Tue Oct 24 19:40:37 2017 +# Process ID: 5832 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1 +# Command line: vivado -log midpoint.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source midpoint.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source midpoint.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 12 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +WARNING: [Vivado 12-584] No ports matched 'sw[0]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:13] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:13] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[1]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:14] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:14] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[2]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:15] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:15] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[3]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:16] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:16] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn[0]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:20] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:20] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[0]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:27] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:27] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[1]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:28] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:28] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[2]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:29] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:29] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[3]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:30] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:30] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1307.207 ; gain = 222.145 ; free physical = 78 ; free virtual = 1222 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.30 . Memory (MB): peak = 1316.211 ; gain = 9.004 ; free physical = 76 ; free virtual = 1222 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:14 . Memory (MB): peak = 1778.703 ; gain = 0.000 ; free physical = 96 ; free virtual = 797 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:14 . Memory (MB): peak = 1778.703 ; gain = 0.000 ; free physical = 94 ; free virtual = 797 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:14 . Memory (MB): peak = 1778.703 ; gain = 0.000 ; free physical = 93 ; free virtual = 797 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:14 . Memory (MB): peak = 1778.703 ; gain = 0.000 ; free physical = 92 ; free virtual = 797 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:14 . Memory (MB): peak = 1778.703 ; gain = 0.000 ; free physical = 92 ; free virtual = 797 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1778.703 ; gain = 0.000 ; free physical = 92 ; free virtual = 797 +Ending Logic Optimization Task | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:14 . Memory (MB): peak = 1778.703 ; gain = 0.000 ; free physical = 92 ; free virtual = 797 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1778.703 ; gain = 0.000 ; free physical = 89 ; free virtual = 797 +20 Infos, 9 Warnings, 9 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:41 . Memory (MB): peak = 1778.703 ; gain = 471.496 ; free physical = 86 ; free virtual = 797 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1778.703 ; gain = 0.000 ; free physical = 71 ; free virtual = 796 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_opt.dcp' has been generated. +Command: report_drc -file midpoint_drc_opted.rpt +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_drc_opted.rpt. +report_drc completed successfully +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 69 ; free virtual = 807 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: f27d35d8 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 69 ; free virtual = 807 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 69 ; free virtual = 807 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15763cadc + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.89 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 78 ; free virtual = 822 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1987a6687 + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.97 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 75 ; free virtual = 821 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1987a6687 + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.98 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 74 ; free virtual = 821 +Phase 1 Placer Initialization | Checksum: 1987a6687 + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.98 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 74 ; free virtual = 821 + +Phase 2 Global Placement +WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 15d447770 + +Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 69 ; free virtual = 820 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 15d447770 + +Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 69 ; free virtual = 820 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c56a8611 + +Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 69 ; free virtual = 820 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1d8926030 + +Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 69 ; free virtual = 820 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1d8926030 + +Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 69 ; free virtual = 820 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 84 ; free virtual = 836 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 84 ; free virtual = 836 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 84 ; free virtual = 836 +Phase 3 Detail Placement | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 84 ; free virtual = 836 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 84 ; free virtual = 836 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 84 ; free virtual = 836 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 84 ; free virtual = 836 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 26c736591 + +Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 84 ; free virtual = 836 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 26c736591 + +Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 84 ; free virtual = 836 +Ending Placer Task | Checksum: 17f82e77e + +Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 85 ; free virtual = 837 +29 Infos, 10 Warnings, 9 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 83 ; free virtual = 837 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 75 ; free virtual = 828 +report_utilization: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 82 ; free virtual = 836 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1786.707 ; gain = 0.000 ; free physical = 82 ; free virtual = 836 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +Checksum: PlaceDB: d7bd3c54 ConstDB: 0 ShapeSum: a7c5ab2a RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 1a15202c3 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:15 . Memory (MB): peak = 1823.707 ; gain = 37.000 ; free physical = 80 ; free virtual = 744 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 1a15202c3 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:16 . Memory (MB): peak = 1826.707 ; gain = 40.000 ; free physical = 69 ; free virtual = 740 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 1a15202c3 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:16 . Memory (MB): peak = 1826.707 ; gain = 40.000 ; free physical = 69 ; free virtual = 740 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 1953b07aa + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1832.707 ; gain = 46.000 ; free physical = 75 ; free virtual = 745 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: a2f6b296 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.707 ; gain = 46.000 ; free physical = 76 ; free virtual = 745 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.707 ; gain = 46.000 ; free physical = 76 ; free virtual = 746 +Phase 4 Rip-up And Reroute | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.707 ; gain = 46.000 ; free physical = 76 ; free virtual = 746 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.707 ; gain = 46.000 ; free physical = 76 ; free virtual = 746 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.707 ; gain = 46.000 ; free physical = 76 ; free virtual = 746 +Phase 6 Post Hold Fix | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.707 ; gain = 46.000 ; free physical = 76 ; free virtual = 746 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0147804 % + Global Horizontal Routing Utilization = 0.0112592 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 10.2941%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 5.88235%, No Congested Regions. +Phase 7 Route finalize | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.707 ; gain = 46.000 ; free physical = 75 ; free virtual = 746 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1834.707 ; gain = 48.000 ; free physical = 75 ; free virtual = 745 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: e4d20086 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1834.707 ; gain = 48.000 ; free physical = 75 ; free virtual = 746 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1834.707 ; gain = 48.000 ; free physical = 81 ; free virtual = 751 + +Routing Is Done. +35 Infos, 10 Warnings, 9 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:19 . Memory (MB): peak = 1868.598 ; gain = 81.891 ; free physical = 72 ; free virtual = 751 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1868.598 ; gain = 0.000 ; free physical = 70 ; free virtual = 751 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_routed.dcp' has been generated. +Command: report_drc -file midpoint_drc_routed.rpt -pb midpoint_drc_routed.pb -rpx midpoint_drc_routed.rpx +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file midpoint_methodology_drc_routed.rpt -rpx midpoint_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file midpoint_power_routed.rpt -pb midpoint_power_summary_routed.pb -rpx midpoint_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +40 Infos, 11 Warnings, 9 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Common 17-206] Exiting Vivado at Tue Oct 24 19:42:18 2017... diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_6218.backup.vdi b/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_6218.backup.vdi new file mode 100644 index 0000000..74938a4 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_6218.backup.vdi @@ -0,0 +1,400 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Tue Oct 24 19:47:26 2017 +# Process ID: 6218 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1 +# Command line: vivado -log midpoint.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source midpoint.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source midpoint.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 12 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +WARNING: [Vivado 12-584] No ports matched 'sw[0]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:13] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:13] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[1]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:14] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:14] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[2]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:15] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:15] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[3]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:16] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:16] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn[0]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:20] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:20] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn[1]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:21] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:21] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn[2]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:22] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:22] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn[3]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:23] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:23] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[0]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:27] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:27] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[1]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:28] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:28] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[2]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:29] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:29] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[3]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:30] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:30] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +link_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1307.199 ; gain = 222.145 ; free physical = 74 ; free virtual = 1217 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1316.203 ; gain = 9.004 ; free physical = 72 ; free virtual = 1215 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 91 ; free virtual = 852 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 89 ; free virtual = 852 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 89 ; free virtual = 852 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.31 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 87 ; free virtual = 852 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.31 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 87 ; free virtual = 852 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 87 ; free virtual = 852 +Ending Logic Optimization Task | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.32 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 87 ; free virtual = 852 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 84 ; free virtual = 852 +20 Infos, 12 Warnings, 12 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:32 . Memory (MB): peak = 1778.695 ; gain = 471.496 ; free physical = 80 ; free virtual = 851 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 77 ; free virtual = 826 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_opt.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:13 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 74 ; free virtual = 826 +Command: report_drc -file midpoint_drc_opted.rpt +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_drc_opted.rpt. +report_drc completed successfully +report_drc: Time (s): cpu = 00:00:01 ; elapsed = 00:00:12 . Memory (MB): peak = 1786.699 ; gain = 8.004 ; free physical = 71 ; free virtual = 840 +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 76 ; free virtual = 834 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: f27d35d8 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 76 ; free virtual = 834 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 75 ; free virtual = 834 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15763cadc + +Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:27 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 91 ; free virtual = 807 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1987a6687 + +Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:29 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 85 ; free virtual = 806 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1987a6687 + +Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:29 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 85 ; free virtual = 806 +Phase 1 Placer Initialization | Checksum: 1987a6687 + +Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:29 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 84 ; free virtual = 806 + +Phase 2 Global Placement +WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 15d447770 + +Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:31 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 77 ; free virtual = 803 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 15d447770 + +Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:31 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 77 ; free virtual = 803 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c56a8611 + +Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:31 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 77 ; free virtual = 803 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1d8926030 + +Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:31 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 77 ; free virtual = 803 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1d8926030 + +Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:31 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 77 ; free virtual = 803 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:32 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 802 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:32 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 802 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:32 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 802 +Phase 3 Detail Placement | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:32 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 802 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:32 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 802 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:32 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 802 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:32 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 72 ; free virtual = 802 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 26c736591 + +Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:32 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 72 ; free virtual = 802 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 26c736591 + +Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:32 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 72 ; free virtual = 802 +Ending Placer Task | Checksum: 17f82e77e + +Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:32 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 71 ; free virtual = 802 +29 Infos, 13 Warnings, 12 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:36 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 803 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 72 ; free virtual = 805 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 75 ; free virtual = 804 +report_utilization: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 81 ; free virtual = 812 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 81 ; free virtual = 812 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +Checksum: PlaceDB: d7bd3c54 ConstDB: 0 ShapeSum: a7c5ab2a RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 1a15202c3 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:42 . Memory (MB): peak = 1823.699 ; gain = 37.000 ; free physical = 85 ; free virtual = 684 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 1a15202c3 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:43 . Memory (MB): peak = 1826.699 ; gain = 40.000 ; free physical = 74 ; free virtual = 682 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 1a15202c3 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:43 . Memory (MB): peak = 1826.699 ; gain = 40.000 ; free physical = 74 ; free virtual = 682 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 1953b07aa + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:43 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 67 ; free virtual = 677 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: a2f6b296 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:44 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 67 ; free virtual = 679 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:44 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 67 ; free virtual = 679 +Phase 4 Rip-up And Reroute | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:44 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 67 ; free virtual = 679 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:44 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 67 ; free virtual = 679 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:44 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 67 ; free virtual = 679 +Phase 6 Post Hold Fix | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:44 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 67 ; free virtual = 679 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0147804 % + Global Horizontal Routing Utilization = 0.0112592 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 10.2941%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 5.88235%, No Congested Regions. +Phase 7 Route finalize | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:44 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 67 ; free virtual = 679 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:44 . Memory (MB): peak = 1834.699 ; gain = 48.000 ; free physical = 66 ; free virtual = 678 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: e4d20086 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:44 . Memory (MB): peak = 1834.699 ; gain = 48.000 ; free physical = 64 ; free virtual = 679 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:44 . Memory (MB): peak = 1834.699 ; gain = 48.000 ; free physical = 70 ; free virtual = 685 + +Routing Is Done. +35 Infos, 13 Warnings, 12 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:46 . Memory (MB): peak = 1868.590 ; gain = 81.891 ; free physical = 78 ; free virtual = 692 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1868.590 ; gain = 0.000 ; free physical = 83 ; free virtual = 699 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_routed.dcp' has been generated. +Command: report_drc -file midpoint_drc_routed.rpt -pb midpoint_drc_routed.pb -rpx midpoint_drc_routed.rpx +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file midpoint_methodology_drc_routed.rpt -rpx midpoint_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file midpoint_power_routed.rpt -pb midpoint_power_summary_routed.pb -rpx midpoint_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +40 Infos, 14 Warnings, 12 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Common 17-206] Exiting Vivado at Tue Oct 24 19:50:23 2017... diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_7034.backup.vdi b/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_7034.backup.vdi new file mode 100644 index 0000000..a908b21 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_7034.backup.vdi @@ -0,0 +1,454 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Tue Oct 24 20:02:36 2017 +# Process ID: 7034 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1 +# Command line: vivado -log midpoint.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source midpoint.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source midpoint.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 12 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +WARNING: [Vivado 12-584] No ports matched 'sw[0]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:13] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:13] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[1]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:14] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:14] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[2]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:15] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:15] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[3]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:16] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:16] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn[0]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:20] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:20] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn[1]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:21] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:21] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn[2]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:22] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:22] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn[3]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:23] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:23] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[0]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:27] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:27] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[1]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:28] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:28] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[2]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:29] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:29] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[3]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:30] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:30] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 1312.199 ; gain = 227.145 ; free physical = 79 ; free virtual = 1943 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.57 . Memory (MB): peak = 1324.203 ; gain = 12.004 ; free physical = 76 ; free virtual = 1942 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1786.695 ; gain = 0.000 ; free physical = 109 ; free virtual = 1534 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1786.695 ; gain = 0.000 ; free physical = 108 ; free virtual = 1534 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1786.695 ; gain = 0.000 ; free physical = 107 ; free virtual = 1534 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1786.695 ; gain = 0.000 ; free physical = 107 ; free virtual = 1534 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1786.695 ; gain = 0.000 ; free physical = 107 ; free virtual = 1534 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1786.695 ; gain = 0.000 ; free physical = 106 ; free virtual = 1534 +Ending Logic Optimization Task | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1786.695 ; gain = 0.000 ; free physical = 106 ; free virtual = 1534 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1786.695 ; gain = 0.000 ; free physical = 104 ; free virtual = 1534 +20 Infos, 12 Warnings, 12 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:22 . Memory (MB): peak = 1786.695 ; gain = 474.496 ; free physical = 104 ; free virtual = 1534 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1786.695 ; gain = 0.000 ; free physical = 92 ; free virtual = 1533 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_opt.dcp' has been generated. +Command: report_drc -file midpoint_drc_opted.rpt +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_drc_opted.rpt. +report_drc completed successfully +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 81 ; free virtual = 1525 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: f27d35d8 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 81 ; free virtual = 1525 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 80 ; free virtual = 1525 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15763cadc + +Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:01 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 1524 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 23ce6ea02 + +Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:01 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 83 ; free virtual = 1543 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 23ce6ea02 + +Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:01 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 83 ; free virtual = 1543 +Phase 1 Placer Initialization | Checksum: 23ce6ea02 + +Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:01 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 83 ; free virtual = 1543 + +Phase 2 Global Placement +Phase 2 Global Placement | Checksum: 17987845c + +Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:01 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 76 ; free virtual = 1541 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 17987845c + +Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:01 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 76 ; free virtual = 1541 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 162d53c3f + +Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:01 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 75 ; free virtual = 1541 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 177f4866c + +Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:01 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 75 ; free virtual = 1541 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 177f4866c + +Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:01 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 75 ; free virtual = 1541 + +Phase 3.5 Timing Path Optimizer +Phase 3.5 Timing Path Optimizer | Checksum: 233124ccf + +Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:01 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 75 ; free virtual = 1541 + +Phase 3.6 Small Shape Detail Placement +Phase 3.6 Small Shape Detail Placement | Checksum: 1d7b30395 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:02 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 71 ; free virtual = 1540 + +Phase 3.7 Re-assign LUT pins +Phase 3.7 Re-assign LUT pins | Checksum: 1d7b30395 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:02 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 71 ; free virtual = 1540 + +Phase 3.8 Pipeline Register Optimization +Phase 3.8 Pipeline Register Optimization | Checksum: 1d7b30395 + +Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:02 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 71 ; free virtual = 1540 +Phase 3 Detail Placement | Checksum: 1d7b30395 + +Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:02 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 71 ; free virtual = 1540 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: 1b1f92d3d + +Phase 4.1.1.1 BUFG Insertion +INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 1 CPUs +INFO: [Place 46-41] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason. +Phase 4.1.1.1 BUFG Insertion | Checksum: 1b1f92d3d + +Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:02 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 66 ; free virtual = 1540 +INFO: [Place 30-746] Post Placement Timing Summary WNS=5.664. For the most accurate timing information please run report_timing. +Phase 4.1.1 Post Placement Optimization | Checksum: 2540cdd14 + +Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:02 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 66 ; free virtual = 1540 +Phase 4.1 Post Commit Optimization | Checksum: 2540cdd14 + +Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:02 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 66 ; free virtual = 1540 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 2540cdd14 + +Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:02 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 64 ; free virtual = 1540 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 2540cdd14 + +Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:02 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 64 ; free virtual = 1540 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 232e3dea8 + +Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:02 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 64 ; free virtual = 1540 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 232e3dea8 + +Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:02 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 64 ; free virtual = 1540 +Ending Placer Task | Checksum: 1525aad13 + +Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:02 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 76 ; free virtual = 1548 +33 Infos, 12 Warnings, 12 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 75 ; free virtual = 1550 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.86 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 89 ; free virtual = 1528 +report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 92 ; free virtual = 1534 +report_control_sets: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.49 . Memory (MB): peak = 1794.699 ; gain = 0.000 ; free physical = 89 ; free virtual = 1535 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +Checksum: PlaceDB: aa9501e9 ConstDB: 0 ShapeSum: a7c5ab2a RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 10877f5e3 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 71 ; free virtual = 1435 + +Phase 2 Router Initialization + +Phase 2.1 Create Timer +Phase 2.1 Create Timer | Checksum: 10877f5e3 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 69 ; free virtual = 1435 + +Phase 2.2 Fix Topology Constraints +Phase 2.2 Fix Topology Constraints | Checksum: 10877f5e3 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 96 ; free virtual = 1445 + +Phase 2.3 Pre Route Cleanup +Phase 2.3 Pre Route Cleanup | Checksum: 10877f5e3 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 96 ; free virtual = 1445 + Number of Nodes with overlaps = 0 + +Phase 2.4 Update Timing +Phase 2.4 Update Timing | Checksum: 1b1e2f106 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 84 ; free virtual = 1441 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.594 | TNS=0.000 | WHS=-0.076 | THS=-0.844 | + +Phase 2 Router Initialization | Checksum: 1de39a806 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 82 ; free virtual = 1440 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 19cbcfada + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 78 ; free virtual = 1442 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.781 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 4.1 Global Iteration 0 | Checksum: 14dea0fea + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 78 ; free virtual = 1442 + +Phase 4.2 Global Iteration 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.781 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 4.2 Global Iteration 1 | Checksum: ff6c7ae1 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 78 ; free virtual = 1442 +Phase 4 Rip-up And Reroute | Checksum: ff6c7ae1 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 78 ; free virtual = 1442 + +Phase 5 Delay and Skew Optimization + +Phase 5.1 Delay CleanUp +Phase 5.1 Delay CleanUp | Checksum: ff6c7ae1 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 78 ; free virtual = 1442 + +Phase 5.2 Clock Skew Optimization +Phase 5.2 Clock Skew Optimization | Checksum: ff6c7ae1 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 78 ; free virtual = 1442 +Phase 5 Delay and Skew Optimization | Checksum: ff6c7ae1 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 78 ; free virtual = 1442 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: 13f0058ed + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 78 ; free virtual = 1442 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=5.934 | TNS=0.000 | WHS=0.182 | THS=0.000 | + +Phase 6.1 Hold Fix Iter | Checksum: 10c687568 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 78 ; free virtual = 1442 +Phase 6 Post Hold Fix | Checksum: 10c687568 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 78 ; free virtual = 1442 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0143581 % + Global Horizontal Routing Utilization = 0.0147059 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 7 Route finalize | Checksum: 10c687568 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 78 ; free virtual = 1442 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 10c687568 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 77 ; free virtual = 1441 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 18f291c0e + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 76 ; free virtual = 1441 + +Phase 10 Post Router Timing +INFO: [Route 35-57] Estimated Timing Summary | WNS=5.934 | TNS=0.000 | WHS=0.182 | THS=0.000 | + +INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. +Phase 10 Post Router Timing | Checksum: 18f291c0e + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 77 ; free virtual = 1442 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1857.699 ; gain = 63.000 ; free physical = 81 ; free virtual = 1447 + +Routing Is Done. +44 Infos, 12 Warnings, 12 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:18 . Memory (MB): peak = 1891.590 ; gain = 96.891 ; free physical = 71 ; free virtual = 1444 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1891.590 ; gain = 0.000 ; free physical = 66 ; free virtual = 1444 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_routed.dcp' has been generated. +Command: report_drc -file midpoint_drc_routed.rpt -pb midpoint_drc_routed.pb -rpx midpoint_drc_routed.rpx +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file midpoint_methodology_drc_routed.rpt -rpx midpoint_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file midpoint_power_routed.rpt -pb midpoint_power_summary_routed.pb -rpx midpoint_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +49 Infos, 12 Warnings, 12 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Common 17-206] Exiting Vivado at Tue Oct 24 20:04:12 2017... diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_7379.backup.vdi b/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_7379.backup.vdi new file mode 100644 index 0000000..7a98387 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_7379.backup.vdi @@ -0,0 +1,397 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Tue Oct 24 20:06:42 2017 +# Process ID: 7379 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1 +# Command line: vivado -log midpoint.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source midpoint.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source midpoint.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 12 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +WARNING: [Vivado 12-584] No ports matched 'sw[0]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:13] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:13] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[1]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:14] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:14] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[2]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:15] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:15] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw[3]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:16] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:16] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn[0]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:20] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:20] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn[1]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:21] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:21] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn[2]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:22] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:22] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn[3]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:23] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:23] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[0]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:27] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:27] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[1]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:28] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:28] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[2]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:29] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:29] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led[3]'. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:30] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc:30] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 1307.199 ; gain = 222.145 ; free physical = 195 ; free virtual = 1914 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.33 . Memory (MB): peak = 1316.203 ; gain = 9.004 ; free physical = 192 ; free virtual = 1911 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 97 ; free virtual = 1539 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 97 ; free virtual = 1540 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 97 ; free virtual = 1540 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 97 ; free virtual = 1540 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 97 ; free virtual = 1540 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 97 ; free virtual = 1540 +Ending Logic Optimization Task | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 97 ; free virtual = 1540 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 12dcb7d16 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 96 ; free virtual = 1539 +20 Infos, 12 Warnings, 12 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:20 . Memory (MB): peak = 1778.695 ; gain = 471.496 ; free physical = 96 ; free virtual = 1539 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1778.695 ; gain = 0.000 ; free physical = 93 ; free virtual = 1539 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_opt.dcp' has been generated. +Command: report_drc -file midpoint_drc_opted.rpt +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_drc_opted.rpt. +report_drc completed successfully +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 1530 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: f27d35d8 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 1530 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 1530 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 15763cadc + +Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 77 ; free virtual = 1525 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1987a6687 + +Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 76 ; free virtual = 1525 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1987a6687 + +Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 75 ; free virtual = 1525 +Phase 1 Placer Initialization | Checksum: 1987a6687 + +Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 75 ; free virtual = 1525 + +Phase 2 Global Placement +WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 15d447770 + +Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 1524 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 15d447770 + +Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 1524 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c56a8611 + +Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 1524 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1d8926030 + +Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 1524 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1d8926030 + +Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 73 ; free virtual = 1524 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 1522 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 1522 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 1522 +Phase 3 Detail Placement | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 1522 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 1522 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:02 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 1522 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 28d9c63fd + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:02 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 1522 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 26c736591 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:02 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 1522 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 26c736591 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:02 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 1522 +Ending Placer Task | Checksum: 17f82e77e + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:02 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 71 ; free virtual = 1523 +29 Infos, 13 Warnings, 12 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 1524 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.35 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 82 ; free virtual = 1515 +report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 89 ; free virtual = 1522 +report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1786.699 ; gain = 0.000 ; free physical = 89 ; free virtual = 1522 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +Checksum: PlaceDB: d7bd3c54 ConstDB: 0 ShapeSum: a7c5ab2a RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 1a15202c3 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 1823.699 ; gain = 37.000 ; free physical = 72 ; free virtual = 1430 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 1a15202c3 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 1826.699 ; gain = 40.000 ; free physical = 65 ; free virtual = 1427 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 1a15202c3 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 1826.699 ; gain = 40.000 ; free physical = 65 ; free virtual = 1427 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 1953b07aa + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 84 ; free virtual = 1422 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: a2f6b296 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 84 ; free virtual = 1422 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 83 ; free virtual = 1422 +Phase 4 Rip-up And Reroute | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 83 ; free virtual = 1422 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 83 ; free virtual = 1422 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 83 ; free virtual = 1422 +Phase 6 Post Hold Fix | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 83 ; free virtual = 1422 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0147804 % + Global Horizontal Routing Utilization = 0.0112592 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 10.2941%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 5.88235%, No Congested Regions. +Phase 7 Route finalize | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 1832.699 ; gain = 46.000 ; free physical = 83 ; free virtual = 1422 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 2e653e0c + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 1834.699 ; gain = 48.000 ; free physical = 83 ; free virtual = 1421 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: e4d20086 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 1834.699 ; gain = 48.000 ; free physical = 82 ; free virtual = 1422 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:22 . Memory (MB): peak = 1834.699 ; gain = 48.000 ; free physical = 87 ; free virtual = 1428 + +Routing Is Done. +35 Infos, 13 Warnings, 12 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:24 . Memory (MB): peak = 1868.590 ; gain = 81.891 ; free physical = 82 ; free virtual = 1428 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1868.590 ; gain = 0.000 ; free physical = 79 ; free virtual = 1428 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_routed.dcp' has been generated. +Command: report_drc -file midpoint_drc_routed.rpt -pb midpoint_drc_routed.pb -rpx midpoint_drc_routed.rpx +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file midpoint_methodology_drc_routed.rpt -rpx midpoint_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file midpoint_power_routed.rpt -pb midpoint_power_summary_routed.pb -rpx midpoint_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +40 Infos, 14 Warnings, 12 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Common 17-206] Exiting Vivado at Tue Oct 24 20:08:11 2017... diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/opt_design.pb b/Lab2Vivado/Lab2Vivado.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..7191331 Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/impl_1/opt_design.pb differ diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/place_design.pb b/Lab2Vivado/Lab2Vivado.runs/impl_1/place_design.pb new file mode 100644 index 0000000..6a1b299 Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/impl_1/place_design.pb differ diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/project.wdf b/Lab2Vivado/Lab2Vivado.runs/impl_1/project.wdf new file mode 100644 index 0000000..d569d93 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/project.wdf @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:34:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6265353433623634396233623433396462356163316236333432313231376264:506172656e742050412070726f6a656374204944:00 +eof:3924487481 diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/route_design.pb b/Lab2Vivado/Lab2Vivado.runs/impl_1/route_design.pb new file mode 100644 index 0000000..4951595 Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/impl_1/route_design.pb differ diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/rundef.js b/Lab2Vivado/Lab2Vivado.runs/impl_1/rundef.js new file mode 100644 index 0000000..4ab95d5 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/rundef.js @@ -0,0 +1,44 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/opt/Xilinx/SDK/2017.2/bin:/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2017.2/bin;"; +} else { + PathVal = "/opt/Xilinx/SDK/2017.2/bin:/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2017.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "write_bitstream", "begin" ); +ISEStep( "vivado", + "-log lab2_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/runme.bat b/Lab2Vivado/Lab2Vivado.runs/impl_1/runme.bat new file mode 100644 index 0000000..220ba68 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/runme.log b/Lab2Vivado/Lab2Vivado.runs/impl_1/runme.log new file mode 100644 index 0000000..a815d24 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/runme.log @@ -0,0 +1,421 @@ + +*** Running vivado + with args -log lab2_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace + + +****** Vivado v2017.2 (64-bit) + **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 + **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 + ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + +source lab2_wrapper.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1307.199 ; gain = 222.145 ; free physical = 162 ; free virtual = 1287 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1316.203 ; gain = 9.004 ; free physical = 159 ; free virtual = 1284 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1f6118efe + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 80 ; free virtual = 919 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1f6118efe + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 79 ; free virtual = 919 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 24777af58 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 78 ; free virtual = 918 +INFO: [Opt 31-389] Phase Sweep created 6 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 24777af58 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 78 ; free virtual = 918 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 24777af58 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 78 ; free virtual = 918 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 78 ; free virtual = 919 +Ending Logic Optimization Task | Checksum: 24777af58 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 78 ; free virtual = 919 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: a7fa1050 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 77 ; free virtual = 918 +20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:14 . Memory (MB): peak = 1772.695 ; gain = 465.496 ; free physical = 77 ; free virtual = 918 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 73 ; free virtual = 918 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_opt.dcp' has been generated. +Command: report_drc -file lab2_wrapper_drc_opted.rpt +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_opted.rpt. +report_drc completed successfully +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 84 ; free virtual = 909 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 7dc0413c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 84 ; free virtual = 909 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 84 ; free virtual = 909 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1a13da61f + +Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.80 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 77 ; free virtual = 908 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1defd2d5b + +Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.85 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 75 ; free virtual = 908 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1defd2d5b + +Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.86 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 75 ; free virtual = 908 +Phase 1 Placer Initialization | Checksum: 1defd2d5b + +Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.87 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 75 ; free virtual = 908 + +Phase 2 Global Placement +WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 1abb4e82c + +Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.98 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 72 ; free virtual = 907 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1abb4e82c + +Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.98 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 72 ; free virtual = 907 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1ad71ff1d + +Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.99 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 71 ; free virtual = 907 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 296e1b60f + +Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 71 ; free virtual = 907 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 296e1b60f + +Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 71 ; free virtual = 907 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 +Phase 3 Detail Placement | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 15b6f1084 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: b1249ec2 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: b1249ec2 + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 68 ; free virtual = 906 +Ending Placer Task | Checksum: 82161d0e + +Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 907 +31 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 909 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.31 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 90 ; free virtual = 899 +report_utilization: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 97 ; free virtual = 907 +report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 97 ; free virtual = 907 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +Checksum: PlaceDB: 76ee6c0b ConstDB: 0 ShapeSum: b27b103 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 114eef21f + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1818.699 ; gain = 38.000 ; free physical = 85 ; free virtual = 825 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 114eef21f + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1822.699 ; gain = 42.000 ; free physical = 78 ; free virtual = 821 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 114eef21f + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1822.699 ; gain = 42.000 ; free physical = 78 ; free virtual = 821 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 14284a479 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 816 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 1d66c625a + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 +Phase 4 Rip-up And Reroute | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 +Phase 6 Post Hold Fix | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0319538 % + Global Horizontal Routing Utilization = 0.0078125 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 14.4144%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. +Phase 7 Route finalize | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1827.699 ; gain = 47.000 ; free physical = 72 ; free virtual = 817 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 187ae75b7 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1829.699 ; gain = 49.000 ; free physical = 71 ; free virtual = 817 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 16e397c04 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1829.699 ; gain = 49.000 ; free physical = 71 ; free virtual = 818 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1829.699 ; gain = 49.000 ; free physical = 75 ; free virtual = 822 + +Routing Is Done. +37 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1863.590 ; gain = 82.891 ; free physical = 71 ; free virtual = 822 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1863.590 ; gain = 0.000 ; free physical = 70 ; free virtual = 823 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_routed.dcp' has been generated. +Command: report_drc -file lab2_wrapper_drc_routed.rpt -pb lab2_wrapper_drc_routed.pb -rpx lab2_wrapper_drc_routed.rpx +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file lab2_wrapper_methodology_drc_routed.rpt -rpx lab2_wrapper_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file lab2_wrapper_power_routed.rpt -pb lab2_wrapper_power_summary_routed.pb -rpx lab2_wrapper_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +42 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:21:16 2017... + +*** Running vivado + with args -log lab2_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace + + +****** Vivado v2017.2 (64-bit) + **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 + **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 + ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + +source lab2_wrapper.tcl -notrace +Command: open_checkpoint lab2_wrapper_routed.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1083.043 ; gain = 0.000 ; free physical = 489 ; free virtual = 1545 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/.Xil/Vivado-13118-comparch-VirtualBox/dcp3/lab2_wrapper.xdc] +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/.Xil/Vivado-13118-comparch-VirtualBox/dcp3/lab2_wrapper.xdc] +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1304.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 1293 +Restored from archive | CPU: 0.020000 secs | Memory: 0.048538 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1304.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 1293 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2017.2 (64-bit) build 1909853 +open_checkpoint: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1304.203 ; gain = 221.160 ; free physical = 190 ; free virtual = 1292 +Command: write_bitstream -force lab2_wrapper.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command write_bitstream +Command: report_drc (run_mandatory_drcs) for: bitstream_checks +WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./lab2_wrapper.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-186] '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Wed Oct 25 21:22:12 2017. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. +14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:16 . Memory (MB): peak = 1718.023 ; gain = 413.820 ; free physical = 375 ; free virtual = 1270 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:22:13 2017... diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/runme.sh b/Lab2Vivado/Lab2Vivado.runs/impl_1/runme.sh new file mode 100755 index 0000000..218a734 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/opt/Xilinx/SDK/2017.2/bin:/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2017.2/bin +else + PATH=/opt/Xilinx/SDK/2017.2/bin:/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2017.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64 +else + LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .write_bitstream.begin.rst +EAStep vivado -log lab2_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace + + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/usage_statistics_webtalk.html b/Lab2Vivado/Lab2Vivado.runs/impl_1/usage_statistics_webtalk.html new file mode 100644 index 0000000..ef8a692 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/usage_statistics_webtalk.html @@ -0,0 +1,468 @@ +Device Usage Statistics Report +

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version1909853
date_generatedWed Oct 25 21:22:10 2017os_platformLIN64
product_versionVivado v2017.2 (64-bit)project_idbe543b649b3b439db5ac1b63421217bd
project_iteration4random_id260071bf-5dad-4818-bd9c-a4f9ad540bfd
registration_id260071bf-5dad-4818-bd9c-a4f9ad540bfdroute_designTRUE
target_devicexc7z010target_familyzynq
target_packageclg400target_speed-1
tool_flowVivado

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Core(TM) i7-4610M CPU @ 3.00GHzcpu_speed2993.344 MHz
os_nameUbuntuos_releaseUbuntu 16.04.3 LTS
system_ram2.000 GBtotal_processors1

+ + +
vivado_usage
+ + + + + + + + + + + + + +
java_command_handlers
addsources=15autoconnecttarget=1editdelete=14launchprogramfpga=2
newproject=1openhardwaremanager=2runbitgen=11runimplementation=11
runsynthesis=25showview=15viewtaskimplementation=3viewtaskprojectmanager=3
+ + + +
other_data
guimode=4
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
project_data
constraintsetcount=1core_container=falsecurrentimplrun=impl_1currentsynthesisrun=synth_1
default_library=xil_defaultlibdesignmode=RTLexport_simulation_activehdl=0export_simulation_ies=0
export_simulation_modelsim=0export_simulation_questa=0export_simulation_riviera=0export_simulation_vcs=0
export_simulation_xsim=0implstrategy=Vivado Implementation Defaultslaunch_simulation_activehdl=0launch_simulation_ies=0
launch_simulation_modelsim=0launch_simulation_questa=0launch_simulation_riviera=0launch_simulation_vcs=0
launch_simulation_xsim=0simulator_language=Mixedsrcsetcount=4synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilogtarget_simulator=XSimtotalimplruns=1totalsynthesisruns=1
+
+ + + + +
unisim_transformation
+ + + + + + + + + + + + + + +
post_unisim_transformation
bufg=1fdre=18fdse=2gnd=4
ibuf=4lut2=1lut3=2lut4=6
lut5=2obuf=9obuft=3vcc=4
+
+ + + + + + + + + + + + + + +
pre_unisim_transformation
bufg=1fdre=18fdse=2gnd=4
ibuf=4lut2=1lut3=2lut4=6
lut5=2obuf=9obuft=3vcc=4
+

+ + + + +
report_drc
+ + + + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-messages=default::[not_specified]-name=default::[not_specified]-return_string=default::[not_specified]
-ruledecks=default::[not_specified]-upgrade_cw=default::[not_specified]-waived=default::[not_specified]
+
+ + + +
results
zps7-1=1
+

+ + + + + + + + + +
report_utilization
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
clocking
bufgctrl_available=32bufgctrl_fixed=0bufgctrl_used=1bufgctrl_util_percentage=3.13
bufhce_available=48bufhce_fixed=0bufhce_used=0bufhce_util_percentage=0.00
bufio_available=8bufio_fixed=0bufio_used=0bufio_util_percentage=0.00
bufmrce_available=4bufmrce_fixed=0bufmrce_used=0bufmrce_util_percentage=0.00
bufr_available=8bufr_fixed=0bufr_used=0bufr_util_percentage=0.00
mmcme2_adv_available=2mmcme2_adv_fixed=0mmcme2_adv_used=0mmcme2_adv_util_percentage=0.00
plle2_adv_available=2plle2_adv_fixed=0plle2_adv_used=0plle2_adv_util_percentage=0.00
+
+ + + + + + +
dsp
dsps_available=80dsps_fixed=0dsps_used=0dsps_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
io_standard
blvds_25=0diff_hstl_i=0diff_hstl_i_18=0diff_hstl_ii=0
diff_hstl_ii_18=0diff_hsul_12=0diff_mobile_ddr=0diff_sstl135=0
diff_sstl135_r=0diff_sstl15=0diff_sstl15_r=0diff_sstl18_i=0
diff_sstl18_ii=0hstl_i=0hstl_i_18=0hstl_ii=0
hstl_ii_18=0hsul_12=0lvcmos12=0lvcmos15=0
lvcmos18=0lvcmos25=0lvcmos33=1lvds_25=0
lvttl=0mini_lvds_25=0mobile_ddr=0pci33_3=0
ppds_25=0rsds_25=0sstl135=0sstl135_r=0
sstl15=0sstl15_r=0sstl18_i=0sstl18_ii=0
tmds_33=0
+
+ + + + + + + + + + + + + + +
memory
block_ram_tile_available=60block_ram_tile_fixed=0block_ram_tile_used=0block_ram_tile_util_percentage=0.00
ramb18_available=120ramb18_fixed=0ramb18_used=0ramb18_util_percentage=0.00
ramb36_fifo_available=60ramb36_fifo_fixed=0ramb36_fifo_used=0ramb36_fifo_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + +
primitives
bufg_functional_category=Clockbufg_used=1fdre_functional_category=Flop & Latchfdre_used=22
fdse_functional_category=Flop & Latchfdse_used=4ibuf_functional_category=IOibuf_used=4
lut2_functional_category=LUTlut2_used=1lut3_functional_category=LUTlut3_used=2
lut4_functional_category=LUTlut4_used=6lut5_functional_category=LUTlut5_used=2
obuf_functional_category=IOobuf_used=9obuft_functional_category=IOobuft_used=3
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
slice_logic
f7_muxes_available=8800f7_muxes_fixed=0f7_muxes_used=0f7_muxes_util_percentage=0.00
f8_muxes_available=4400f8_muxes_fixed=0f8_muxes_used=0f8_muxes_util_percentage=0.00
lut_as_logic_available=17600lut_as_logic_fixed=0lut_as_logic_used=7lut_as_logic_util_percentage=0.04
lut_as_memory_available=6000lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=35200register_as_flip_flop_fixed=0register_as_flip_flop_used=26register_as_flip_flop_util_percentage=0.07
register_as_latch_available=35200register_as_latch_fixed=0register_as_latch_used=0register_as_latch_util_percentage=0.00
slice_luts_available=17600slice_luts_fixed=0slice_luts_used=7slice_luts_util_percentage=0.04
slice_registers_available=35200slice_registers_fixed=0slice_registers_used=26slice_registers_util_percentage=0.07
fully_used_lut_ff_pairs_fixed=0.07fully_used_lut_ff_pairs_used=4lut_as_distributed_ram_fixed=0lut_as_distributed_ram_used=0
lut_as_logic_available=17600lut_as_logic_fixed=0lut_as_logic_used=7lut_as_logic_util_percentage=0.04
lut_as_memory_available=6000lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0lut_as_shift_register_used=0lut_ff_pairs_with_one_unused_flip_flop_fixed=0lut_ff_pairs_with_one_unused_flip_flop_used=2
lut_ff_pairs_with_one_unused_lut_output_fixed=2lut_ff_pairs_with_one_unused_lut_output_used=2lut_flip_flop_pairs_available=17600lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=6lut_flip_flop_pairs_util_percentage=0.03slice_available=4400slice_fixed=0
slice_used=7slice_util_percentage=0.16slicel_fixed=0slicel_used=3
slicem_fixed=0slicem_used=4unique_control_sets_used=2using_o5_and_o6_fixed=2
using_o5_and_o6_used=4using_o5_output_only_fixed=4using_o5_output_only_used=0using_o6_output_only_fixed=0
using_o6_output_only_used=3
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
specific_feature
bscane2_available=4bscane2_fixed=0bscane2_used=0bscane2_util_percentage=0.00
capturee2_available=1capturee2_fixed=0capturee2_used=0capturee2_util_percentage=0.00
dna_port_available=1dna_port_fixed=0dna_port_used=0dna_port_util_percentage=0.00
efuse_usr_available=1efuse_usr_fixed=0efuse_usr_used=0efuse_usr_util_percentage=0.00
frame_ecce2_available=1frame_ecce2_fixed=0frame_ecce2_used=0frame_ecce2_util_percentage=0.00
icape2_available=2icape2_fixed=0icape2_used=0icape2_util_percentage=0.00
startupe2_available=1startupe2_fixed=0startupe2_used=0startupe2_util_percentage=0.00
xadc_available=1xadc_fixed=0xadc_used=0xadc_util_percentage=0.00
+

+ + + +
router
+ + + + + + + + + + + + + + + + + + + + + + + + + +
usage
actual_expansions=87218bogomips=5986bram18=0bram36=0
bufg=0bufr=0ctrls=2dsp=0
effort=2estimated_expansions=33252ff=26global_clocks=1
high_fanout_nets=0iob=16lut=7movable_instances=62
nets=67pins=228pll=0router_runtime=0.000000
router_timing_driven=1threads=1timing_constraints_exist=1
+

+ + + + +
synthesis
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-assert=default::[not_specified]-bufg=default::12-cascade_dsp=default::auto-constrset=default::[not_specified]
-control_set_opt_threshold=default::auto-directive=default::default-fanout_limit=default::10000-flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto-gated_clock_conversion=default::off-generic=default::[not_specified]-include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified]-max_bram=default::-1-max_bram_cascade_height=default::-1-max_dsp=default::-1
-max_uram=default::-1-max_uram_cascade_height=default::-1-mode=default::default-name=default::[not_specified]
-no_lc=default::[not_specified]-no_srlextract=default::[not_specified]-no_timing_driven=default::[not_specified]-part=xc7z010clg400-1
-resource_sharing=default::auto-retiming=default::[not_specified]-rtl=default::[not_specified]-rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified]-seu_protect=default::none-sfcu=default::[not_specified]-shreg_min_size=default::3
-top=lab2_wrapper-verilog_define=default::[not_specified]
+
+ + + + + + +
usage
elapsed=00:00:21shls_ip=0memory_gain=382.328MBmemory_peak=1467.383MB
+

+ + diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/usage_statistics_webtalk.xml b/Lab2Vivado/Lab2Vivado.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..9fa817e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,416 @@ + + +
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+
+
+ diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou b/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou new file mode 100644 index 0000000..6358f0a --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:21:29 2017 +# Process ID: 13118 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1 +# Command line: vivado -log lab2_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.pb b/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.pb new file mode 100644 index 0000000..c8d246c Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.pb differ diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado_11694.backup.jou b/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado_11694.backup.jou new file mode 100644 index 0000000..8c6aef3 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado_11694.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:10:47 2017 +# Process ID: 11694 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1 +# Command line: vivado -log lab2_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado_13005.backup.jou b/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado_13005.backup.jou new file mode 100644 index 0000000..3e8aa15 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado_13005.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:20:09 2017 +# Process ID: 13005 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1 +# Command line: vivado -log lab2_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado_7236.backup.jou b/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado_7236.backup.jou new file mode 100644 index 0000000..219f87c --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado_7236.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 19:57:10 2017 +# Process ID: 7236 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1 +# Command line: vivado -log lab2_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado_7379.backup.jou b/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado_7379.backup.jou new file mode 100644 index 0000000..70673c6 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado_7379.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Tue Oct 24 20:06:42 2017 +# Process ID: 7379 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1 +# Command line: vivado -log midpoint.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source midpoint.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/midpoint.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source midpoint.tcl -notrace diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado_9254.backup.jou b/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado_9254.backup.jou new file mode 100644 index 0000000..b243065 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado_9254.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 20:34:16 2017 +# Process ID: 9254 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1 +# Command line: vivado -log lab2_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/lab2_wrapper.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace diff --git a/Lab2Vivado/Lab2Vivado.runs/impl_1/write_bitstream.pb b/Lab2Vivado/Lab2Vivado.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..24a632f Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/impl_1/write_bitstream.pb differ diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/.Vivado_Synthesis.queue.rst b/Lab2Vivado/Lab2Vivado.runs/synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/.Xil/lab2_wrapper_propImpl.xdc b/Lab2Vivado/Lab2Vivado.runs/synth_1/.Xil/lab2_wrapper_propImpl.xdc new file mode 100644 index 0000000..a790f8e --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/synth_1/.Xil/lab2_wrapper_propImpl.xdc @@ -0,0 +1,43 @@ +set_property SRC_FILE_INFO {cfile:/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc rfile:../../../Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L11P_T1_SRCC_35 Sch=sysclk +set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=SW0 +set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=SW1 +set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=SW2 +set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=SW3 +set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L20N_T3_34 Sch=BTN0 +set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=BTN1 +set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L18P_T2_34 Sch=BTN2 +set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=BTN3 +set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=LED0 +set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=LED1 +set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35=Sch=LED2 +set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3 +set_property src_info {type:XDC file:1 line:114 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=JE1 +set_property src_info {type:XDC file:1 line:115 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=JE2 +set_property src_info {type:XDC file:1 line:116 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=JE3 +set_property src_info {type:XDC file:1 line:117 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=JE4 +set_property src_info {type:XDC file:1 line:118 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=JE7 +set_property src_info {type:XDC file:1 line:119 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=JE8 +set_property src_info {type:XDC file:1 line:120 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=JE9 +set_property src_info {type:XDC file:1 line:121 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=JE10 diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/.vivado.begin.rst b/Lab2Vivado/Lab2Vivado.runs/synth_1/.vivado.begin.rst new file mode 100644 index 0000000..2e64ef8 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/.vivado.end.rst b/Lab2Vivado/Lab2Vivado.runs/synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/ISEWrap.js b/Lab2Vivado/Lab2Vivado.runs/synth_1/ISEWrap.js new file mode 100755 index 0000000..8284d2d --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/synth_1/ISEWrap.js @@ -0,0 +1,244 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/ISEWrap.sh b/Lab2Vivado/Lab2Vivado.runs/synth_1/ISEWrap.sh new file mode 100755 index 0000000..e1a8f5d --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/synth_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/gen_run.xml b/Lab2Vivado/Lab2Vivado.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..eafd6d3 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/synth_1/gen_run.xml @@ -0,0 +1,73 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/htr.txt b/Lab2Vivado/Lab2Vivado.runs/synth_1/htr.txt new file mode 100644 index 0000000..eb9437d --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# + +vivado -log lab2_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source lab2_wrapper.tcl diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/lab2_wrapper.dcp b/Lab2Vivado/Lab2Vivado.runs/synth_1/lab2_wrapper.dcp new file mode 100644 index 0000000..45f299a Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/synth_1/lab2_wrapper.dcp differ diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/lab2_wrapper.tcl b/Lab2Vivado/Lab2Vivado.runs/synth_1/lab2_wrapper.tcl new file mode 100644 index 0000000..0ec93ee --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/synth_1/lab2_wrapper.tcl @@ -0,0 +1,41 @@ +# +# Synthesis run script generated by Vivado +# + +set_param xicom.use_bs_reader 1 +create_project -in_memory -part xc7z010clg400-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.cache/wt [current_project] +set_property parent.project_path /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property board_part digilentinc.com:zybo:part0:1.0 [current_project] +set_property ip_output_repo /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib { + /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/inputconditioner.v + /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/shiftregister.v + /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/midpoint.v + /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/lab2wrapper.v +} +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc +set_property used_in_implementation false [get_files /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] + + +synth_design -top lab2_wrapper -part xc7z010clg400-1 + + +write_checkpoint -force -noxdef lab2_wrapper.dcp + +catch { report_utilization -file lab2_wrapper_utilization_synth.rpt -pb lab2_wrapper_utilization_synth.pb } diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/lab2_wrapper.vds b/Lab2Vivado/Lab2Vivado.runs/synth_1/lab2_wrapper.vds new file mode 100644 index 0000000..9f09044 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/synth_1/lab2_wrapper.vds @@ -0,0 +1,331 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:19:00 2017 +# Process ID: 12614 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/synth_1 +# Command line: vivado -log lab2_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source lab2_wrapper.tcl +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/synth_1/lab2_wrapper.vds +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/synth_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace +Command: synth_design -top lab2_wrapper -part xc7z010clg400-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010-clg400' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 12885 +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module inputconditioner [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/inputconditioner.v:9] +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module shiftregister [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/shiftregister.v:9] +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module inputconditioner [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/inputconditioner.v:9] +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module shiftregister [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/shiftregister.v:9] +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module midpoint [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/midpoint.v:7] +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1146.887 ; gain = 49.246 ; free physical = 309 ; free virtual = 1443 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'lab2_wrapper' [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/lab2wrapper.v:23] +INFO: [Synth 8-638] synthesizing module 'midpoint' [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/midpoint.v:7] + Parameter width bound to: 8 - type: integer +INFO: [Synth 8-638] synthesizing module 'inputconditioner' [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/inputconditioner.v:9] + Parameter counterwidth bound to: 3 - type: integer + Parameter waittime bound to: 3 - type: integer +INFO: [Synth 8-256] done synthesizing module 'inputconditioner' (1#1) [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/inputconditioner.v:9] +INFO: [Synth 8-638] synthesizing module 'shiftregister' [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/shiftregister.v:9] + Parameter width bound to: 8 - type: integer +INFO: [Synth 8-256] done synthesizing module 'shiftregister' (2#1) [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/shiftregister.v:9] +INFO: [Synth 8-256] done synthesizing module 'midpoint' (3#1) [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/midpoint.v:7] +WARNING: [Synth 8-3848] Net led in module/entity lab2_wrapper does not have driver. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/lab2wrapper.v:28] +INFO: [Synth 8-256] done synthesizing module 'lab2_wrapper' (4#1) [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/lab2wrapper.v:23] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[1] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port sw[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port sw[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[1] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1171.137 ; gain = 73.496 ; free physical = 321 ; free virtual = 1458 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1171.137 ; gain = 73.496 ; free physical = 321 ; free virtual = 1458 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/lab2_wrapper_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/lab2_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1467.375 ; gain = 0.000 ; free physical = 69 ; free virtual = 1225 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 139 ; free virtual = 1296 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z010clg400-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 139 ; free virtual = 1296 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 139 ; free virtual = 1296 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5544] ROM "conditioned" won't be mapped to Block RAM because address size (3) smaller than threshold (5) +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 131 ; free virtual = 1288 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 3 ++---Registers : + 8 Bit Registers := 1 + 3 Bit Registers := 3 + 1 Bit Registers := 15 ++---Muxes : + 2 Input 8 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 3 + 2 Input 1 Bit Muxes := 15 + 3 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module inputconditioner +Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 1 ++---Registers : + 3 Bit Registers := 1 + 1 Bit Registers := 5 ++---Muxes : + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 +Module shiftregister +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 1 ++---Muxes : + 2 Input 8 Bit Muxes := 1 + 3 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 80 (col length:40) +BRAMs: 120 (col length: RAMB18 40 RAMB36 20) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[1] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port sw[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port sw[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[1] +WARNING: [Synth 8-3332] Sequential element (mid/parallelLoadCond/positiveedge_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/synchronizer0_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/synchronizer1_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/conditioned_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/counter_reg[2]) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/counter_reg[1]) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/counter_reg[0]) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/positiveedge_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/negativeedge_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/SCLKCond/negativeedge_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/parallelLoadCond/counter_reg[2]) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/SCLKCond/counter_reg[2]) is unused and will be removed from module lab2_wrapper. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 121 ; free virtual = 1279 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 75 ; free virtual = 1154 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 75 ; free virtual = 1154 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 95 ; free virtual = 1154 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:00:36 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 95 ; free virtual = 1154 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:00:36 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 95 ; free virtual = 1154 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:00:36 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 95 ; free virtual = 1154 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:00:36 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 95 ; free virtual = 1154 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:36 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 95 ; free virtual = 1154 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:36 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 95 ; free virtual = 1154 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |BUFG | 1| +|2 |LUT2 | 1| +|3 |LUT3 | 2| +|4 |LUT4 | 6| +|5 |LUT5 | 2| +|6 |FDRE | 18| +|7 |FDSE | 2| +|8 |IBUF | 4| +|9 |OBUF | 9| +|10 |OBUFT | 3| ++------+------+------+ + +Report Instance Areas: ++------+---------------------+-------------------+------+ +| |Instance |Module |Cells | ++------+---------------------+-------------------+------+ +|1 |top | | 48| +|2 | mid |midpoint | 31| +|3 | SCLKCond |inputconditioner | 10| +|4 | parallelLoadCond |inputconditioner_0 | 11| +|5 | shift |shiftregister | 10| ++------+---------------------+-------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:36 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 95 ; free virtual = 1154 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 20 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1467.375 ; gain = 73.496 ; free physical = 154 ; free virtual = 1213 +Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:36 . Memory (MB): peak = 1467.383 ; gain = 369.734 ; free physical = 157 ; free virtual = 1216 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +20 Infos, 37 Warnings, 5 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:38 . Memory (MB): peak = 1467.383 ; gain = 382.328 ; free physical = 120 ; free virtual = 1181 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/synth_1/lab2_wrapper.dcp' has been generated. +report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1467.383 ; gain = 0.000 ; free physical = 115 ; free virtual = 1182 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:19:58 2017... diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/lab2_wrapper_utilization_synth.pb b/Lab2Vivado/Lab2Vivado.runs/synth_1/lab2_wrapper_utilization_synth.pb new file mode 100644 index 0000000..47ba740 Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/synth_1/lab2_wrapper_utilization_synth.pb differ diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/lab2_wrapper_utilization_synth.rpt b/Lab2Vivado/Lab2Vivado.runs/synth_1/lab2_wrapper_utilization_synth.rpt new file mode 100644 index 0000000..2189830 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/synth_1/lab2_wrapper_utilization_synth.rpt @@ -0,0 +1,177 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:19:57 2017 +| Host : comparch-VirtualBox running 64-bit Ubuntu 16.04.3 LTS +| Command : report_utilization -file lab2_wrapper_utilization_synth.rpt -pb lab2_wrapper_utilization_synth.pb +| Design : lab2_wrapper +| Device : 7z010clg400-1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 7 | 0 | 17600 | 0.04 | +| LUT as Logic | 7 | 0 | 17600 | 0.04 | +| LUT as Memory | 0 | 0 | 6000 | 0.00 | +| Slice Registers | 20 | 0 | 35200 | 0.06 | +| Register as Flip Flop | 20 | 0 | 35200 | 0.06 | +| Register as Latch | 0 | 0 | 35200 | 0.00 | +| F7 Muxes | 0 | 0 | 8800 | 0.00 | +| F8 Muxes | 0 | 0 | 4400 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 2 | Yes | Set | - | +| 18 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 60 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 60 | 0.00 | +| RAMB18 | 0 | 0 | 120 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 80 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 16 | 0 | 100 | 16.00 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 2 | 0.00 | +| PHASER_REF | 0 | 0 | 2 | 0.00 | +| OUT_FIFO | 0 | 0 | 8 | 0.00 | +| IN_FIFO | 0 | 0 | 8 | 0.00 | +| IDELAYCTRL | 0 | 0 | 2 | 0.00 | +| IBUFDS | 0 | 0 | 96 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 | +| ILOGIC | 0 | 0 | 100 | 0.00 | +| OLOGIC | 0 | 0 | 100 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 8 | 0.00 | +| MMCME2_ADV | 0 | 0 | 2 | 0.00 | +| PLLE2_ADV | 0 | 0 | 2 | 0.00 | +| BUFMRCE | 0 | 0 | 4 | 0.00 | +| BUFHCE | 0 | 0 | 48 | 0.00 | +| BUFR | 0 | 0 | 8 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 18 | Flop & Latch | +| OBUF | 9 | IO | +| LUT4 | 6 | LUT | +| IBUF | 4 | IO | +| OBUFT | 3 | IO | +| LUT5 | 2 | LUT | +| LUT3 | 2 | LUT | +| FDSE | 2 | Flop & Latch | +| LUT2 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/project.wdf b/Lab2Vivado/Lab2Vivado.runs/synth_1/project.wdf new file mode 100644 index 0000000..d569d93 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/synth_1/project.wdf @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:34:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6265353433623634396233623433396462356163316236333432313231376264:506172656e742050412070726f6a656374204944:00 +eof:3924487481 diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/rundef.js b/Lab2Vivado/Lab2Vivado.runs/synth_1/rundef.js new file mode 100644 index 0000000..cc9dd21 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/synth_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/opt/Xilinx/SDK/2017.2/bin:/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2017.2/bin;"; +} else { + PathVal = "/opt/Xilinx/SDK/2017.2/bin:/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2017.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log lab2_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source lab2_wrapper.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/runme.bat b/Lab2Vivado/Lab2Vivado.runs/synth_1/runme.bat new file mode 100644 index 0000000..220ba68 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/runme.log b/Lab2Vivado/Lab2Vivado.runs/synth_1/runme.log new file mode 100644 index 0000000..1f738a3 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/synth_1/runme.log @@ -0,0 +1,330 @@ + +*** Running vivado + with args -log lab2_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source lab2_wrapper.tcl + + +****** Vivado v2017.2 (64-bit) + **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 + **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 + ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + +source lab2_wrapper.tcl -notrace +Command: synth_design -top lab2_wrapper -part xc7z010clg400-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010-clg400' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 12885 +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module inputconditioner [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/inputconditioner.v:9] +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module shiftregister [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/shiftregister.v:9] +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module inputconditioner [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/inputconditioner.v:9] +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module shiftregister [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/shiftregister.v:9] +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module midpoint [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/midpoint.v:7] +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1146.887 ; gain = 49.246 ; free physical = 309 ; free virtual = 1443 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'lab2_wrapper' [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/lab2wrapper.v:23] +INFO: [Synth 8-638] synthesizing module 'midpoint' [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/midpoint.v:7] + Parameter width bound to: 8 - type: integer +INFO: [Synth 8-638] synthesizing module 'inputconditioner' [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/inputconditioner.v:9] + Parameter counterwidth bound to: 3 - type: integer + Parameter waittime bound to: 3 - type: integer +INFO: [Synth 8-256] done synthesizing module 'inputconditioner' (1#1) [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/inputconditioner.v:9] +INFO: [Synth 8-638] synthesizing module 'shiftregister' [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/shiftregister.v:9] + Parameter width bound to: 8 - type: integer +INFO: [Synth 8-256] done synthesizing module 'shiftregister' (2#1) [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/shiftregister.v:9] +INFO: [Synth 8-256] done synthesizing module 'midpoint' (3#1) [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/midpoint.v:7] +WARNING: [Synth 8-3848] Net led in module/entity lab2_wrapper does not have driver. [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/lab2wrapper.v:28] +INFO: [Synth 8-256] done synthesizing module 'lab2_wrapper' (4#1) [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/lab2wrapper.v:23] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[1] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port sw[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port sw[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[1] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1171.137 ; gain = 73.496 ; free physical = 321 ; free virtual = 1458 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1171.137 ; gain = 73.496 ; free physical = 321 ; free virtual = 1458 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/lab2_wrapper_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/lab2_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1467.375 ; gain = 0.000 ; free physical = 69 ; free virtual = 1225 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 139 ; free virtual = 1296 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z010clg400-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 139 ; free virtual = 1296 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 139 ; free virtual = 1296 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5544] ROM "conditioned" won't be mapped to Block RAM because address size (3) smaller than threshold (5) +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 131 ; free virtual = 1288 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 3 ++---Registers : + 8 Bit Registers := 1 + 3 Bit Registers := 3 + 1 Bit Registers := 15 ++---Muxes : + 2 Input 8 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 3 + 2 Input 1 Bit Muxes := 15 + 3 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module inputconditioner +Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 1 ++---Registers : + 3 Bit Registers := 1 + 1 Bit Registers := 5 ++---Muxes : + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 +Module shiftregister +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 1 ++---Muxes : + 2 Input 8 Bit Muxes := 1 + 3 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 80 (col length:40) +BRAMs: 120 (col length: RAMB18 40 RAMB36 20) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[1] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port sw[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port sw[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[1] +WARNING: [Synth 8-3332] Sequential element (mid/parallelLoadCond/positiveedge_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/synchronizer0_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/synchronizer1_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/conditioned_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/counter_reg[2]) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/counter_reg[1]) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/counter_reg[0]) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/positiveedge_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/negativeedge_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/SCLKCond/negativeedge_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/parallelLoadCond/counter_reg[2]) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/SCLKCond/counter_reg[2]) is unused and will be removed from module lab2_wrapper. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 121 ; free virtual = 1279 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 75 ; free virtual = 1154 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 75 ; free virtual = 1154 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 95 ; free virtual = 1154 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:00:36 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 95 ; free virtual = 1154 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:00:36 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 95 ; free virtual = 1154 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:00:36 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 95 ; free virtual = 1154 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:00:36 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 95 ; free virtual = 1154 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:36 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 95 ; free virtual = 1154 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:36 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 95 ; free virtual = 1154 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |BUFG | 1| +|2 |LUT2 | 1| +|3 |LUT3 | 2| +|4 |LUT4 | 6| +|5 |LUT5 | 2| +|6 |FDRE | 18| +|7 |FDSE | 2| +|8 |IBUF | 4| +|9 |OBUF | 9| +|10 |OBUFT | 3| ++------+------+------+ + +Report Instance Areas: ++------+---------------------+-------------------+------+ +| |Instance |Module |Cells | ++------+---------------------+-------------------+------+ +|1 |top | | 48| +|2 | mid |midpoint | 31| +|3 | SCLKCond |inputconditioner | 10| +|4 | parallelLoadCond |inputconditioner_0 | 11| +|5 | shift |shiftregister | 10| ++------+---------------------+-------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:36 . Memory (MB): peak = 1467.375 ; gain = 369.734 ; free physical = 95 ; free virtual = 1154 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 20 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1467.375 ; gain = 73.496 ; free physical = 154 ; free virtual = 1213 +Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:36 . Memory (MB): peak = 1467.383 ; gain = 369.734 ; free physical = 157 ; free virtual = 1216 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +20 Infos, 37 Warnings, 5 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:38 . Memory (MB): peak = 1467.383 ; gain = 382.328 ; free physical = 120 ; free virtual = 1181 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/synth_1/lab2_wrapper.dcp' has been generated. +report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1467.383 ; gain = 0.000 ; free physical = 115 ; free virtual = 1182 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:19:58 2017... diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/runme.sh b/Lab2Vivado/Lab2Vivado.runs/synth_1/runme.sh new file mode 100755 index 0000000..2bb6b8c --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/opt/Xilinx/SDK/2017.2/bin:/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2017.2/bin +else + PATH=/opt/Xilinx/SDK/2017.2/bin:/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2017.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64 +else + LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log lab2_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source lab2_wrapper.tcl diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/vivado.jou b/Lab2Vivado/Lab2Vivado.runs/synth_1/vivado.jou new file mode 100644 index 0000000..43298ab --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:19:00 2017 +# Process ID: 12614 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/synth_1 +# Command line: vivado -log lab2_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source lab2_wrapper.tcl +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/synth_1/lab2_wrapper.vds +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/Lab2Vivado/Lab2Vivado.runs/synth_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace diff --git a/Lab2Vivado/Lab2Vivado.runs/synth_1/vivado.pb b/Lab2Vivado/Lab2Vivado.runs/synth_1/vivado.pb new file mode 100644 index 0000000..041ca13 Binary files /dev/null and b/Lab2Vivado/Lab2Vivado.runs/synth_1/vivado.pb differ diff --git a/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc b/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc new file mode 100644 index 0000000..a20dc59 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc @@ -0,0 +1,146 @@ +## This file is a general .xdc for the ZYBO Rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used signals according to the project + + +##Clock signal +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L11P_T1_SRCC_35 Sch=sysclk +#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }]; + + +##Switches +set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=SW0 +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=SW1 +set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=SW2 +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=SW3 + + +##Buttons +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L20N_T3_34 Sch=BTN0 +set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=BTN1 +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L18P_T2_34 Sch=BTN2 +set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=BTN3 + + +##LEDs +set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=LED0 +set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=LED1 +set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35=Sch=LED2 +set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3 + + +##I2S Audio Codec +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports ac_bclk]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK +#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports ac_mclk]; #IO_25_34 Sch=AC_MCLK +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports ac_muten]; #IO_L23N_T3_34 Sch=AC_MUTEN +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports ac_pbdat]; #IO_L8P_T1_AD10P_35 Sch=AC_PBDAT +#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports ac_pblrc]; #IO_L11N_T1_SRCC_35 Sch=AC_PBLRC +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports ac_recdat]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports ac_reclrc]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC + + +##Audio Codec/external EEPROM IIC bus +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports ac_scl]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports ac_sda]; #IO_L23P_T3_34 Sch=AC_SDA + + +##Additional Ethernet signals +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports eth_int_b]; #IO_L6P_T0_35 Sch=ETH_INT_B +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports eth_rst_b]; #IO_L3P_T0_DQS_AD1P_35 Sch=ETH_RST_B + + +##HDMI Signals +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_n]; #IO_L13N_T2_MRCC_35 Sch=HDMI_CLK_N +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_p]; #IO_L13P_T2_MRCC_35 Sch=HDMI_CLK_P +#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[0] }]; #IO_L4N_T0_35 Sch=HDMI_D0_N +#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[0] }]; #IO_L4P_T0_35 Sch=HDMI_D0_P +#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=HDMI_D1_N +#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=HDMI_D1_P +#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=HDMI_D2_N +#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=HDMI_D2_P +#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports hdmi_cec]; #IO_L5N_T0_AD9N_35 Sch=HDMI_CEC +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports hdmi_hpd]; #IO_L5P_T0_AD9P_35 Sch=HDMI_HPD +#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports hdmi_out_en]; #IO_L6N_T0_VREF_35 Sch=HDMI_OUT_EN +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports hdmi_scl]; #IO_L16P_T2_35 Sch=HDMI_SCL +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports hdmi_sda]; #IO_L16N_T2_35 Sch=HDMI_SDA + + +##Pmod Header JA (XADC) +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja_p[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P +#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[0] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N +#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N +#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N + + +##Pmod Header JB +#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[0] }]; #IO_L15P_T2_DQS_34 Sch=JB1_p +#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[0] }]; #IO_L15N_T2_DQS_34 Sch=JB1_N +#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L16P_T2_34 Sch=JB2_P +#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L16N_T2_34 Sch=JB2_N +#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L17P_T2_34 Sch=JB3_P +#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L17N_T2_34 Sch=JB3_N +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L22P_T3_34 Sch=JB4_P +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L22N_T3_34 Sch=JB4_N + + +##Pmod Header JC +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc_p[0] }]; #IO_L10P_T1_34 Sch=JC1_P +#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc_n[0] }]; #IO_L10N_T1_34 Sch=JC1_N +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc_p[1] }]; #IO_L1P_T0_34 Sch=JC2_P +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc_n[1] }]; #IO_L1N_T0_34 Sch=JC2_N +#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc_p[2] }]; #IO_L8P_T1_34 Sch=JC3_P +#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc_n[2] }]; #IO_L8N_T1_34 Sch=JC3_N +#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc_p[3] }]; #IO_L2P_T0_34 Sch=JC4_P +#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc_n[3] }]; #IO_L2N_T0_34 Sch=JC4_N + + +##Pmod Header JD +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[0] }]; #IO_L5P_T0_34 Sch=JD1_P +#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[0] }]; #IO_L5N_T0_34 Sch=JD1_N +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[1] }]; #IO_L6P_T0_34 Sch=JD2_P +#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd_n[1] }]; #IO_L6N_T0_VREF_34 Sch=JD2_N +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[2] }]; #IO_L11P_T1_SRCC_34 Sch=JD3_P +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[2] }]; #IO_L11N_T1_SRCC_34 Sch=JD3_N +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd_p[3] }]; #IO_L21P_T3_DQS_34 Sch=JD4_P +#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd_n[3] }]; #IO_L21N_T3_DQS_34 Sch=JD4_N + + +##Pmod Header JE +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=JE1 +set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=JE2 +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=JE3 +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=JE4 +set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=JE7 +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=JE8 +set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=JE9 +set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=JE10 + + +##USB-OTG overcurrent detect pin +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports otg_oc]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=OTG_OC + + +##VGA Connector +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L7P_T1_AD2P_35 Sch=VGA_R1 +#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=VGA_R2 +#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L17P_T2_AD5P_35 Sch=VGA_R3 +#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L18N_T2_AD13N_35 Sch=VGA_R4 +#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_AD12P_35 Sch=VGA_R5 +#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=VGA_G0 +#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L14P_T2_SRCC_34 Sch=VGA_G1 +#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=VGA_G2 +#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L10N_T1_AD11N_35 Sch=VGA_G3 +#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L17N_T2_AD5N_35 Sch=VGA_G4 +#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L15N_T2_DQS_AD12N_35 Sch=VGA=G5 +#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L14N_T2_SRCC_34 Sch=VGA_B1 +#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L7N_T1_AD2N_35 Sch=VGA_B2 +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L10P_T1_AD11P_35 Sch=VGA_B3 +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=VGA_B4 +#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L18P_T2_AD13P_35 Sch=VGA_B5 +#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports vga_hs]; #IO_L13N_T2_MRCC_34 Sch=VGA_HS +#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports vga_vs]; #IO_0_34 Sch=VGA_VS diff --git a/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/inputconditioner.v b/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/inputconditioner.v new file mode 100644 index 0000000..7940cce --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/inputconditioner.v @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------ +// Input Conditioner +// 1) Synchronizes input to clock domain +// 2) Debounces input +// 3) Creates pulses at edge transitions +//------------------------------------------------------------------------ +// 50 MHz is 2 * 1-^-8 seconds per cycle + +module inputconditioner +( +input clk, // Clock domain to synchronize input to +input noisysignal, // (Potentially) noisy input signal +output reg conditioned, // Conditioned output signal +output reg positiveedge, // 1 clk pulse at rising edge of conditioned +output reg negativeedge // 1 clk pulse at falling edge of conditioned +); + + parameter counterwidth = 3; // Counter size, in bits, >= log2(waittime) (maybe this could be 2 since 2^2 > 3) + parameter waittime = 3; // Debounce delay, in clock cycles + + reg[counterwidth-1:0] counter = 0; + reg synchronizer0 = 0; + reg synchronizer1 = 0; // you need 2 synchronizers so you can calculate + and - edge + +always @(posedge clk ) begin + +if(conditioned == synchronizer1) + counter <= 0; +else begin + if(counter == waittime) begin + counter <= 0; + conditioned <= synchronizer1; + if(conditioned == 0 & synchronizer1 ==1) + positiveedge <= 1; + if(conditioned == 1 & synchronizer1 ==0) + negativeedge <= 1; + end + else + counter <= counter+1; +end // end to the else begin statement + +if(positiveedge == 1) + positiveedge <= 0; +if(negativeedge == 1) + negativeedge <= 0; + +synchronizer0 <= noisysignal; // these happen every time there's a clk edge +synchronizer1 <= synchronizer0; +end + +endmodule + diff --git a/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/lab2wrapper.v b/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/lab2wrapper.v new file mode 100644 index 0000000..0a5b4c3 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/lab2wrapper.v @@ -0,0 +1,49 @@ +//-------------------------------------------------------------------------------- +// Wrapper for Lab 0: Full Adder +// +// Rationale: +// The ZYBO board has 4 buttons, 4 switches, and 4 LEDs. +// +// This wrapper module allows for one bit to be loaded in at a time and to then show all data at once +// +// +// Usage: +// btn0 - Parallel Load +// sw0 - SerialIn +// sw1 - SCLCK +// +// Note: Buttons, switches, and LEDs have the least-significant (0) position +// on the right. +//-------------------------------------------------------------------------------- + +`timescale 1ns / 1ps +`include "midpoint.v" + + +module lab2_wrapper +( + input clk, + input [3:0] sw, // Built-in switches, used for input opA + input [3:0] btn, + output [3:0] led, // Built-in LED, used to display opA for sanity checking + output [7:0] je // Plug LD8 into JE, used to display sum, cout, overflow +); + + wire [7:0] parallelDataIn; + wire serialOut; + wire[7:0] res; + assign parallelDataIn = 8'b10010011; + assign je[7:0] = res; + assign serialOut = led[0]; + + midpoint mid(.switch0(sw[0]), .switch1(sw[1]), .button(btn[0]), .clk(clk), .parallelDataIn(parallelDataIn), .parallelDataOut2(res), .serialDataOut(serialOut)); + +endmodule + + + + + + + + diff --git a/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/midpoint.v b/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/midpoint.v new file mode 100644 index 0000000..5c003a7 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/midpoint.v @@ -0,0 +1,44 @@ +// Midpoint deliverable file + +`include "inputconditioner.v" +`include "shiftregister.v" + + +module midpoint +#(parameter width = 8) +( +input switch0, // SerialDataIn +input switch1, // peripheralClkEdge +input button, // ParallelLoad +input clk, +input [width-1:0] parallelDataIn, +output [width-1:0] parallelDataOut2, +output wire serialDataOut +); + +wire conditioned0; +wire positiveedge0; +wire negativeedge0; + +wire conditioned1; +wire positiveedge1; +wire negativeedge1; + +wire conditioned2; +wire positiveedge2; +wire negativeedge2; + + + +inputconditioner parallelLoadCond(clk, button, conditioned0, positiveedge0, negativeedge0); // negativeedge0 is your cleaned up button/ParallelLoad + +inputconditioner serialInCond(clk, switch0, conditioned1, positiveedge1, negativeedge1); // conditioned1 is your cleaned up SerialDataIn + +inputconditioner SCLKCond(clk, switch1, conditioned2, positiveedge2, negativeedge2); // positiveedge2 is your cleaned up peripheralClkEdge + +shiftregister shift(clk, positiveedge2, negativeedge0, parallelDataIn, switch0, parallelDataOut2, serialDataOut); + + +endmodule + + diff --git a/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/shiftregister.v b/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/shiftregister.v new file mode 100644 index 0000000..e8f75eb --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.srcs/sources_1/imports/Lab2/shiftregister.v @@ -0,0 +1,44 @@ +//------------------------------------------------------------------------ +// Shift Register +// Parameterized width (in bits) +// Shift register can operate in two modes: +// - serial in, parallel out +// - parallel in, serial out +//------------------------------------------------------------------------ + +module shiftregister +#(parameter width = 8) +( +input clk, // FPGA Clock +input peripheralClkEdge, // Edge indicator +input parallelLoad, // 1 = Load shift reg with parallelDataIn +input [width-1:0] parallelDataIn, // Load shift reg in parallel +input serialDataIn, // Load shift reg serially +output wire [width-1:0] parallelDataOut, // Shift reg data contents +output wire serialDataOut // Positive edge synchronized +); + +reg [width-1:0] shiftregistermem; +assign parallelDataOut = shiftregistermem; +assign serialDataOut = shiftregistermem[width-1]; + +always @(posedge clk) begin + + if(parallelLoad ==1) begin // do thisfor parallel data in + + shiftregistermem <= parallelDataIn; + //serialDataOut <= shiftregistermem[width-1]; + end + + else if(parallelLoad ==0) begin // We are deciding that parallelLoad will win. This takes priority over serial shift - peripheralClkEdge only matters if parallelLoad = 0. + if (peripheralClkEdge == 1) begin + shiftregistermem <= {shiftregistermem[width-2:0], serialDataIn}; + //parallelDataOut <= shiftregistermem; + + end + end + +end + +endmodule + diff --git a/Lab2Vivado/Lab2Vivado.xpr b/Lab2Vivado/Lab2Vivado.xpr new file mode 100644 index 0000000..76a73a7 --- /dev/null +++ b/Lab2Vivado/Lab2Vivado.xpr @@ -0,0 +1,173 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.cache/wt/gui_resources.wdf b/Lab2Vivado_FreshStart/project_2_freshstart.cache/wt/gui_resources.wdf new file mode 100644 index 0000000..4a222df --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.cache/wt/gui_resources.wdf @@ -0,0 +1,25 @@ +version:1 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+70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:70726f67726573736469616c6f675f63616e63656c:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f7265736f7572636573:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:31:00:00 +eof:822272203 diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.cache/wt/java_command_handlers.wdf b/Lab2Vivado_FreshStart/project_2_freshstart.cache/wt/java_command_handlers.wdf new file mode 100644 index 0000000..96713c7 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.cache/wt/java_command_handlers.wdf @@ -0,0 +1,10 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 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b/Lab2Vivado_FreshStart/project_2_freshstart.cache/wt/project.wpc new file mode 100644 index 0000000..3c63dc5 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.cache/wt/project.wpc @@ -0,0 +1,4 @@ +version:1 +57656254616c6b5472616e736d697373696f6e417474656d70746564:1 +6d6f64655f636f756e7465727c4755494d6f6465:1 +eof: diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.cache/wt/synthesis.wdf b/Lab2Vivado_FreshStart/project_2_freshstart.cache/wt/synthesis.wdf new file mode 100644 index 0000000..12cf5a1 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.cache/wt/synthesis.wdf @@ -0,0 +1,39 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a303130636c673430302d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 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+ + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.hw/hw_1/hw.xml b/Lab2Vivado_FreshStart/project_2_freshstart.hw/hw_1/hw.xml new file mode 100644 index 0000000..2f8d4f9 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.hw/hw_1/hw.xml @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.hw/project_2_freshstart.lpr b/Lab2Vivado_FreshStart/project_2_freshstart.hw/project_2_freshstart.lpr new file mode 100644 index 0000000..e87eed2 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.hw/project_2_freshstart.lpr @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/.jobs/vrs_config_1.xml b/Lab2Vivado_FreshStart/project_2_freshstart.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..203b09b --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/.jobs/vrs_config_2.xml b/Lab2Vivado_FreshStart/project_2_freshstart.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..9b3168b --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/.jobs/vrs_config_3.xml b/Lab2Vivado_FreshStart/project_2_freshstart.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..9d92ad4 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/.jobs/vrs_config_4.xml b/Lab2Vivado_FreshStart/project_2_freshstart.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..9d92ad4 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Vivado_Implementation.queue.rst b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Vivado_Implementation.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/.lpr b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/.lpr new file mode 100644 index 0000000..d20a952 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/.lpr @@ -0,0 +1,6 @@ + + + + + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/dcp.xml b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/dcp.xml new file mode 100644 index 0000000..baa5014 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/dcp.xml @@ -0,0 +1,24 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper.edf b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper.edf new file mode 100644 index 0000000..35d77b9 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper.edf @@ -0,0 +1,1392 @@ +(edif lab2_wrapper + (edifversion 2 0 0) + (edifLevel 0) + (keywordmap (keywordlevel 0)) +(status + (written + (timeStamp 2017 10 25 21 42 02) + (program "Vivado" (version "2017.2")) + (comment "Built on 'Thu Jun 15 18:39:10 MDT 2017'") + (comment "Built by 'xbuild'") +(metax FILE0 (string "/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/lab2wrapper.v")) +(metax FILE1 (string "/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/midpoint.v")) +(metax FILE2 (string "/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/inputconditioner.v")) +(metax FILE3 (string "/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/shiftregister.v")) + ) +) + (Library hdi_primitives + (edifLevel 0) + (technology (numberDefinition )) + (cell GND (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port G (direction OUTPUT)) + ) + ) + ) + (cell VCC (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port P (direction OUTPUT)) + ) + ) + ) + (cell IBUF (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + ) + ) + ) + (cell BUFG (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + ) + ) + ) + (cell OBUF (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + ) + ) + ) + (cell OBUFT (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I (direction INPUT)) + (port T (direction INPUT)) + ) + ) + ) + (cell LUT4 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + ) + ) + ) + (cell FDRE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port D (direction INPUT)) + (port R (direction INPUT)) + ) + ) + ) + (cell LUT3 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + ) + ) + ) + (cell LUT5 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + (port I2 (direction INPUT)) + (port I3 (direction INPUT)) + (port I4 (direction INPUT)) + ) + ) + ) + (cell LUT2 (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + ) + ) + ) + (cell FDSE (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port Q (direction OUTPUT)) + (port C (direction INPUT)) + (port CE (direction INPUT)) + (port D (direction INPUT)) + (port S (direction INPUT)) + ) + ) + ) + (cell INV (celltype GENERIC) + (view netlist (viewtype NETLIST) + (interface + (port I (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + ) + (Library work + (edifLevel 0) + (technology (numberDefinition )) + (cell inputconditioner (celltype GENERIC) + (view inputconditioner (viewtype NETLIST) + (interface + (port positiveedge2 (direction OUTPUT) + (property XLNX_LINE_FILE (integer 36866)) + ) + (port (rename sw_IBUF_0_ "sw_IBUF[0]") (direction INPUT) + (property k0 (string "wholebus^id{XLNX_LINE_FILE}") (owner "XLNX")) + (property v0 (integer 36866) (owner "XLNX")) + ) + (port clk_IBUF_BUFG (direction INPUT) + (property XLNX_LINE_FILE (integer 36866)) + ) + ) + (contents + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance conditioned_i_1__1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hCAAA")) + (property SOFT_HLUTNM (string "soft_lutpair0")) + (property XLNX_LINE_FILE (integer 110594)) + ) + (instance conditioned_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 110594)) + ) + (instance (rename counter_0__i_1 "counter[0]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h14")) + (property SOFT_HLUTNM (string "soft_lutpair1")) + (property XLNX_LINE_FILE (integer 114690)) + ) + (instance (rename counter_1__i_1 "counter[1]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0660")) + (property SOFT_HLUTNM (string "soft_lutpair1")) + (property XLNX_LINE_FILE (integer 114690)) + ) + (instance (rename counter_reg_0_ "counter_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 114690)) + ) + (instance (rename counter_reg_1_ "counter_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 114690)) + ) + (instance positiveedge_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h04000000")) + (property SOFT_HLUTNM (string "soft_lutpair0")) + (property XLNX_LINE_FILE (integer 139266)) + ) + (instance positiveedge_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 139266)) + ) + (instance synchronizer0_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 192514)) + ) + (instance synchronizer1_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 110594)) + ) + (net (rename &_const0_ "[]") (joined + (portref G (instanceref GND)) + (portref R (instanceref conditioned_reg)) + (portref R (instanceref counter_reg_0_)) + (portref R (instanceref counter_reg_1_)) + (portref R (instanceref positiveedge_reg)) + (portref R (instanceref synchronizer0_reg)) + (portref R (instanceref synchronizer1_reg)) + ) + ) + (net (rename &_const1_ "[]") (joined + (portref CE (instanceref conditioned_reg)) + (portref CE (instanceref counter_reg_0_)) + (portref CE (instanceref counter_reg_1_)) + (portref CE (instanceref positiveedge_reg)) + (portref CE (instanceref synchronizer0_reg)) + (portref CE (instanceref synchronizer1_reg)) + (portref P (instanceref VCC)) + ) + ) + (net clk_IBUF_BUFG (joined + (portref C (instanceref conditioned_reg)) + (portref C (instanceref counter_reg_0_)) + (portref C (instanceref counter_reg_1_)) + (portref C (instanceref positiveedge_reg)) + (portref C (instanceref synchronizer0_reg)) + (portref C (instanceref synchronizer1_reg)) + (portref clk_IBUF_BUFG) + ) + ) + (net conditioned_i_1__1_n_0 (joined + (portref D (instanceref conditioned_reg)) + (portref O (instanceref conditioned_i_1__1)) + ) + ) + (net conditioned_reg_n_0 (joined + (portref I0 (instanceref conditioned_i_1__1)) + (portref I1 (instanceref counter_0__i_1)) + (portref I2 (instanceref counter_1__i_1)) + (portref I2 (instanceref positiveedge_i_1)) + (portref Q (instanceref conditioned_reg)) + ) + ) + (net (rename counter_0__i_1_n_0 "counter[0]_i_1_n_0") (joined + (portref D (instanceref counter_reg_0_)) + (portref O (instanceref counter_0__i_1)) + ) + ) + (net (rename counter_1__i_1_n_0 "counter[1]_i_1_n_0") (joined + (portref D (instanceref counter_reg_1_)) + (portref O (instanceref counter_1__i_1)) + ) + ) + (net positiveedge2 (joined + (portref I0 (instanceref positiveedge_i_1)) + (portref Q (instanceref positiveedge_reg)) + (portref positiveedge2) + ) + ) + (net positiveedge_i_1_n_0 (joined + (portref D (instanceref positiveedge_reg)) + (portref O (instanceref positiveedge_i_1)) + ) + ) + (net synchronizer0_reg_n_0 (joined + (portref D (instanceref synchronizer1_reg)) + (portref Q (instanceref synchronizer0_reg)) + ) + ) + (net synchronizer1 (joined + (portref I1 (instanceref conditioned_i_1__1)) + (portref I1 (instanceref positiveedge_i_1)) + (portref I2 (instanceref counter_0__i_1)) + (portref I3 (instanceref counter_1__i_1)) + (portref Q (instanceref synchronizer1_reg)) + ) + ) + (net (rename counter "[1:0]counter") (joined) ) + (net (rename counter_0_ "counter[0]") (joined + (portref I0 (instanceref counter_0__i_1)) + (portref I1 (instanceref counter_1__i_1)) + (portref I2 (instanceref conditioned_i_1__1)) + (portref I3 (instanceref positiveedge_i_1)) + (portref Q (instanceref counter_reg_0_)) + ) + ) + (net (rename counter_1_ "counter[1]") (joined + (portref I0 (instanceref counter_1__i_1)) + (portref I3 (instanceref conditioned_i_1__1)) + (portref I4 (instanceref positiveedge_i_1)) + (portref Q (instanceref counter_reg_1_)) + ) + ) + (net (rename sw_IBUF "[0:0]sw_IBUF") (joined) ) + (net (rename sw_IBUF_0_ "sw_IBUF[0]") (joined + (portref D (instanceref synchronizer0_reg)) + (portref sw_IBUF_0_) + ) + ) + ) + + (property XLNX_LINE_FILE (integer 36866)) + ) + ) + (cell inputconditioner_0 (celltype GENERIC) + (view inputconditioner_0 (viewtype NETLIST) + (interface + (port negativeedge0 (direction OUTPUT) + (property XLNX_LINE_FILE (integer 36866)) + ) + (port shiftregistermem (direction OUTPUT) + (property XLNX_LINE_FILE (integer 36866)) + ) + (port button (direction INPUT) + (property XLNX_LINE_FILE (integer 36866)) + ) + (port clk_IBUF_BUFG (direction INPUT) + (property XLNX_LINE_FILE (integer 36866)) + ) + (port positiveedge2 (direction INPUT) + (property XLNX_LINE_FILE (integer 36866)) + ) + ) + (contents + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance conditioned_i_1 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hCAAA")) + (property SOFT_HLUTNM (string "soft_lutpair2")) + (property XLNX_LINE_FILE (integer 110594)) + ) + (instance conditioned_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 110594)) + ) + (instance (rename counter_0__i_1 "counter[0]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h14")) + (property SOFT_HLUTNM (string "soft_lutpair3")) + (property XLNX_LINE_FILE (integer 114690)) + ) + (instance (rename counter_1__i_1 "counter[1]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0660")) + (property SOFT_HLUTNM (string "soft_lutpair3")) + (property XLNX_LINE_FILE (integer 114690)) + ) + (instance (rename counter_reg_0_ "counter_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 114690)) + ) + (instance (rename counter_reg_1_ "counter_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 114690)) + ) + (instance negativeedge_i_1 (viewref netlist (cellref LUT5 (libraryref hdi_primitives))) + (property INIT (string "32'h10000000")) + (property SOFT_HLUTNM (string "soft_lutpair2")) + (property XLNX_LINE_FILE (integer 147458)) + ) + (instance negativeedge_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 147458)) + ) + (instance (rename shiftregistermem_6__i_1 "shiftregistermem[6]_i_1") (viewref netlist (cellref LUT2 (libraryref hdi_primitives))) + (property INIT (string "4'hE")) + (property XLNX_LINE_FILE (integer 90115)) + ) + (instance synchronizer0_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 192514)) + ) + (instance synchronizer1_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 110594)) + ) + (net (rename &_const0_ "[]") (joined + (portref G (instanceref GND)) + (portref R (instanceref conditioned_reg)) + (portref R (instanceref counter_reg_0_)) + (portref R (instanceref counter_reg_1_)) + (portref R (instanceref negativeedge_reg)) + (portref R (instanceref synchronizer0_reg)) + (portref R (instanceref synchronizer1_reg)) + ) + ) + (net (rename &_const1_ "[]") (joined + (portref CE (instanceref conditioned_reg)) + (portref CE (instanceref counter_reg_0_)) + (portref CE (instanceref counter_reg_1_)) + (portref CE (instanceref negativeedge_reg)) + (portref CE (instanceref synchronizer0_reg)) + (portref CE (instanceref synchronizer1_reg)) + (portref P (instanceref VCC)) + ) + ) + (net button (joined + (portref D (instanceref synchronizer0_reg)) + (portref button) + ) + ) + (net clk_IBUF_BUFG (joined + (portref C (instanceref conditioned_reg)) + (portref C (instanceref counter_reg_0_)) + (portref C (instanceref counter_reg_1_)) + (portref C (instanceref negativeedge_reg)) + (portref C (instanceref synchronizer0_reg)) + (portref C (instanceref synchronizer1_reg)) + (portref clk_IBUF_BUFG) + ) + ) + (net conditioned_i_1_n_0 (joined + (portref D (instanceref conditioned_reg)) + (portref O (instanceref conditioned_i_1)) + ) + ) + (net conditioned_reg_n_0 (joined + (portref I0 (instanceref conditioned_i_1)) + (portref I1 (instanceref counter_0__i_1)) + (portref I2 (instanceref counter_1__i_1)) + (portref I2 (instanceref negativeedge_i_1)) + (portref Q (instanceref conditioned_reg)) + ) + ) + (net (rename counter_0__i_1_n_0 "counter[0]_i_1_n_0") (joined + (portref D (instanceref counter_reg_0_)) + (portref O (instanceref counter_0__i_1)) + ) + ) + (net (rename counter_1__i_1_n_0 "counter[1]_i_1_n_0") (joined + (portref D (instanceref counter_reg_1_)) + (portref O (instanceref counter_1__i_1)) + ) + ) + (net negativeedge0 (joined + (portref I0 (instanceref negativeedge_i_1)) + (portref I0 (instanceref shiftregistermem_6__i_1)) + (portref Q (instanceref negativeedge_reg)) + (portref negativeedge0) + ) + ) + (net negativeedge_i_1_n_0 (joined + (portref D (instanceref negativeedge_reg)) + (portref O (instanceref negativeedge_i_1)) + ) + ) + (net positiveedge2 (joined + (portref I1 (instanceref shiftregistermem_6__i_1)) + (portref positiveedge2) + ) + ) + (net shiftregistermem (joined + (portref O (instanceref shiftregistermem_6__i_1)) + (portref shiftregistermem) + ) + ) + (net synchronizer0 (joined + (portref D (instanceref synchronizer1_reg)) + (portref Q (instanceref synchronizer0_reg)) + ) + ) + (net synchronizer1 (joined + (portref I1 (instanceref conditioned_i_1)) + (portref I1 (instanceref negativeedge_i_1)) + (portref I2 (instanceref counter_0__i_1)) + (portref I3 (instanceref counter_1__i_1)) + (portref Q (instanceref synchronizer1_reg)) + ) + ) + (net (rename counter "[1:0]counter") (joined) ) + (net (rename counter_0_ "counter[0]") (joined + (portref I0 (instanceref counter_0__i_1)) + (portref I1 (instanceref counter_1__i_1)) + (portref I2 (instanceref conditioned_i_1)) + (portref I3 (instanceref negativeedge_i_1)) + (portref Q (instanceref counter_reg_0_)) + ) + ) + (net (rename counter_1_ "counter[1]") (joined + (portref I0 (instanceref counter_1__i_1)) + (portref I3 (instanceref conditioned_i_1)) + (portref I4 (instanceref negativeedge_i_1)) + (portref Q (instanceref counter_reg_1_)) + ) + ) + ) + + (property ORIG_REF_NAME (string "inputconditioner")) + (property XLNX_LINE_FILE (integer 36866)) + ) + ) + (cell inputconditioner_1 (celltype GENERIC) + (view inputconditioner_1 (viewtype NETLIST) + (interface + (port conditioned1 (direction OUTPUT) + (property XLNX_LINE_FILE (integer 36866)) + ) + (port (rename sw_IBUF_0_ "sw_IBUF[0]") (direction INPUT) + (property k0 (string "wholebus^id{XLNX_LINE_FILE}") (owner "XLNX")) + (property v0 (integer 36866) (owner "XLNX")) + ) + (port clk_IBUF_BUFG (direction INPUT) + (property XLNX_LINE_FILE (integer 36866)) + ) + ) + (contents + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance conditioned_i_1__0 (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hCAAA")) + (property SOFT_HLUTNM (string "soft_lutpair4")) + (property XLNX_LINE_FILE (integer 110594)) + ) + (instance conditioned_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 110594)) + ) + (instance (rename counter_0__i_1 "counter[0]_i_1") (viewref netlist (cellref LUT3 (libraryref hdi_primitives))) + (property INIT (string "8'h14")) + (property XLNX_LINE_FILE (integer 114690)) + ) + (instance (rename counter_1__i_1 "counter[1]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'h0660")) + (property SOFT_HLUTNM (string "soft_lutpair4")) + (property XLNX_LINE_FILE (integer 114690)) + ) + (instance (rename counter_reg_0_ "counter_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 114690)) + ) + (instance (rename counter_reg_1_ "counter_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 114690)) + ) + (instance synchronizer0_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 192514)) + ) + (instance synchronizer1_reg (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 110594)) + ) + (net (rename &_const0_ "[]") (joined + (portref G (instanceref GND)) + (portref R (instanceref conditioned_reg)) + (portref R (instanceref counter_reg_0_)) + (portref R (instanceref counter_reg_1_)) + (portref R (instanceref synchronizer0_reg)) + (portref R (instanceref synchronizer1_reg)) + ) + ) + (net (rename &_const1_ "[]") (joined + (portref CE (instanceref conditioned_reg)) + (portref CE (instanceref counter_reg_0_)) + (portref CE (instanceref counter_reg_1_)) + (portref CE (instanceref synchronizer0_reg)) + (portref CE (instanceref synchronizer1_reg)) + (portref P (instanceref VCC)) + ) + ) + (net clk_IBUF_BUFG (joined + (portref C (instanceref conditioned_reg)) + (portref C (instanceref counter_reg_0_)) + (portref C (instanceref counter_reg_1_)) + (portref C (instanceref synchronizer0_reg)) + (portref C (instanceref synchronizer1_reg)) + (portref clk_IBUF_BUFG) + ) + ) + (net conditioned1 (joined + (portref I0 (instanceref conditioned_i_1__0)) + (portref I1 (instanceref counter_0__i_1)) + (portref I2 (instanceref counter_1__i_1)) + (portref Q (instanceref conditioned_reg)) + (portref conditioned1) + ) + ) + (net conditioned_i_1__0_n_0 (joined + (portref D (instanceref conditioned_reg)) + (portref O (instanceref conditioned_i_1__0)) + ) + ) + (net (rename counter_0__i_1_n_0 "counter[0]_i_1_n_0") (joined + (portref D (instanceref counter_reg_0_)) + (portref O (instanceref counter_0__i_1)) + ) + ) + (net (rename counter_1__i_1_n_0 "counter[1]_i_1_n_0") (joined + (portref D (instanceref counter_reg_1_)) + (portref O (instanceref counter_1__i_1)) + ) + ) + (net synchronizer0_reg_n_0 (joined + (portref D (instanceref synchronizer1_reg)) + (portref Q (instanceref synchronizer0_reg)) + ) + ) + (net synchronizer1 (joined + (portref I1 (instanceref conditioned_i_1__0)) + (portref I2 (instanceref counter_0__i_1)) + (portref I3 (instanceref counter_1__i_1)) + (portref Q (instanceref synchronizer1_reg)) + ) + ) + (net (rename counter "[1:0]counter") (joined) ) + (net (rename counter_0_ "counter[0]") (joined + (portref I0 (instanceref counter_0__i_1)) + (portref I1 (instanceref counter_1__i_1)) + (portref I2 (instanceref conditioned_i_1__0)) + (portref Q (instanceref counter_reg_0_)) + ) + ) + (net (rename counter_1_ "counter[1]") (joined + (portref I0 (instanceref counter_1__i_1)) + (portref I3 (instanceref conditioned_i_1__0)) + (portref Q (instanceref counter_reg_1_)) + ) + ) + (net (rename sw_IBUF "[0:0]sw_IBUF") (joined) ) + (net (rename sw_IBUF_0_ "sw_IBUF[0]") (joined + (portref D (instanceref synchronizer0_reg)) + (portref sw_IBUF_0_) + ) + ) + ) + + (property ORIG_REF_NAME (string "inputconditioner")) + (property XLNX_LINE_FILE (integer 36866)) + ) + ) + (cell shiftregister (celltype GENERIC) + (view shiftregister (viewtype NETLIST) + (interface + (port (array (rename je_OBUF "je_OBUF[7:0]") 8) (direction OUTPUT) + (property k0 (string "wholebus^id{XLNX_LINE_FILE}") (owner "XLNX")) + (property v0 (integer 36867) (owner "XLNX")) + ) + (port negativeedge0 (direction INPUT) + (property XLNX_LINE_FILE (integer 36867)) + ) + (port shiftregistermem (direction INPUT) + (property XLNX_LINE_FILE (integer 36867)) + ) + (port clk_IBUF_BUFG (direction INPUT) + (property XLNX_LINE_FILE (integer 36867)) + ) + (port conditioned1 (direction INPUT) + (property XLNX_LINE_FILE (integer 36867)) + ) + (port positiveedge2 (direction INPUT) + (property XLNX_LINE_FILE (integer 36867)) + ) + (port lopt (direction OUTPUT)) + (port lopt_1 (direction OUTPUT)) + (port lopt_2 (direction OUTPUT)) + (port lopt_3 (direction OUTPUT)) + (port lopt_4 (direction OUTPUT)) + (port lopt_5 (direction OUTPUT)) + ) + (contents + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance (rename shiftregistermem_0__i_1 "shiftregistermem[0]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFCFA")) + (property SOFT_HLUTNM (string "soft_lutpair5")) + (property XLNX_LINE_FILE (integer 90115)) + ) + (instance (rename shiftregistermem_1__i_1 "shiftregistermem[1]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFCFA")) + (property SOFT_HLUTNM (string "soft_lutpair5")) + (property XLNX_LINE_FILE (integer 90115)) + ) + (instance (rename shiftregistermem_4__i_1 "shiftregistermem[4]_i_1") (viewref netlist (cellref LUT4 (libraryref hdi_primitives))) + (property INIT (string "16'hFCFA")) + (property XLNX_LINE_FILE (integer 90115)) + ) + (instance (rename shiftregistermem_reg_0_ "shiftregistermem_reg[0]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 90115)) + ) + (instance (rename shiftregistermem_reg_1_ "shiftregistermem_reg[1]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 90115)) + ) + (instance (rename shiftregistermem_reg_2_ "shiftregistermem_reg[2]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 90115)) + ) + (instance (rename shiftregistermem_reg_2__lopt_replica "shiftregistermem_reg[2]_lopt_replica") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 90115)) + ) + (instance (rename shiftregistermem_reg_3_ "shiftregistermem_reg[3]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 90115)) + ) + (instance (rename shiftregistermem_reg_3__lopt_replica "shiftregistermem_reg[3]_lopt_replica") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 90115)) + ) + (instance (rename shiftregistermem_reg_4_ "shiftregistermem_reg[4]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 90115)) + ) + (instance (rename shiftregistermem_reg_5_ "shiftregistermem_reg[5]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 90115)) + ) + (instance (rename shiftregistermem_reg_5__lopt_replica "shiftregistermem_reg[5]_lopt_replica") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 90115)) + ) + (instance (rename shiftregistermem_reg_6_ "shiftregistermem_reg[6]") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 90115)) + ) + (instance (rename shiftregistermem_reg_6__lopt_replica "shiftregistermem_reg[6]_lopt_replica") (viewref netlist (cellref FDRE (libraryref hdi_primitives))) + (property INIT (string "1'b0")) + (property XLNX_LINE_FILE (integer 90115)) + ) + (instance (rename shiftregistermem_reg_7_ "shiftregistermem_reg[7]") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + (property XLNX_LINE_FILE (integer 90115)) + ) + (instance (rename shiftregistermem_reg_7__lopt_replica "shiftregistermem_reg[7]_lopt_replica") (viewref netlist (cellref FDSE (libraryref hdi_primitives))) + (property INIT (string "1'b1")) + (property XLNX_LINE_FILE (integer 90115)) + ) + (net (rename &_const0_ "[]") (joined + (portref G (instanceref GND)) + (portref R (instanceref shiftregistermem_reg_0_)) + (portref R (instanceref shiftregistermem_reg_1_)) + (portref R (instanceref shiftregistermem_reg_4_)) + ) + ) + (net (rename &_const1_ "[]") (joined + (portref CE (instanceref shiftregistermem_reg_0_)) + (portref CE (instanceref shiftregistermem_reg_1_)) + (portref CE (instanceref shiftregistermem_reg_4_)) + (portref P (instanceref VCC)) + ) + ) + (net clk_IBUF_BUFG (joined + (portref C (instanceref shiftregistermem_reg_0_)) + (portref C (instanceref shiftregistermem_reg_1_)) + (portref C (instanceref shiftregistermem_reg_2_)) + (portref C (instanceref shiftregistermem_reg_2__lopt_replica)) + (portref C (instanceref shiftregistermem_reg_3_)) + (portref C (instanceref shiftregistermem_reg_3__lopt_replica)) + (portref C (instanceref shiftregistermem_reg_4_)) + (portref C (instanceref shiftregistermem_reg_5_)) + (portref C (instanceref shiftregistermem_reg_5__lopt_replica)) + (portref C (instanceref shiftregistermem_reg_6_)) + (portref C (instanceref shiftregistermem_reg_6__lopt_replica)) + (portref C (instanceref shiftregistermem_reg_7_)) + (portref C (instanceref shiftregistermem_reg_7__lopt_replica)) + (portref clk_IBUF_BUFG) + ) + ) + (net conditioned1 (joined + (portref I1 (instanceref shiftregistermem_0__i_1)) + (portref conditioned1) + ) + ) + (net negativeedge0 (joined + (portref I2 (instanceref shiftregistermem_0__i_1)) + (portref I2 (instanceref shiftregistermem_1__i_1)) + (portref I2 (instanceref shiftregistermem_4__i_1)) + (portref R (instanceref shiftregistermem_reg_2_)) + (portref R (instanceref shiftregistermem_reg_2__lopt_replica)) + (portref R (instanceref shiftregistermem_reg_3_)) + (portref R (instanceref shiftregistermem_reg_3__lopt_replica)) + (portref R (instanceref shiftregistermem_reg_5_)) + (portref R (instanceref shiftregistermem_reg_5__lopt_replica)) + (portref R (instanceref shiftregistermem_reg_6_)) + (portref R (instanceref shiftregistermem_reg_6__lopt_replica)) + (portref S (instanceref shiftregistermem_reg_7_)) + (portref S (instanceref shiftregistermem_reg_7__lopt_replica)) + (portref negativeedge0) + ) + ) + (net positiveedge2 (joined + (portref I3 (instanceref shiftregistermem_0__i_1)) + (portref I3 (instanceref shiftregistermem_1__i_1)) + (portref I3 (instanceref shiftregistermem_4__i_1)) + (portref positiveedge2) + ) + ) + (net shiftregistermem (joined + (portref CE (instanceref shiftregistermem_reg_2_)) + (portref CE (instanceref shiftregistermem_reg_2__lopt_replica)) + (portref CE (instanceref shiftregistermem_reg_3_)) + (portref CE (instanceref shiftregistermem_reg_3__lopt_replica)) + (portref CE (instanceref shiftregistermem_reg_5_)) + (portref CE (instanceref shiftregistermem_reg_5__lopt_replica)) + (portref CE (instanceref shiftregistermem_reg_6_)) + (portref CE (instanceref shiftregistermem_reg_6__lopt_replica)) + (portref CE (instanceref shiftregistermem_reg_7_)) + (portref CE (instanceref shiftregistermem_reg_7__lopt_replica)) + (portref shiftregistermem) + ) + ) + (net (rename shiftregistermem_0__i_1_n_0 "shiftregistermem[0]_i_1_n_0") (joined + (portref D (instanceref shiftregistermem_reg_0_)) + (portref O (instanceref shiftregistermem_0__i_1)) + ) + ) + (net (rename shiftregistermem_1__i_1_n_0 "shiftregistermem[1]_i_1_n_0") (joined + (portref D (instanceref shiftregistermem_reg_1_)) + (portref O (instanceref shiftregistermem_1__i_1)) + ) + ) + (net (rename shiftregistermem_4__i_1_n_0 "shiftregistermem[4]_i_1_n_0") (joined + (portref D (instanceref shiftregistermem_reg_4_)) + (portref O (instanceref shiftregistermem_4__i_1)) + ) + ) + (net (rename shiftregistermem_reg_2__lopt_replica_1 "shiftregistermem_reg[2]_lopt_replica_1") (joined + (portref Q (instanceref shiftregistermem_reg_2__lopt_replica)) + (portref lopt) + ) + ) + (net (rename shiftregistermem_reg_3__lopt_replica_1 "shiftregistermem_reg[3]_lopt_replica_1") (joined + (portref Q (instanceref shiftregistermem_reg_3__lopt_replica)) + (portref lopt_1) + ) + ) + (net (rename shiftregistermem_reg_5__lopt_replica_1 "shiftregistermem_reg[5]_lopt_replica_1") (joined + (portref Q (instanceref shiftregistermem_reg_5__lopt_replica)) + (portref lopt_2) + ) + ) + (net (rename shiftregistermem_reg_6__lopt_replica_1 "shiftregistermem_reg[6]_lopt_replica_1") (joined + (portref Q (instanceref shiftregistermem_reg_6__lopt_replica)) + (portref lopt_3) + ) + ) + (net (rename shiftregistermem_reg_7__lopt_replica_1 "shiftregistermem_reg[7]_lopt_replica_1") (joined + (portref Q (instanceref shiftregistermem_reg_7__lopt_replica)) + (portref lopt_4) + ) + ) + (net (rename je_OBUF "[7:0]je_OBUF") (joined) ) + (net (rename je_OBUF_0_ "je_OBUF[0]") (joined + (portref I0 (instanceref shiftregistermem_0__i_1)) + (portref I1 (instanceref shiftregistermem_1__i_1)) + (portref Q (instanceref shiftregistermem_reg_0_)) + (portref (member je_OBUF 7)) + ) + ) + (net (rename je_OBUF_1_ "je_OBUF[1]") (joined + (portref D (instanceref shiftregistermem_reg_2_)) + (portref D (instanceref shiftregistermem_reg_2__lopt_replica)) + (portref I0 (instanceref shiftregistermem_1__i_1)) + (portref Q (instanceref shiftregistermem_reg_1_)) + (portref (member je_OBUF 6)) + ) + ) + (net (rename je_OBUF_2_ "je_OBUF[2]") (joined + (portref D (instanceref shiftregistermem_reg_3_)) + (portref D (instanceref shiftregistermem_reg_3__lopt_replica)) + (portref Q (instanceref shiftregistermem_reg_2_)) + (portref (member je_OBUF 5)) + ) + ) + (net (rename je_OBUF_3_ "je_OBUF[3]") (joined + (portref I1 (instanceref shiftregistermem_4__i_1)) + (portref Q (instanceref shiftregistermem_reg_3_)) + (portref (member je_OBUF 4)) + ) + ) + (net (rename je_OBUF_4_ "je_OBUF[4]") (joined + (portref D (instanceref shiftregistermem_reg_5_)) + (portref D (instanceref shiftregistermem_reg_5__lopt_replica)) + (portref I0 (instanceref shiftregistermem_4__i_1)) + (portref Q (instanceref shiftregistermem_reg_4_)) + (portref (member je_OBUF 3)) + ) + ) + (net (rename je_OBUF_5_ "je_OBUF[5]") (joined + (portref D (instanceref shiftregistermem_reg_6_)) + (portref D (instanceref shiftregistermem_reg_6__lopt_replica)) + (portref Q (instanceref shiftregistermem_reg_5_)) + (portref (member je_OBUF 2)) + ) + ) + (net (rename je_OBUF_6_ "je_OBUF[6]") (joined + (portref D (instanceref shiftregistermem_reg_7_)) + (portref D (instanceref shiftregistermem_reg_7__lopt_replica)) + (portref Q (instanceref shiftregistermem_reg_6_)) + (portref (member je_OBUF 1)) + ) + ) + (net (rename je_OBUF_7_ "je_OBUF[7]") (joined + (portref Q (instanceref shiftregistermem_reg_7_)) + (portref (member je_OBUF 0)) + ) + ) + ) + + (property XLNX_LINE_FILE (integer 36867)) + ) + ) + (cell midpoint (celltype GENERIC) + (view midpoint (viewtype NETLIST) + (interface + (port (array (rename je_OBUF "je_OBUF[7:0]") 8) (direction OUTPUT) + (property k0 (string "wholebus^id{XLNX_LINE_FILE}") (owner "XLNX")) + (property v0 (integer 28673) (owner "XLNX")) + ) + (port button (direction INPUT) + (property XLNX_LINE_FILE (integer 28673)) + ) + (port clk_IBUF_BUFG (direction INPUT) + (property XLNX_LINE_FILE (integer 28673)) + ) + (port (array (rename sw_IBUF "sw_IBUF[1:0]") 2) (direction INPUT) + (property k0 (string "wholebus^id{XLNX_LINE_FILE}") (owner "XLNX")) + (property v0 (integer 28673) (owner "XLNX")) + ) + (port lopt (direction OUTPUT)) + (port lopt_1 (direction OUTPUT)) + (port lopt_2 (direction OUTPUT)) + (port lopt_3 (direction OUTPUT)) + (port lopt_4 (direction OUTPUT)) + (port lopt_5 (direction OUTPUT)) + ) + (contents + (instance SCLKCond (viewref inputconditioner (cellref inputconditioner (libraryref work))) + (property XLNX_LINE_FILE (integer 151553)) + ) + (instance parallelLoadCond (viewref inputconditioner_0 (cellref inputconditioner_0 (libraryref work))) + (property XLNX_LINE_FILE (integer 135169)) + ) + (instance serialInCond (viewref inputconditioner_1 (cellref inputconditioner_1 (libraryref work))) + (property XLNX_LINE_FILE (integer 143361)) + ) + (instance shift (viewref shiftregister (cellref shiftregister (libraryref work))) + (property XLNX_LINE_FILE (integer 159745)) + ) + (net button (joined + (portref button (instanceref parallelLoadCond)) + (portref button) + ) + ) + (net clk_IBUF_BUFG (joined + (portref clk_IBUF_BUFG (instanceref SCLKCond)) + (portref clk_IBUF_BUFG (instanceref parallelLoadCond)) + (portref clk_IBUF_BUFG (instanceref serialInCond)) + (portref clk_IBUF_BUFG (instanceref shift)) + (portref clk_IBUF_BUFG) + ) + ) + (net conditioned1 (joined + (portref conditioned1 (instanceref serialInCond)) + (portref conditioned1 (instanceref shift)) + ) + ) + (net lopt (joined + (portref lopt (instanceref shift)) + (portref lopt) + ) + ) + (net lopt_1 (joined + (portref lopt_1 (instanceref shift)) + (portref lopt_1) + ) + ) + (net lopt_2 (joined + (portref lopt_2 (instanceref shift)) + (portref lopt_2) + ) + ) + (net lopt_3 (joined + (portref lopt_3 (instanceref shift)) + (portref lopt_3) + ) + ) + (net lopt_4 (joined + (portref lopt_4 (instanceref shift)) + (portref lopt_4) + ) + ) + (net lopt_5 (joined + (portref lopt_5) + ) + ) + (net negativeedge0 (joined + (portref negativeedge0 (instanceref parallelLoadCond)) + (portref negativeedge0 (instanceref shift)) + ) + ) + (net positiveedge2 (joined + (portref positiveedge2 (instanceref SCLKCond)) + (portref positiveedge2 (instanceref parallelLoadCond)) + (portref positiveedge2 (instanceref shift)) + ) + ) + (net shiftregistermem (joined + (portref shiftregistermem (instanceref parallelLoadCond)) + (portref shiftregistermem (instanceref shift)) + ) + ) + (net (rename je_OBUF "[7:0]je_OBUF") (joined) ) + (net (rename je_OBUF_0_ "je_OBUF[0]") (joined + (portref (member je_OBUF 7) (instanceref shift)) + (portref (member je_OBUF 7)) + ) + ) + (net (rename je_OBUF_1_ "je_OBUF[1]") (joined + (portref (member je_OBUF 6) (instanceref shift)) + (portref (member je_OBUF 6)) + ) + ) + (net (rename je_OBUF_2_ "je_OBUF[2]") (joined + (portref (member je_OBUF 5) (instanceref shift)) + (portref (member je_OBUF 5)) + ) + ) + (net (rename je_OBUF_3_ "je_OBUF[3]") (joined + (portref (member je_OBUF 4) (instanceref shift)) + (portref (member je_OBUF 4)) + ) + ) + (net (rename je_OBUF_4_ "je_OBUF[4]") (joined + (portref (member je_OBUF 3) (instanceref shift)) + (portref (member je_OBUF 3)) + ) + ) + (net (rename je_OBUF_5_ "je_OBUF[5]") (joined + (portref (member je_OBUF 2) (instanceref shift)) + (portref (member je_OBUF 2)) + ) + ) + (net (rename je_OBUF_6_ "je_OBUF[6]") (joined + (portref (member je_OBUF 1) (instanceref shift)) + (portref (member je_OBUF 1)) + ) + ) + (net (rename je_OBUF_7_ "je_OBUF[7]") (joined + (portref (member je_OBUF 0) (instanceref shift)) + (portref (member je_OBUF 0)) + ) + ) + (net (rename sw_IBUF "[1:0]sw_IBUF") (joined) ) + (net (rename sw_IBUF_0_ "sw_IBUF[0]") (joined + (portref sw_IBUF_0_ (instanceref serialInCond)) + (portref (member sw_IBUF 1)) + ) + ) + (net (rename sw_IBUF_1_ "sw_IBUF[1]") (joined + (portref sw_IBUF_0_ (instanceref SCLKCond)) + (portref (member sw_IBUF 0)) + ) + ) + ) + + (property XLNX_LINE_FILE (integer 28673)) + ) + ) + (cell lab2_wrapper (celltype GENERIC) + (view lab2_wrapper (viewtype NETLIST) + (interface + (port clk (direction INPUT) + (property XLNX_LINE_FILE (integer 94208)) + ) + (port (array (rename sw "sw[3:0]") 4) (direction INPUT) + (property k0 (string "idx+3id{IOSTANDARD}") (owner "XLNX")) + (property v0 (string "LVCMOS33") (owner "XLNX")) + (property k1 (string "idx+2id{IOSTANDARD}") (owner "XLNX")) + (property v1 (string "LVCMOS33") (owner "XLNX")) + (property k2 (string "wholebus^id{XLNX_LINE_FILE}") (owner "XLNX")) + (property v2 (integer 94208) (owner "XLNX")) + ) + (port (array (rename btn "btn[3:0]") 4) (direction INPUT) + (property k0 (string "idx+3id{IOSTANDARD}") (owner "XLNX")) + (property v0 (string "LVCMOS33") (owner "XLNX")) + (property k1 (string "idx+2id{IOSTANDARD}") (owner "XLNX")) + (property v1 (string "LVCMOS33") (owner "XLNX")) + (property k2 (string "idx+1id{IOSTANDARD}") (owner "XLNX")) + (property v2 (string "LVCMOS33") (owner "XLNX")) + (property k3 (string "wholebus^id{XLNX_LINE_FILE}") (owner "XLNX")) + (property v3 (integer 94208) (owner "XLNX")) + ) + (port (array (rename led "led[3:0]") 4) (direction OUTPUT) + (property k0 (string "wholebus^id{XLNX_LINE_FILE}") (owner "XLNX")) + (property v0 (integer 94208) (owner "XLNX")) + ) + (port (array (rename je "je[7:0]") 8) (direction OUTPUT) + (property k0 (string "wholebus^id{XLNX_LINE_FILE}") (owner "XLNX")) + (property v0 (integer 94208) (owner "XLNX")) + ) + ) + (contents + (instance GND (viewref netlist (cellref GND (libraryref hdi_primitives)))) + (instance VCC (viewref netlist (cellref VCC (libraryref hdi_primitives)))) + (instance (rename btn_IBUF_0__inst "btn_IBUF[0]_inst") (viewref netlist (cellref IBUF (libraryref hdi_primitives))) + (property XLNX_LINE_FILE (integer 94208)) + ) + (instance clk_IBUF_BUFG_inst (viewref netlist (cellref BUFG (libraryref hdi_primitives))) + (property XLNX_LINE_FILE (integer 94208)) + ) + (instance clk_IBUF_inst (viewref netlist (cellref IBUF (libraryref hdi_primitives))) + (property XLNX_LINE_FILE (integer 94208)) + ) + (instance (rename je_OBUF_0__inst "je_OBUF[0]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XLNX_LINE_FILE (integer 94208)) + ) + (instance (rename je_OBUF_1__inst "je_OBUF[1]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XLNX_LINE_FILE (integer 94208)) + ) + (instance (rename je_OBUF_2__inst "je_OBUF[2]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XLNX_LINE_FILE (integer 94208)) + ) + (instance (rename je_OBUF_3__inst "je_OBUF[3]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XLNX_LINE_FILE (integer 94208)) + ) + (instance (rename je_OBUF_4__inst "je_OBUF[4]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XLNX_LINE_FILE (integer 94208)) + ) + (instance (rename je_OBUF_5__inst "je_OBUF[5]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XLNX_LINE_FILE (integer 94208)) + ) + (instance (rename je_OBUF_6__inst "je_OBUF[6]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XLNX_LINE_FILE (integer 94208)) + ) + (instance (rename je_OBUF_7__inst "je_OBUF[7]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XLNX_LINE_FILE (integer 94208)) + ) + (instance (rename led_OBUF_0__inst "led_OBUF[0]_inst") (viewref netlist (cellref OBUF (libraryref hdi_primitives))) + (property XLNX_LINE_FILE (integer 94208)) + ) + (instance (rename led_OBUF_1__inst "led_OBUF[1]_inst") (viewref netlist (cellref OBUFT (libraryref hdi_primitives))) + (property XLNX_LINE_FILE (integer 94208)) + ) + (instance (rename led_OBUF_2__inst "led_OBUF[2]_inst") (viewref netlist (cellref OBUFT (libraryref hdi_primitives))) + (property XLNX_LINE_FILE (integer 94208)) + ) + (instance (rename led_OBUF_3__inst "led_OBUF[3]_inst") (viewref netlist (cellref OBUFT (libraryref hdi_primitives))) + (property XLNX_LINE_FILE (integer 94208)) + ) + (instance mid (viewref midpoint (cellref midpoint (libraryref work))) + (property XLNX_LINE_FILE (integer 159744)) + ) + (instance (rename sw_IBUF_0__inst "sw_IBUF[0]_inst") (viewref netlist (cellref IBUF (libraryref hdi_primitives))) + (property XLNX_LINE_FILE (integer 94208)) + ) + (instance (rename sw_IBUF_1__inst "sw_IBUF[1]_inst") (viewref netlist (cellref IBUF (libraryref hdi_primitives))) + (property XLNX_LINE_FILE (integer 94208)) + ) + (net (rename &_const0_ "[]") (joined + (portref G (instanceref GND)) + (portref I (instanceref led_OBUF_1__inst)) + (portref I (instanceref led_OBUF_2__inst)) + (portref I (instanceref led_OBUF_3__inst)) + ) + ) + (net (rename &_const1_ "[]") (joined + (portref P (instanceref VCC)) + (portref T (instanceref led_OBUF_1__inst)) + (portref T (instanceref led_OBUF_2__inst)) + (portref T (instanceref led_OBUF_3__inst)) + ) + ) + (net clk (joined + (portref I (instanceref clk_IBUF_inst)) + (portref clk) + ) + + (property IOSTANDARD (string "LVCMOS33")) + ) + (net clk_IBUF (joined + (portref I (instanceref clk_IBUF_BUFG_inst)) + (portref O (instanceref clk_IBUF_inst)) + ) + ) + (net clk_IBUF_BUFG (joined + (portref O (instanceref clk_IBUF_BUFG_inst)) + (portref clk_IBUF_BUFG (instanceref mid)) + ) + ) + (net lopt (joined + (portref I (instanceref je_OBUF_2__inst)) + (portref lopt (instanceref mid)) + ) + ) + (net lopt_1 (joined + (portref I (instanceref je_OBUF_3__inst)) + (portref lopt_1 (instanceref mid)) + ) + ) + (net lopt_2 (joined + (portref I (instanceref je_OBUF_5__inst)) + (portref lopt_2 (instanceref mid)) + ) + ) + (net lopt_3 (joined + (portref I (instanceref je_OBUF_6__inst)) + (portref lopt_3 (instanceref mid)) + ) + ) + (net lopt_4 (joined + (portref I (instanceref je_OBUF_7__inst)) + (portref lopt_4 (instanceref mid)) + ) + ) + (net lopt_5 (joined + (portref lopt_5 (instanceref mid)) + ) + ) + (net (rename btn "[0:0]btn") (joined) ) + (net (rename btn_0_ "btn[0]") (joined + (portref I (instanceref btn_IBUF_0__inst)) + (portref (member btn 3)) + ) + + (property IOSTANDARD (string "LVCMOS33")) + ) + (net (rename btn_IBUF "[0:0]btn_IBUF") (joined) ) + (net (rename btn_IBUF_0_ "btn_IBUF[0]") (joined + (portref O (instanceref btn_IBUF_0__inst)) + (portref button (instanceref mid)) + ) + ) + (net (rename je "[7:0]je") (joined) ) + (net (rename je_0_ "je[0]") (joined + (portref O (instanceref je_OBUF_0__inst)) + (portref (member je 7)) + ) + + (property IOSTANDARD (string "LVCMOS33")) + ) + (net (rename je_1_ "je[1]") (joined + (portref O (instanceref je_OBUF_1__inst)) + (portref (member je 6)) + ) + + (property IOSTANDARD (string "LVCMOS33")) + ) + (net (rename je_2_ "je[2]") (joined + (portref O (instanceref je_OBUF_2__inst)) + (portref (member je 5)) + ) + + (property IOSTANDARD (string "LVCMOS33")) + ) + (net (rename je_3_ "je[3]") (joined + (portref O (instanceref je_OBUF_3__inst)) + (portref (member je 4)) + ) + + (property IOSTANDARD (string "LVCMOS33")) + ) + (net (rename je_4_ "je[4]") (joined + (portref O (instanceref je_OBUF_4__inst)) + (portref (member je 3)) + ) + + (property IOSTANDARD (string "LVCMOS33")) + ) + (net (rename je_5_ "je[5]") (joined + (portref O (instanceref je_OBUF_5__inst)) + (portref (member je 2)) + ) + + (property IOSTANDARD (string "LVCMOS33")) + ) + (net (rename je_6_ "je[6]") (joined + (portref O (instanceref je_OBUF_6__inst)) + (portref (member je 1)) + ) + + (property IOSTANDARD (string "LVCMOS33")) + ) + (net (rename je_7_ "je[7]") (joined + (portref O (instanceref je_OBUF_7__inst)) + (portref (member je 0)) + ) + + (property IOSTANDARD (string "LVCMOS33")) + ) + (net (rename je_OBUF "[7:0]je_OBUF") (joined) ) + (net (rename je_OBUF_0_ "je_OBUF[0]") (joined + (portref I (instanceref je_OBUF_0__inst)) + (portref (member je_OBUF 7) (instanceref mid)) + ) + ) + (net (rename je_OBUF_1_ "je_OBUF[1]") (joined + (portref I (instanceref je_OBUF_1__inst)) + (portref (member je_OBUF 6) (instanceref mid)) + ) + ) + (net (rename je_OBUF_2_ "je_OBUF[2]") (joined + (portref (member je_OBUF 5) (instanceref mid)) + ) + ) + (net (rename je_OBUF_3_ "je_OBUF[3]") (joined + (portref (member je_OBUF 4) (instanceref mid)) + ) + ) + (net (rename je_OBUF_4_ "je_OBUF[4]") (joined + (portref I (instanceref je_OBUF_4__inst)) + (portref (member je_OBUF 3) (instanceref mid)) + ) + ) + (net (rename je_OBUF_5_ "je_OBUF[5]") (joined + (portref (member je_OBUF 2) (instanceref mid)) + ) + ) + (net (rename je_OBUF_6_ "je_OBUF[6]") (joined + (portref (member je_OBUF 1) (instanceref mid)) + ) + ) + (net (rename je_OBUF_7_ "je_OBUF[7]") (joined + (portref I (instanceref led_OBUF_0__inst)) + (portref (member je_OBUF 0) (instanceref mid)) + ) + ) + (net (rename led "[3:0]led") (joined) ) + (net (rename led_0_ "led[0]") (joined + (portref O (instanceref led_OBUF_0__inst)) + (portref (member led 3)) + ) + + (property IOSTANDARD (string "LVCMOS33")) + ) + (net (rename led_1_ "led[1]") (joined + (portref O (instanceref led_OBUF_1__inst)) + (portref (member led 2)) + ) + + (property IOSTANDARD (string "LVCMOS33")) + ) + (net (rename led_2_ "led[2]") (joined + (portref O (instanceref led_OBUF_2__inst)) + (portref (member led 1)) + ) + + (property IOSTANDARD (string "LVCMOS33")) + ) + (net (rename led_3_ "led[3]") (joined + (portref O (instanceref led_OBUF_3__inst)) + (portref (member led 0)) + ) + + (property IOSTANDARD (string "LVCMOS33")) + ) + (net (rename sw "[1:0]sw") (joined) ) + (net (rename sw_0_ "sw[0]") (joined + (portref I (instanceref sw_IBUF_0__inst)) + (portref (member sw 3)) + ) + + (property IOSTANDARD (string "LVCMOS33")) + ) + (net (rename sw_1_ "sw[1]") (joined + (portref I (instanceref sw_IBUF_1__inst)) + (portref (member sw 2)) + ) + + (property IOSTANDARD (string "LVCMOS33")) + ) + (net (rename sw_IBUF "[1:0]sw_IBUF") (joined) ) + (net (rename sw_IBUF_0_ "sw_IBUF[0]") (joined + (portref O (instanceref sw_IBUF_0__inst)) + (portref (member sw_IBUF 1) (instanceref mid)) + ) + ) + (net (rename sw_IBUF_1_ "sw_IBUF[1]") (joined + (portref O (instanceref sw_IBUF_1__inst)) + (portref (member sw_IBUF 0) (instanceref mid)) + ) + ) + ) + + (property ECO_CHECKSUM (string "43cdce77")) + (property XLNX_LINE_FILE (integer 94208)) + ) + ) + ) +(comment "Reference To The Cell Of Highest Level") + + (design lab2_wrapper + (cellref lab2_wrapper (libraryref work)) + (property MLO_VERSION_NUMBER (string "2017.2_7")) + (property XLNX_PROJ_DIR (string "/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart")) + (property (rename PHYSOPT_VERSION "PHYSOPT.VERSION") (string "2017.2_7")) + (property (rename PHYSOPT_ROUTE_DESIGN_CALLED "PHYSOPT.ROUTE_DESIGN_CALLED") (integer 1)) + (property part (string "xc7z010clg400-1")) + ) +) diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper.incr b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper.incr new file mode 100644 index 0000000..c1760b9 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper.incr @@ -0,0 +1 @@ +Timing_Data_For_IncrementalFlowver1.422 serialization::archive 14 0 4 0 3 0 0 0 0 0 0 0 0 0 0 3 0 0 0 1 0 0 0 0 26 PRODUCTION 1.11 2014-09-11 0 0 0 0 0 3 0 0 0 13 OriginalSlack 3.402823466e+38 17 OriginalHoldSlack 0.000000000e+00 5 stage 1.000000000e+00 3 0 15 InitTotalExpand 1.185709983e-01 11 TotalExpand 1.222980022e-01 20 DefaultRouterRuntime 0.000000000e+00 0 0 1 0 20 DefaultPlacerRuntime 1.429999948e+00 0 0 diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper.rda b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper.rda new file mode 100644 index 0000000..63cf3ff --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper.rda @@ -0,0 +1 @@ +Data_For_RDAFlowver1.922 serialization::archive 14 0 0 4 2 0 2 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 0 1 0 1 1 2 10 -bufg_opt 0 0 0 1 0 1 0 1 1 4 0 0 43 340282346638528859811704183484516925440.000 0 1 0 1 0 1 1 0 0 1 6 4 0.99 4 0.00 1 3 4 0.90 4 1.66 1 3 4 0.90 1 0 4 0.14 1 2 0 0 5 0 0 0 0 42 340282346638528859811704183484516925440.00 4 0.00 1 0 1 0 1 0 2 42 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a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper.xdc b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper.xdc new file mode 100644 index 0000000..aecfbf0 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper.xdc @@ -0,0 +1,295 @@ +set_property SRC_FILE_INFO {cfile:/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc rfile:../../project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc id:1 rxprname:$PSRCDIR/constrs_1/imports/Desktop/ZYBO_Master.xdc} [current_design] +set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design] +## This file is a general .xdc for the ZYBO Rev B board +set_property src_info {type:XDC file:1 line:2 export:INPUT save:INPUT read:READ} [current_design] +## To use it in a project: +set_property src_info {type:XDC file:1 line:3 export:INPUT save:INPUT read:READ} [current_design] +## - uncomment the lines corresponding to used pins +set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design] +## - rename the used signals according to the project +set_property src_info {type:XDC file:1 line:5 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:6 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design] +##Clock signal +set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports clk] +set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design] +#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }]; +set_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design] +##Switches +set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports {sw[0]}] +set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {sw[1]}] +set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS33} [get_ports {sw[2]}] +set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports {sw[3]}] +set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:18 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design] +##Buttons +set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {btn[0]}] +set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports {btn[1]}] +set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports {btn[2]}] +set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports {btn[3]}] +set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design] +##LEDs +set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports {led[0]}] +set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports {led[1]}] +set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {led[2]}] +set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {led[3]}] +set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design] +##I2S Audio Codec +set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports ac_bclk]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK +set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports ac_mclk]; #IO_25_34 Sch=AC_MCLK +set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports ac_muten]; #IO_L23N_T3_34 Sch=AC_MUTEN +set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports ac_pbdat]; #IO_L8P_T1_AD10P_35 Sch=AC_PBDAT +set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports ac_pblrc]; #IO_L11N_T1_SRCC_35 Sch=AC_PBLRC +set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports ac_recdat]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT +set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports ac_reclrc]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC +set_property src_info {type:XDC file:1 line:41 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design] +##Audio Codec/external EEPROM IIC bus +set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports ac_scl]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL +set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports ac_sda]; #IO_L23P_T3_34 Sch=AC_SDA +set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design] +##Additional Ethernet signals +set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports eth_int_b]; #IO_L6P_T0_35 Sch=ETH_INT_B +set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports eth_rst_b]; #IO_L3P_T0_DQS_AD1P_35 Sch=ETH_RST_B +set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:53 export:INPUT save:INPUT read:READ} [current_design] +##HDMI Signals +set_property src_info {type:XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_n]; #IO_L13N_T2_MRCC_35 Sch=HDMI_CLK_N +set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_p]; #IO_L13P_T2_MRCC_35 Sch=HDMI_CLK_P +set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[0] }]; #IO_L4N_T0_35 Sch=HDMI_D0_N +set_property src_info {type:XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[0] }]; #IO_L4P_T0_35 Sch=HDMI_D0_P +set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=HDMI_D1_N +set_property src_info {type:XDC file:1 line:59 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=HDMI_D1_P +set_property src_info {type:XDC file:1 line:60 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=HDMI_D2_N +set_property src_info {type:XDC file:1 line:61 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=HDMI_D2_P +set_property src_info {type:XDC file:1 line:62 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports hdmi_cec]; #IO_L5N_T0_AD9N_35 Sch=HDMI_CEC +set_property src_info {type:XDC file:1 line:63 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports hdmi_hpd]; #IO_L5P_T0_AD9P_35 Sch=HDMI_HPD +set_property src_info {type:XDC file:1 line:64 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports hdmi_out_en]; #IO_L6N_T0_VREF_35 Sch=HDMI_OUT_EN +set_property src_info {type:XDC file:1 line:65 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports hdmi_scl]; #IO_L16P_T2_35 Sch=HDMI_SCL +set_property src_info {type:XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports hdmi_sda]; #IO_L16N_T2_35 Sch=HDMI_SDA +set_property src_info {type:XDC file:1 line:67 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:68 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:69 export:INPUT save:INPUT read:READ} [current_design] +##Pmod Header JA (XADC) +set_property src_info {type:XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja_p[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p +set_property src_info {type:XDC file:1 line:71 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P +set_property src_info {type:XDC file:1 line:72 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P +set_property src_info {type:XDC file:1 line:73 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P +set_property src_info {type:XDC file:1 line:74 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[0] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N +set_property src_info {type:XDC file:1 line:75 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N +set_property src_info {type:XDC file:1 line:76 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N +set_property src_info {type:XDC file:1 line:77 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N +set_property src_info {type:XDC file:1 line:78 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:79 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:80 export:INPUT save:INPUT read:READ} [current_design] +##Pmod Header JB +set_property src_info {type:XDC file:1 line:81 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[0] }]; #IO_L15P_T2_DQS_34 Sch=JB1_p +set_property src_info {type:XDC file:1 line:82 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[0] }]; #IO_L15N_T2_DQS_34 Sch=JB1_N +set_property src_info {type:XDC file:1 line:83 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L16P_T2_34 Sch=JB2_P +set_property src_info {type:XDC file:1 line:84 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L16N_T2_34 Sch=JB2_N +set_property src_info {type:XDC file:1 line:85 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L17P_T2_34 Sch=JB3_P +set_property src_info {type:XDC file:1 line:86 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L17N_T2_34 Sch=JB3_N +set_property src_info {type:XDC file:1 line:87 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L22P_T3_34 Sch=JB4_P +set_property src_info {type:XDC file:1 line:88 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L22N_T3_34 Sch=JB4_N +set_property src_info {type:XDC file:1 line:89 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:90 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:91 export:INPUT save:INPUT read:READ} [current_design] +##Pmod Header JC +set_property src_info {type:XDC file:1 line:92 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc_p[0] }]; #IO_L10P_T1_34 Sch=JC1_P +set_property src_info {type:XDC file:1 line:93 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc_n[0] }]; #IO_L10N_T1_34 Sch=JC1_N +set_property src_info {type:XDC file:1 line:94 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc_p[1] }]; #IO_L1P_T0_34 Sch=JC2_P +set_property src_info {type:XDC file:1 line:95 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc_n[1] }]; #IO_L1N_T0_34 Sch=JC2_N +set_property src_info {type:XDC file:1 line:96 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc_p[2] }]; #IO_L8P_T1_34 Sch=JC3_P +set_property src_info {type:XDC file:1 line:97 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc_n[2] }]; #IO_L8N_T1_34 Sch=JC3_N +set_property src_info {type:XDC file:1 line:98 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc_p[3] }]; #IO_L2P_T0_34 Sch=JC4_P +set_property src_info {type:XDC file:1 line:99 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc_n[3] }]; #IO_L2N_T0_34 Sch=JC4_N +set_property src_info {type:XDC file:1 line:100 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:101 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:102 export:INPUT save:INPUT read:READ} [current_design] +##Pmod Header JD +set_property src_info {type:XDC file:1 line:103 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[0] }]; #IO_L5P_T0_34 Sch=JD1_P +set_property src_info {type:XDC file:1 line:104 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[0] }]; #IO_L5N_T0_34 Sch=JD1_N +set_property src_info {type:XDC file:1 line:105 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[1] }]; #IO_L6P_T0_34 Sch=JD2_P +set_property src_info {type:XDC file:1 line:106 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd_n[1] }]; #IO_L6N_T0_VREF_34 Sch=JD2_N +set_property src_info {type:XDC file:1 line:107 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[2] }]; #IO_L11P_T1_SRCC_34 Sch=JD3_P +set_property src_info {type:XDC file:1 line:108 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[2] }]; #IO_L11N_T1_SRCC_34 Sch=JD3_N +set_property src_info {type:XDC file:1 line:109 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd_p[3] }]; #IO_L21P_T3_DQS_34 Sch=JD4_P +set_property src_info {type:XDC file:1 line:110 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd_n[3] }]; #IO_L21N_T3_DQS_34 Sch=JD4_N +set_property src_info {type:XDC file:1 line:111 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:112 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:113 export:INPUT save:INPUT read:READ} [current_design] +##Pmod Header JE +set_property src_info {type:XDC file:1 line:114 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {je[0]}] +set_property src_info {type:XDC file:1 line:115 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS33} [get_ports {je[1]}] +set_property src_info {type:XDC file:1 line:116 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {je[2]}] +set_property src_info {type:XDC file:1 line:117 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {je[3]}] +set_property src_info {type:XDC file:1 line:118 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports {je[4]}] +set_property src_info {type:XDC file:1 line:119 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {je[5]}] +set_property src_info {type:XDC file:1 line:120 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS33} [get_ports {je[6]}] +set_property src_info {type:XDC file:1 line:121 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports {je[7]}] +set_property src_info {type:XDC file:1 line:122 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:123 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:124 export:INPUT save:INPUT read:READ} [current_design] +##USB-OTG overcurrent detect pin +set_property src_info {type:XDC file:1 line:125 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports otg_oc]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=OTG_OC +set_property src_info {type:XDC file:1 line:126 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:127 export:INPUT save:INPUT read:READ} [current_design] + +set_property src_info {type:XDC file:1 line:128 export:INPUT save:INPUT read:READ} [current_design] +##VGA Connector +set_property src_info {type:XDC file:1 line:129 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L7P_T1_AD2P_35 Sch=VGA_R1 +set_property src_info {type:XDC file:1 line:130 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=VGA_R2 +set_property src_info {type:XDC file:1 line:131 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L17P_T2_AD5P_35 Sch=VGA_R3 +set_property src_info {type:XDC file:1 line:132 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L18N_T2_AD13N_35 Sch=VGA_R4 +set_property src_info {type:XDC file:1 line:133 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_AD12P_35 Sch=VGA_R5 +set_property src_info {type:XDC file:1 line:134 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=VGA_G0 +set_property src_info {type:XDC file:1 line:135 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L14P_T2_SRCC_34 Sch=VGA_G1 +set_property src_info {type:XDC file:1 line:136 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=VGA_G2 +set_property src_info {type:XDC file:1 line:137 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L10N_T1_AD11N_35 Sch=VGA_G3 +set_property src_info {type:XDC file:1 line:138 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L17N_T2_AD5N_35 Sch=VGA_G4 +set_property src_info {type:XDC file:1 line:139 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L15N_T2_DQS_AD12N_35 Sch=VGA=G5 +set_property src_info {type:XDC file:1 line:140 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L14N_T2_SRCC_34 Sch=VGA_B1 +set_property src_info {type:XDC file:1 line:141 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L7N_T1_AD2N_35 Sch=VGA_B2 +set_property src_info {type:XDC file:1 line:142 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L10P_T1_AD11P_35 Sch=VGA_B3 +set_property src_info {type:XDC file:1 line:143 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=VGA_B4 +set_property src_info {type:XDC file:1 line:144 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L18P_T2_AD13P_35 Sch=VGA_B5 +set_property src_info {type:XDC file:1 line:145 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports vga_hs]; #IO_L13N_T2_MRCC_34 Sch=VGA_HS +set_property src_info {type:XDC file:1 line:146 export:INPUT save:INPUT read:READ} [current_design] +#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports vga_vs]; #IO_0_34 Sch=VGA_VS +set_property src_info {type:XDC file:1 line:147 export:INPUT save:INPUT read:READ} [current_design] + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper.xdef b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper.xdef new file mode 100644 index 0000000..8949fb3 Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper.xdef differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper.xn b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper.xn new file mode 100644 index 0000000..a0b81f0 Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper.xn differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper_iPhysOpt.tcl b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper_iPhysOpt.tcl new file mode 100644 index 0000000..e69de29 diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper_stub.v b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper_stub.v new file mode 100644 index 0000000..75b0147 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper_stub.v @@ -0,0 +1,11 @@ +// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module lab2_wrapper(clk, sw, btn, led, je); + input clk; + input [3:0]sw; + input [3:0]btn; + output [3:0]led; + output [7:0]je; +endmodule diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper_stub.vhdl b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper_stub.vhdl new file mode 100644 index 0000000..476c347 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14511-comparch-VirtualBox/dcp3/lab2_wrapper_stub.vhdl @@ -0,0 +1,21 @@ +-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity lab2_wrapper is + Port ( + clk : in STD_LOGIC; + sw : in STD_LOGIC_VECTOR ( 3 downto 0 ); + btn : in STD_LOGIC_VECTOR ( 3 downto 0 ); + led : out STD_LOGIC_VECTOR ( 3 downto 0 ); + je : out STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + +end lab2_wrapper; + +architecture stub of lab2_wrapper is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +begin +end; diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.init_design.begin.rst b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.init_design.begin.rst new file mode 100644 index 0000000..84bc4d3 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.init_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.init_design.end.rst b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.init_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.opt_design.begin.rst b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.opt_design.begin.rst new file mode 100644 index 0000000..84bc4d3 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.opt_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.opt_design.end.rst b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.opt_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.place_design.begin.rst b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.place_design.begin.rst new file mode 100644 index 0000000..84bc4d3 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.place_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.place_design.end.rst b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.place_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.route_design.begin.rst b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.route_design.begin.rst new file mode 100644 index 0000000..84bc4d3 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.route_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.route_design.end.rst b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.route_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.vivado.begin.rst b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.vivado.begin.rst new file mode 100644 index 0000000..6682d48 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.vivado.end.rst b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.write_bitstream.begin.rst b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.write_bitstream.begin.rst new file mode 100644 index 0000000..43a522c --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.write_bitstream.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.write_bitstream.end.rst b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/.write_bitstream.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/ISEWrap.js b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/ISEWrap.js new file mode 100755 index 0000000..8284d2d --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/ISEWrap.js @@ -0,0 +1,244 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/ISEWrap.sh b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/ISEWrap.sh new file mode 100755 index 0000000..e1a8f5d --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/gen_run.xml b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..e138c13 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/gen_run.xml @@ -0,0 +1,135 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/htr.txt b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/htr.txt new file mode 100644 index 0000000..5cc1a54 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# + +vivado -log lab2_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/init_design.pb b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/init_design.pb new file mode 100644 index 0000000..2359f81 Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/init_design.pb differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper.bit b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper.bit new file mode 100644 index 0000000..045170c Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper.bit differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper.tcl b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper.tcl new file mode 100644 index 0000000..307b09c --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper.tcl @@ -0,0 +1,67 @@ +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + +set_msg_config -id {Common 17-41} -limit 10000000 + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + set_param xicom.use_bs_reader 1 + open_checkpoint lab2_wrapper_routed.dcp + set_property webtalk.parent_dir /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.cache/wt [current_project] + catch { write_mem_info -force lab2_wrapper.mmi } + write_bitstream -force lab2_wrapper.bit + catch {write_debug_probes -no_partial_ltxfile -quiet -force debug_nets} + catch {file copy -force debug_nets.ltx lab2_wrapper.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper.vdi b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper.vdi new file mode 100644 index 0000000..6717654 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper.vdi @@ -0,0 +1,444 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:40:50 2017 +# Process ID: 14391 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1 +# Command line: vivado -log lab2_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1307.199 ; gain = 222.145 ; free physical = 70 ; free virtual = 1346 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.33 . Memory (MB): peak = 1316.203 ; gain = 9.004 ; free physical = 67 ; free virtual = 1344 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1713a94cd + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 92 ; free virtual = 989 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1713a94cd + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 91 ; free virtual = 989 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: cad9f257 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 88 ; free virtual = 989 +INFO: [Opt 31-389] Phase Sweep created 5 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: cad9f257 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 87 ; free virtual = 989 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: cad9f257 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 87 ; free virtual = 989 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 87 ; free virtual = 989 +Ending Logic Optimization Task | Checksum: cad9f257 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 87 ; free virtual = 989 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1b281726d + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 84 ; free virtual = 989 +20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:16 . Memory (MB): peak = 1772.695 ; gain = 465.496 ; free physical = 83 ; free virtual = 989 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 75 ; free virtual = 989 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper_opt.dcp' has been generated. +Command: report_drc -file lab2_wrapper_drc_opted.rpt +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper_drc_opted.rpt. +report_drc completed successfully +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 980 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 16eb3a3f6 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 980 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 980 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f9eb0a13 + +Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.92 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 66 ; free virtual = 980 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1a55c9a0e + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.98 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 63 ; free virtual = 980 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1a55c9a0e + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 979 +Phase 1 Placer Initialization | Checksum: 1a55c9a0e + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 979 + +Phase 2 Global Placement +WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 131b360c7 + +Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 978 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 131b360c7 + +Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 978 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1ef7f9f6e + +Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 978 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 154ee63e4 + +Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 978 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 154ee63e4 + +Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 978 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 +Phase 3 Detail Placement | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: f40da953 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: f40da953 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 +Ending Placer Task | Checksum: 902b657c + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 978 +31 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 980 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 81 ; free virtual = 971 +report_utilization: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 87 ; free virtual = 979 +report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 85 ; free virtual = 977 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +Checksum: PlaceDB: 3337b348 ConstDB: 0 ShapeSum: 5cf3b234 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 16ed4557e + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1820.699 ; gain = 40.000 ; free physical = 91 ; free virtual = 902 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 16ed4557e + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1824.699 ; gain = 44.000 ; free physical = 81 ; free virtual = 899 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 16ed4557e + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1824.699 ; gain = 44.000 ; free physical = 81 ; free virtual = 899 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: c9ab31ea + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 892 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 5e036487 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 74 ; free virtual = 894 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 893 +Phase 4 Rip-up And Reroute | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 893 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 894 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 894 +Phase 6 Post Hold Fix | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 894 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0343468 % + Global Horizontal Routing Utilization = 0.00804228 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 17.1171%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. +Phase 7 Route finalize | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 894 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1834.699 ; gain = 54.000 ; free physical = 73 ; free virtual = 893 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 86e4b1c5 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1834.699 ; gain = 54.000 ; free physical = 72 ; free virtual = 893 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1834.699 ; gain = 54.000 ; free physical = 70 ; free virtual = 895 + +Routing Is Done. +37 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1868.590 ; gain = 87.891 ; free physical = 64 ; free virtual = 895 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1868.590 ; gain = 0.000 ; free physical = 79 ; free virtual = 888 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper_routed.dcp' has been generated. +Command: report_drc -file lab2_wrapper_drc_routed.rpt -pb lab2_wrapper_drc_routed.pb -rpx lab2_wrapper_drc_routed.rpx +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file lab2_wrapper_methodology_drc_routed.rpt -rpx lab2_wrapper_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file lab2_wrapper_power_routed.rpt -pb lab2_wrapper_power_summary_routed.pb -rpx lab2_wrapper_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +42 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:42:09 2017... +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:42:20 2017 +# Process ID: 14511 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1 +# Command line: vivado -log lab2_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace +Command: open_checkpoint lab2_wrapper_routed.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1083.039 ; gain = 0.000 ; free physical = 485 ; free virtual = 1615 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:43:13 2017 +# Process ID: 14667 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1 +# Command line: vivado -log lab2_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace +Command: open_checkpoint lab2_wrapper_routed.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1083.047 ; gain = 0.000 ; free physical = 386 ; free virtual = 1598 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14667-comparch-VirtualBox/dcp3/lab2_wrapper.xdc] +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14667-comparch-VirtualBox/dcp3/lab2_wrapper.xdc] +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1304.207 ; gain = 0.000 ; free physical = 114 ; free virtual = 1343 +Restored from archive | CPU: 0.010000 secs | Memory: 0.063492 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1304.207 ; gain = 0.000 ; free physical = 114 ; free virtual = 1343 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2017.2 (64-bit) build 1909853 +open_checkpoint: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1304.207 ; gain = 221.160 ; free physical = 115 ; free virtual = 1342 +Command: write_bitstream -force lab2_wrapper.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command write_bitstream +Command: report_drc (run_mandatory_drcs) for: bitstream_checks +WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./lab2_wrapper.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-186] '/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Wed Oct 25 21:44:09 2017. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. +14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:23 . Memory (MB): peak = 1718.027 ; gain = 413.820 ; free physical = 362 ; free virtual = 1318 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:44:09 2017... diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_14391.backup.vdi b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_14391.backup.vdi new file mode 100644 index 0000000..bf233c4 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_14391.backup.vdi @@ -0,0 +1,385 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:40:50 2017 +# Process ID: 14391 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1 +# Command line: vivado -log lab2_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1307.199 ; gain = 222.145 ; free physical = 70 ; free virtual = 1346 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.33 . Memory (MB): peak = 1316.203 ; gain = 9.004 ; free physical = 67 ; free virtual = 1344 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1713a94cd + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 92 ; free virtual = 989 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1713a94cd + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 91 ; free virtual = 989 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: cad9f257 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 88 ; free virtual = 989 +INFO: [Opt 31-389] Phase Sweep created 5 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: cad9f257 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 87 ; free virtual = 989 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: cad9f257 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 87 ; free virtual = 989 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 87 ; free virtual = 989 +Ending Logic Optimization Task | Checksum: cad9f257 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 87 ; free virtual = 989 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1b281726d + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 84 ; free virtual = 989 +20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:16 . Memory (MB): peak = 1772.695 ; gain = 465.496 ; free physical = 83 ; free virtual = 989 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 75 ; free virtual = 989 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper_opt.dcp' has been generated. +Command: report_drc -file lab2_wrapper_drc_opted.rpt +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper_drc_opted.rpt. +report_drc completed successfully +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 980 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 16eb3a3f6 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 980 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 980 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f9eb0a13 + +Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.92 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 66 ; free virtual = 980 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1a55c9a0e + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.98 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 63 ; free virtual = 980 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1a55c9a0e + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 979 +Phase 1 Placer Initialization | Checksum: 1a55c9a0e + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 979 + +Phase 2 Global Placement +WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 131b360c7 + +Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 978 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 131b360c7 + +Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 978 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1ef7f9f6e + +Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 978 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 154ee63e4 + +Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 978 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 154ee63e4 + +Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 978 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 +Phase 3 Detail Placement | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: f40da953 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: f40da953 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 +Ending Placer Task | Checksum: 902b657c + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 978 +31 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 980 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 81 ; free virtual = 971 +report_utilization: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 87 ; free virtual = 979 +report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 85 ; free virtual = 977 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +Checksum: PlaceDB: 3337b348 ConstDB: 0 ShapeSum: 5cf3b234 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 16ed4557e + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1820.699 ; gain = 40.000 ; free physical = 91 ; free virtual = 902 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 16ed4557e + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1824.699 ; gain = 44.000 ; free physical = 81 ; free virtual = 899 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 16ed4557e + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1824.699 ; gain = 44.000 ; free physical = 81 ; free virtual = 899 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: c9ab31ea + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 892 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 5e036487 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 74 ; free virtual = 894 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 893 +Phase 4 Rip-up And Reroute | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 893 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 894 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 894 +Phase 6 Post Hold Fix | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 894 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0343468 % + Global Horizontal Routing Utilization = 0.00804228 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 17.1171%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. +Phase 7 Route finalize | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 894 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1834.699 ; gain = 54.000 ; free physical = 73 ; free virtual = 893 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 86e4b1c5 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1834.699 ; gain = 54.000 ; free physical = 72 ; free virtual = 893 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1834.699 ; gain = 54.000 ; free physical = 70 ; free virtual = 895 + +Routing Is Done. +37 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1868.590 ; gain = 87.891 ; free physical = 64 ; free virtual = 895 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1868.590 ; gain = 0.000 ; free physical = 79 ; free virtual = 888 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper_routed.dcp' has been generated. +Command: report_drc -file lab2_wrapper_drc_routed.rpt -pb lab2_wrapper_drc_routed.pb -rpx lab2_wrapper_drc_routed.rpx +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file lab2_wrapper_methodology_drc_routed.rpt -rpx lab2_wrapper_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file lab2_wrapper_power_routed.rpt -pb lab2_wrapper_power_summary_routed.pb -rpx lab2_wrapper_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +42 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:42:09 2017... +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:42:20 2017 +# Process ID: 14511 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1 +# Command line: vivado -log lab2_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace +Command: open_checkpoint lab2_wrapper_routed.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1083.039 ; gain = 0.000 ; free physical = 485 ; free virtual = 1615 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_clock_utilization_routed.rpt b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_clock_utilization_routed.rpt new file mode 100644 index 0000000..6ba6d0e --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_clock_utilization_routed.rpt @@ -0,0 +1,154 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:42:08 2017 +| Host : comparch-VirtualBox running 64-bit unknown +| Command : report_clock_utilization -file lab2_wrapper_clock_utilization_routed.rpt +| Design : lab2_wrapper +| Device : 7z010-clg400 +| Speed File : -1 PRODUCTION 1.11 2014-09-11 +------------------------------------------------------------------------------------------ + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X1Y0 +8. Clock Region Cell Placement per Global Clock: Region X1Y1 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 48 | 0 | 0 | 0 | +| BUFIO | 0 | 8 | 0 | 0 | 0 | +| BUFMR | 0 | 4 | 0 | 0 | 0 | +| BUFR | 0 | 8 | 0 | 0 | 0 | +| MMCM | 0 | 2 | 0 | 0 | 0 | +| PLL | 0 | 2 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 2 | 30 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| src0 | g0 | IBUF/O | IOB_X0Y78 | IOB_X0Y78 | X1Y1 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 29 | 1100 | 15 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 1 | 1100 | 1 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y1 | 0 | 1 | +| Y0 | 0 | 1 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| g0 | BUFG/O | n/a | | | | 30 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+-----+ +| | X0 | X1 | ++----+----+-----+ +| Y1 | 0 | 1 | +| Y0 | 0 | 29 | ++----+----+-----+ + + +7. Clock Region Cell Placement per Global Clock: Region X1Y0 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 29 | 0 | 29 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +8. Clock Region Cell Placement per Global Clock: Region X1Y1 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y16 [get_cells clk_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X0Y78 [get_ports clk] + +# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y16" +#startgroup +create_pblock {CLKAG_clk_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1} +#endgroup diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_control_sets_placed.rpt b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_control_sets_placed.rpt new file mode 100644 index 0000000..3097e50 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_control_sets_placed.rpt @@ -0,0 +1,63 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:41:44 2017 +| Host : comparch-VirtualBox running 64-bit Ubuntu 16.04.3 LTS +| Command : report_control_sets -verbose -file lab2_wrapper_control_sets_placed.rpt +| Design : lab2_wrapper +| Device : xc7z010 +----------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Flip-Flop Distribution +3. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 2 | +| Unused register locations in slices containing registers | 10 | ++----------------------------------------------------------+-------+ + + +2. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 20 | 9 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 10 | 4 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +3. Detailed Control Set Information +----------------------------------- + ++----------------+---------------------------------------+------------------------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++----------------+---------------------------------------+------------------------------------+------------------+----------------+ +| clk_IBUF_BUFG | mid/parallelLoadCond/shiftregistermem | mid/parallelLoadCond/negativeedge0 | 4 | 10 | +| clk_IBUF_BUFG | | | 9 | 20 | ++----------------+---------------------------------------+------------------------------------+------------------+----------------+ + + ++--------+-----------------------+ +| Fanout | Number of ControlSets | ++--------+-----------------------+ +| 10 | 1 | +| 16+ | 1 | ++--------+-----------------------+ + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_drc_opted.rpt b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_drc_opted.rpt new file mode 100644 index 0000000..795612f --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_drc_opted.rpt @@ -0,0 +1,41 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:41:41 2017 +| Host : comparch-VirtualBox running 64-bit Ubuntu 16.04.3 LTS +| Command : report_drc -file lab2_wrapper_drc_opted.rpt +| Design : lab2_wrapper +| Device : xc7z010clg400-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++--------+----------+--------------------+------------+ +| Rule | Severity | Description | Violations | ++--------+----------+--------------------+------------+ +| ZPS7-1 | Warning | PS7 block required | 1 | ++--------+----------+--------------------+------------+ + +2. REPORT DETAILS +----------------- +ZPS7-1#1 Warning +PS7 block required +The PS7 cell must be used in this Zynq design in order to enable correct default configuration. +Related violations: + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_drc_routed.pb b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_drc_routed.pb new file mode 100644 index 0000000..70698d1 Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_drc_routed.pb differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_drc_routed.rpt b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_drc_routed.rpt new file mode 100644 index 0000000..44a5a18 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_drc_routed.rpt @@ -0,0 +1,41 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:42:05 2017 +| Host : comparch-VirtualBox running 64-bit unknown +| Command : report_drc -file lab2_wrapper_drc_routed.rpt -pb lab2_wrapper_drc_routed.pb -rpx lab2_wrapper_drc_routed.rpx +| Design : lab2_wrapper +| Device : xc7z010clg400-1 +| Speed File : -1 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 1 ++--------+----------+--------------------+------------+ +| Rule | Severity | Description | Violations | ++--------+----------+--------------------+------------+ +| ZPS7-1 | Warning | PS7 block required | 1 | ++--------+----------+--------------------+------------+ + +2. REPORT DETAILS +----------------- +ZPS7-1#1 Warning +PS7 block required +The PS7 cell must be used in this Zynq design in order to enable correct default configuration. +Related violations: + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_drc_routed.rpx b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_drc_routed.rpx new file mode 100644 index 0000000..9c15c7c Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_drc_routed.rpx differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_io_placed.rpt b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_io_placed.rpt new file mode 100644 index 0000000..6c091b9 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_io_placed.rpt @@ -0,0 +1,442 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:41:43 2017 +| Host : comparch-VirtualBox running 64-bit Ubuntu 16.04.3 LTS +| Command : report_io -file lab2_wrapper_io_placed.rpt +| Design : lab2_wrapper +| Device : xc7z010 +| Speed File : -1 +| Package : clg400 +| Package Version : FINAL 2012-10-23 +| Package Pin Delay Version : VERS. 2.0 2012-10-23 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 21 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | ++------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+ +| A1 | | | PS_DDR_DM0_502 | PSS IO | | | | | | | | | | | | | +| A2 | | | PS_DDR_DQ2_502 | PSS IO | | | | | | | | | | | | | +| A3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| A4 | | | PS_DDR_DQ3_502 | PSS IO | | | | | | | | | | | | | +| A5 | | | PS_MIO6_500 | PSS IO | | | | | | | | | | | | | +| A6 | | | PS_MIO5_500 | PSS IO | | | | | | | | | | | | | +| A7 | | | PS_MIO1_500 | PSS IO | | | | | | | | | | | | | +| A8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| A9 | | | PS_MIO43_501 | PSS IO | | | | | | | | | | | | | +| A10 | | | PS_MIO37_501 | PSS IO | | | | | | | | | | | | | +| A11 | | | PS_MIO36_501 | PSS IO | | | | | | | | | | | | | +| A12 | | | PS_MIO34_501 | PSS IO | | | | | | | | | | | | | +| A13 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| A14 | | | PS_MIO32_501 | PSS IO | | | | | | | | | | | | | +| A15 | | | PS_MIO26_501 | PSS IO | | | | | | | | | | | | | +| A16 | | | PS_MIO24_501 | PSS IO | | | | | | | | | | | | | +| A17 | | | PS_MIO20_501 | PSS IO | | | | | | | | | | | | | +| A18 | | | GND | GND | | | | | | | 0.0 | | | | | | +| A19 | | | PS_MIO16_501 | PSS IO | | | | | | | | | | | | | +| A20 | | High Range | IO_L2N_T0_AD8N_35 | User IO | | 35 | | | | | | | | | | | +| B1 | | | GND | GND | | | | | | | 0.0 | | | | | | +| B2 | | | PS_DDR_DQS_N0_502 | PSS IO | | | | | | | | | | | | | +| B3 | | | PS_DDR_DQ1_502 | PSS IO | | | | | | | | | | | | | +| B4 | | | PS_DDR_DRST_B_502 | PSS IO | | | | | | | | | | | | | +| B5 | | | PS_MIO9_500 | PSS IO | | | | | | | | | | | | | +| B6 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | +| B7 | | | PS_MIO4_500 | PSS IO | | | | | | | | | | | | | +| B8 | | | PS_MIO2_500 | PSS IO | | | | | | | | | | | | | +| B9 | | | PS_MIO51_501 | PSS IO | | | | | | | | | | | | | +| B10 | | | PS_SRST_B_501 | PSS IO | | | | | | | | | | | | | +| B11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| B12 | | | PS_MIO48_501 | PSS IO | | | | | | | | | | | | | +| B13 | | | PS_MIO50_501 | PSS IO | | | | | | | | | | | | | +| B14 | | | PS_MIO47_501 | PSS IO | | | | | | | | | | | | | +| B15 | | | PS_MIO45_501 | PSS IO | | | | | | | | | | | | | +| B16 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| B17 | | | PS_MIO22_501 | PSS IO | | | | | | | | | | | | | +| B18 | | | PS_MIO18_501 | PSS IO | | | | | | | | | | | | | +| B19 | | High Range | IO_L2P_T0_AD8P_35 | User IO | | 35 | | | | | | | | | | | +| B20 | | High Range | IO_L1N_T0_AD0N_35 | User IO | | 35 | | | | | | | | | | | +| C1 | | | PS_DDR_DQ6_502 | PSS IO | | | | | | | | | | | | | +| C2 | | | PS_DDR_DQS_P0_502 | PSS IO | | | | | | | | | | | | | +| C3 | | | PS_DDR_DQ0_502 | PSS IO | | | | | | | | | | | | | +| C4 | | | GND | GND | | | | | | | 0.0 | | | | | | +| C5 | | | PS_MIO14_500 | PSS IO | | | | | | | | | | | | | +| C6 | | | PS_MIO11_500 | PSS IO | | | | | | | | | | | | | +| C7 | | | PS_POR_B_500 | PSS IO | | | | | | | | | | | | | +| C8 | | | PS_MIO15_500 | PSS IO | | | | | | | | | | | | | +| C9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| C10 | | | PS_MIO52_501 | PSS IO | | | | | | | | | | | | | +| C11 | | | PS_MIO53_501 | PSS IO | | | | | | | | | | | | | +| C12 | | | PS_MIO49_501 | PSS IO | | | | | | | | | | | | | +| C13 | | | PS_MIO29_501 | PSS IO | | | | | | | | | | | | | +| C14 | | | GND | GND | | | | | | | 0.0 | | | | | | +| C15 | | | PS_MIO30_501 | PSS IO | | | | | | | | | | | | | +| C16 | | | PS_MIO28_501 | PSS IO | | | | | | | | | | | | | +| C17 | | | PS_MIO41_501 | PSS IO | | | | | | | | | | | | | +| C18 | | | PS_MIO39_501 | PSS IO | | | | | | | | | | | | | +| C19 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| C20 | | High Range | IO_L1P_T0_AD0P_35 | User IO | | 35 | | | | | | | | | | | +| D1 | | | PS_DDR_DQ5_502 | PSS IO | | | | | | | | | | | | | +| D2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| D3 | | | PS_DDR_DQ4_502 | PSS IO | | | | | | | | | | | | | +| D4 | | | PS_DDR_A13_502 | PSS IO | | | | | | | | | | | | | +| D5 | | | PS_MIO8_500 | PSS IO | | | | | | | | | | | | | +| D6 | | | PS_MIO3_500 | PSS IO | | | | | | | | | | | | | +| D7 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | +| D8 | | | PS_MIO7_500 | PSS IO | | | | | | | | | | | | | +| D9 | | | PS_MIO12_500 | PSS IO | | | | | | | | | | | | | +| D10 | | | PS_MIO19_501 | PSS IO | | | | | | | | | | | | | +| D11 | | | PS_MIO23_501 | PSS IO | | | | | | | | | | | | | +| D12 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| D13 | | | PS_MIO27_501 | PSS IO | | | | | | | | | | | | | +| D14 | | | PS_MIO40_501 | PSS IO | | | | | | | | | | | | | +| D15 | | | PS_MIO33_501 | PSS IO | | | | | | | | | | | | | +| D16 | | | PS_MIO46_501 | PSS IO | | | | | | | | | | | | | +| D17 | | | GND | GND | | | | | | | 0.0 | | | | | | +| D18 | led[3] | High Range | IO_L3N_T0_DQS_AD1N_35 | TRISTATE | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| D19 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | +| D20 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | +| E1 | | | PS_DDR_DQ7_502 | PSS IO | | | | | | | | | | | | | +| E2 | | | PS_DDR_DQ8_502 | PSS IO | | | | | | | | | | | | | +| E3 | | | PS_DDR_DQ9_502 | PSS IO | | | | | | | | | | | | | +| E4 | | | PS_DDR_A12_502 | PSS IO | | | | | | | | | | | | | +| E5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| E6 | | | PS_MIO0_500 | PSS IO | | | | | | | | | | | | | +| E7 | | | PS_CLK_500 | PSS Clock | | | | | | | | | | | | | +| E8 | | | PS_MIO13_500 | PSS IO | | | | | | | | | | | | | +| E9 | | | PS_MIO10_500 | PSS IO | | | | | | | | | | | | | +| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| E11 | | | PS_MIO_VREF_501 | PSS IO | | | | | | | | | | | | | +| E12 | | | PS_MIO42_501 | PSS IO | | | | | | | | | | | | | +| E13 | | | PS_MIO38_501 | PSS IO | | | | | | | | | | | | | +| E14 | | | PS_MIO17_501 | PSS IO | | | | | | | | | | | | | +| E15 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| E16 | | | PS_MIO31_501 | PSS IO | | | | | | | | | | | | | +| E17 | | High Range | IO_L3P_T0_DQS_AD1P_35 | User IO | | 35 | | | | | | | | | | | +| E18 | | High Range | IO_L5P_T0_AD9P_35 | User IO | | 35 | | | | | | | | | | | +| E19 | | High Range | IO_L5N_T0_AD9N_35 | User IO | | 35 | | | | | | | | | | | +| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | +| F1 | | | PS_DDR_DM1_502 | PSS IO | | | | | | | | | | | | | +| F2 | | | PS_DDR_DQS_N1_502 | PSS IO | | | | | | | | | | | | | +| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | +| F4 | | | PS_DDR_A14_502 | PSS IO | | | | | | | | | | | | | +| F5 | | | PS_DDR_A10_502 | PSS IO | | | | | | | | | | | | | +| F6 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| F8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| F9 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | +| F10 | | | RSVDGND | GND | | | | | | | | | | | | | +| F11 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | +| F12 | | | PS_MIO35_501 | PSS IO | | | | | | | | | | | | | +| F13 | | | PS_MIO44_501 | PSS IO | | | | | | | | | | | | | +| F14 | | | PS_MIO21_501 | PSS IO | | | | | | | | | | | | | +| F15 | | | PS_MIO25_501 | PSS IO | | | | | | | | | | | | | +| F16 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | +| F17 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | +| F18 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| F19 | | High Range | IO_L15P_T2_DQS_AD12P_35 | User IO | | 35 | | | | | | | | | | | +| F20 | | High Range | IO_L15N_T2_DQS_AD12N_35 | User IO | | 35 | | | | | | | | | | | +| G1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| G2 | | | PS_DDR_DQS_P1_502 | PSS IO | | | | | | | | | | | | | +| G3 | | | PS_DDR_DQ10_502 | PSS IO | | | | | | | | | | | | | +| G4 | | | PS_DDR_A11_502 | PSS IO | | | | | | | | | | | | | +| G5 | | | PS_DDR_VRN_502 | PSS IO | | | | | | | | | | | | | +| G6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | +| G7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| G8 | | | VCCPLL | PSS VCCPLL | | | | | | | | | | | | | +| G9 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| G14 | led[2] | High Range | IO_0_35 | TRISTATE | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| G15 | sw[0] | High Range | IO_L19N_T3_VREF_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | +| G16 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G17 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | +| G18 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | +| G19 | | High Range | IO_L18P_T2_AD13P_35 | User IO | | 35 | | | | | | | | | | | +| G20 | | High Range | IO_L18N_T2_AD13N_35 | User IO | | 35 | | | | | | | | | | | +| H1 | | | PS_DDR_DQ14_502 | PSS IO | | | | | | | | | | | | | +| H2 | | | PS_DDR_DQ13_502 | PSS IO | | | | | | | | | | | | | +| H3 | | | PS_DDR_DQ11_502 | PSS IO | | | | | | | | | | | | | +| H4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| H5 | | | PS_DDR_VRP_502 | PSS IO | | | | | | | | | | | | | +| H6 | | | PS_DDR_VREF0_502 | PSS IO | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| H9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H12 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H14 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| H15 | je[3] | High Range | IO_L19P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H16 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | +| H17 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | +| H18 | | High Range | IO_L14N_T2_AD4N_SRCC_35 | User IO | | 35 | | | | | | | | | | | +| H19 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H20 | | High Range | IO_L17N_T2_AD5N_35 | User IO | | 35 | | | | | | | | | | | +| J1 | | | PS_DDR_DQ15_502 | PSS IO | | | | | | | | | | | | | +| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J3 | | | PS_DDR_DQ12_502 | PSS IO | | | | | | | | | | | | | +| J4 | | | PS_DDR_A9_502 | PSS IO | | | | | | | | | | | | | +| J5 | | | PS_DDR_BA2_502 | PSS IO | | | | | | | | | | | | | +| J6 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | +| J7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J9 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | +| J10 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | +| J11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| J14 | | High Range | IO_L20N_T3_AD6N_35 | User IO | | 35 | | | | | | | | | | | +| J15 | je[2] | High Range | IO_25_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J16 | | High Range | IO_L24N_T3_AD15N_35 | User IO | | 35 | | | | | | | | | | | +| J17 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| J18 | | High Range | IO_L14P_T2_AD4P_SRCC_35 | User IO | | 35 | | | | | | | | | | | +| J19 | | High Range | IO_L10N_T1_AD11N_35 | User IO | | 35 | | | | | | | | | | | +| J20 | | High Range | IO_L17P_T2_AD5P_35 | User IO | | 35 | | | | | | | | | | | +| K1 | | | PS_DDR_A8_502 | PSS IO | | | | | | | | | | | | | +| K2 | | | PS_DDR_A1_502 | PSS IO | | | | | | | | | | | | | +| K3 | | | PS_DDR_A3_502 | PSS IO | | | | | | | | | | | | | +| K4 | | | PS_DDR_A7_502 | PSS IO | | | | | | | | | | | | | +| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K6 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| K9 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | +| K10 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K12 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K14 | | High Range | IO_L20P_T3_AD6P_35 | User IO | | 35 | | | | | | | | | | | +| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K16 | | High Range | IO_L24P_T3_AD15P_35 | User IO | | 35 | | | | | | | | | | | +| K17 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | +| K18 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | +| K19 | | High Range | IO_L10P_T1_AD11P_35 | User IO | | 35 | | | | | | | | | | | +| K20 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| L1 | | | PS_DDR_A5_502 | PSS IO | | | | | | | | | | | | | +| L2 | | | PS_DDR_CKP_502 | PSS IO | | | | | | | | | | | | | +| L3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| L4 | | | PS_DDR_A6_502 | PSS IO | | | | | | | | | | | | | +| L5 | | | PS_DDR_BA0_502 | PSS IO | | | | | | | | | | | | | +| L6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | +| L7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L9 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | +| L10 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | +| L11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| L14 | | High Range | IO_L22P_T3_AD7P_35 | User IO | | 35 | | | | | | | | | | | +| L15 | | High Range | IO_L22N_T3_AD7N_35 | User IO | | 35 | | | | | | | | | | | +| L16 | clk | High Range | IO_L11P_T1_SRCC_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | +| L17 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | +| L18 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L19 | | High Range | IO_L9P_T1_DQS_AD3P_35 | User IO | | 35 | | | | | | | | | | | +| L20 | | High Range | IO_L9N_T1_DQS_AD3N_35 | User IO | | 35 | | | | | | | | | | | +| M1 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M2 | | | PS_DDR_CKN_502 | PSS IO | | | | | | | | | | | | | +| M3 | | | PS_DDR_A2_502 | PSS IO | | | | | | | | | | | | | +| M4 | | | PS_DDR_A4_502 | PSS IO | | | | | | | | | | | | | +| M5 | | | PS_DDR_WE_B_502 | PSS IO | | | | | | | | | | | | | +| M6 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| M9 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | +| M10 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M12 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M14 | led[0] | High Range | IO_L23P_T3_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M15 | led[1] | High Range | IO_L23N_T3_35 | TRISTATE | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M16 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | +| M17 | | High Range | IO_L8P_T1_AD10P_35 | User IO | | 35 | | | | | | | | | | | +| M18 | | High Range | IO_L8N_T1_AD10N_35 | User IO | | 35 | | | | | | | | | | | +| M19 | | High Range | IO_L7P_T1_AD2P_35 | User IO | | 35 | | | | | | | | | | | +| M20 | | High Range | IO_L7N_T1_AD2N_35 | User IO | | 35 | | | | | | | | | | | +| N1 | | | PS_DDR_CS_B_502 | PSS IO | | | | | | | | | | | | | +| N2 | | | PS_DDR_A0_502 | PSS IO | | | | | | | | | | | | | +| N3 | | | PS_DDR_CKE_502 | PSS IO | | | | | | | | | | | | | +| N4 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N5 | | | PS_DDR_ODT_502 | PSS IO | | | | | | | | | | | | | +| N6 | | | RSVDVCC3 | Reserved | | | | | | | | | | | | | +| N7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N15 | | High Range | IO_L21P_T3_DQS_AD14P_35 | User IO | | 35 | | | | | | | | | | | +| N16 | | High Range | IO_L21N_T3_DQS_AD14N_35 | User IO | | 35 | | | | | | | | | | | +| N17 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | +| N18 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | +| N19 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| N20 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | +| P1 | | | PS_DDR_DQ16_502 | PSS IO | | | | | | | | | | | | | +| P2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| P3 | | | PS_DDR_DQ17_502 | PSS IO | | | | | | | | | | | | | +| P4 | | | PS_DDR_RAS_B_502 | PSS IO | | | | | | | | | | | | | +| P5 | | | PS_DDR_CAS_B_502 | PSS IO | | | | | | | | | | | | | +| P6 | | | PS_DDR_VREF1_502 | PSS IO | | | | | | | | | | | | | +| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P8 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P12 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P14 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | +| P15 | sw[1] | High Range | IO_L24P_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | +| P16 | btn[1] | High Range | IO_L24N_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | +| P17 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P18 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | +| P19 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | +| P20 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | +| R1 | | | PS_DDR_DQ19_502 | PSS IO | | | | | | | | | | | | | +| R2 | | | PS_DDR_DQS_P2_502 | PSS IO | | | | | | | | | | | | | +| R3 | | | PS_DDR_DQ18_502 | PSS IO | | | | | | | | | | | | | +| R4 | | | PS_DDR_BA1_502 | PSS IO | | | | | | | | | | | | | +| R5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| R6 | | | RSVDVCC2 | Reserved | | | | | | | | | | | | | +| R7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| R10 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | +| R11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | +| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| R13 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| R14 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | +| R15 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| R16 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | +| R17 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | +| R18 | btn[0] | High Range | IO_L20N_T3_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | +| R19 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | +| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | +| T1 | | | PS_DDR_DM2_502 | PSS IO | | | | | | | | | | | | | +| T2 | | | PS_DDR_DQS_N2_502 | PSS IO | | | | | | | | | | | | | +| T3 | | | GND | GND | | | | | | | 0.0 | | | | | | +| T4 | | | PS_DDR_DQ20_502 | PSS IO | | | | | | | | | | | | | +| T5 | | | NC | Not Connected | | | | | | | | | | | | | +| T6 | | | RSVDVCC1 | Reserved | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| T8 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | +| T9 | | | NC | Not Connected | | | | | | | | | | | | | +| T10 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | +| T11 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | +| T12 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | +| T13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| T14 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | +| T15 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | +| T16 | sw[3] | High Range | IO_L9P_T1_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | +| T17 | je[6] | High Range | IO_L20P_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| T18 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| T19 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | +| T20 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | +| U1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| U2 | | | PS_DDR_DQ22_502 | PSS IO | | | | | | | | | | | | | +| U3 | | | PS_DDR_DQ23_502 | PSS IO | | | | | | | | | | | | | +| U4 | | | PS_DDR_DQ21_502 | PSS IO | | | | | | | | | | | | | +| U5 | | | NC | Not Connected | | | | | | | | | | | | | +| U6 | | | GND | GND | | | | | | | 0.0 | | | | | | +| U7 | | | NC | Not Connected | | | | | | | | | | | | | +| U8 | | | NC | Not Connected | | | | | | | | | | | | | +| U9 | | | NC | Not Connected | | | | | | | | | | | | | +| U10 | | | NC | Not Connected | | | | | | | | | | | | | +| U11 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | +| U12 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | +| U13 | | High Range | IO_L3P_T0_DQS_PUDC_B_34 | User IO | | 34 | | | | | | | | | | | +| U14 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | +| U15 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | +| U16 | | | GND | GND | | | | | | | 0.0 | | | | | | +| U17 | je[5] | High Range | IO_L9N_T1_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| U18 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | +| U19 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | +| U20 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | +| V1 | | | PS_DDR_DQ24_502 | PSS IO | | | | | | | | | | | | | +| V2 | | | PS_DDR_DQ30_502 | PSS IO | | | | | | | | | | | | | +| V3 | | | PS_DDR_DQ31_502 | PSS IO | | | | | | | | | | | | | +| V4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| V5 | | | NC | Not Connected | | | | | | | | | | | | | +| V6 | | | NC | Not Connected | | | | | | | | | | | | | +| V7 | | | NC | Not Connected | | | | | | | | | | | | | +| V8 | | | NC | Not Connected | | | | | | | | | | | | | +| V9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| V10 | | | NC | Not Connected | | | | | | | | | | | | | +| V11 | | | NC | Not Connected | | | | | | | | | | | | | +| V12 | je[0] | High Range | IO_L4P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| V13 | je[4] | High Range | IO_L3N_T0_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| V14 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| V15 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | +| V16 | btn[2] | High Range | IO_L18P_T2_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | +| V17 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | +| V18 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | +| V19 | | | GND | GND | | | | | | | 0.0 | | | | | | +| V20 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | +| W1 | | | PS_DDR_DQ26_502 | PSS IO | | | | | | | | | | | | | +| W2 | | | GND | GND | | | | | | | 0.0 | | | | | | +| W3 | | | PS_DDR_DQ29_502 | PSS IO | | | | | | | | | | | | | +| W4 | | | PS_DDR_DQS_N3_502 | PSS IO | | | | | | | | | | | | | +| W5 | | | PS_DDR_DQS_P3_502 | PSS IO | | | | | | | | | | | | | +| W6 | | | NC | Not Connected | | | | | | | | | | | | | +| W7 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | +| W8 | | | NC | Not Connected | | | | | | | | | | | | | +| W9 | | | NC | Not Connected | | | | | | | | | | | | | +| W10 | | | NC | Not Connected | | | | | | | | | | | | | +| W11 | | | NC | Not Connected | | | | | | | | | | | | | +| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| W13 | sw[2] | High Range | IO_L4N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | +| W14 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | +| W15 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | +| W16 | je[1] | High Range | IO_L18N_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| W17 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| W18 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | +| W19 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | +| W20 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | +| Y1 | | | PS_DDR_DM3_502 | PSS IO | | | | | | | | | | | | | +| Y2 | | | PS_DDR_DQ28_502 | PSS IO | | | | | | | | | | | | | +| Y3 | | | PS_DDR_DQ25_502 | PSS IO | | | | | | | | | | | | | +| Y4 | | | PS_DDR_DQ27_502 | PSS IO | | | | | | | | | | | | | +| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| Y6 | | | NC | Not Connected | | | | | | | | | | | | | +| Y7 | | | NC | Not Connected | | | | | | | | | | | | | +| Y8 | | | NC | Not Connected | | | | | | | | | | | | | +| Y9 | | | NC | Not Connected | | | | | | | | | | | | | +| Y10 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | +| Y11 | | | NC | Not Connected | | | | | | | | | | | | | +| Y12 | | | NC | Not Connected | | | | | | | | | | | | | +| Y13 | | | NC | Not Connected | | | | | | | | | | | | | +| Y14 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | +| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | +| Y16 | btn[3] | High Range | IO_L7P_T1_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | +| Y17 | je[7] | High Range | IO_L7N_T1_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| Y18 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | +| Y19 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | +| Y20 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | ++------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpt b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpt new file mode 100644 index 0000000..3b3c2da --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpt @@ -0,0 +1,185 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:42:07 2017 +| Host : comparch-VirtualBox running 64-bit unknown +| Command : report_methodology -file lab2_wrapper_methodology_drc_routed.rpt -rpx lab2_wrapper_methodology_drc_routed.rpx +| Design : lab2_wrapper +| Device : xc7z010clg400-1 +| Speed File : -1 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 30 ++-----------+----------+-----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-----------------------------+------------+ +| TIMING-17 | Warning | Non-clocked sequential cell | 30 | ++-----------+----------+-----------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-17#1 Warning +Non-clocked sequential cell +The clock pin mid/SCLKCond/conditioned_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Warning +Non-clocked sequential cell +The clock pin mid/SCLKCond/counter_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Warning +Non-clocked sequential cell +The clock pin mid/SCLKCond/counter_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#4 Warning +Non-clocked sequential cell +The clock pin mid/SCLKCond/positiveedge_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#5 Warning +Non-clocked sequential cell +The clock pin mid/SCLKCond/synchronizer0_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#6 Warning +Non-clocked sequential cell +The clock pin mid/SCLKCond/synchronizer1_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#7 Warning +Non-clocked sequential cell +The clock pin mid/parallelLoadCond/conditioned_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#8 Warning +Non-clocked sequential cell +The clock pin mid/parallelLoadCond/counter_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#9 Warning +Non-clocked sequential cell +The clock pin mid/parallelLoadCond/counter_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#10 Warning +Non-clocked sequential cell +The clock pin mid/parallelLoadCond/negativeedge_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#11 Warning +Non-clocked sequential cell +The clock pin mid/parallelLoadCond/synchronizer0_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#12 Warning +Non-clocked sequential cell +The clock pin mid/parallelLoadCond/synchronizer1_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#13 Warning +Non-clocked sequential cell +The clock pin mid/serialInCond/conditioned_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#14 Warning +Non-clocked sequential cell +The clock pin mid/serialInCond/counter_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#15 Warning +Non-clocked sequential cell +The clock pin mid/serialInCond/counter_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#16 Warning +Non-clocked sequential cell +The clock pin mid/serialInCond/synchronizer0_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#17 Warning +Non-clocked sequential cell +The clock pin mid/serialInCond/synchronizer1_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#18 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#19 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#20 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#21 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[2]_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#22 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#23 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[3]_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#24 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[4]/C is not reached by a timing clock +Related violations: + +TIMING-17#25 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#26 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[5]_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#27 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#28 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[6]_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#29 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#30 Warning +Non-clocked sequential cell +The clock pin mid/shift/shiftregistermem_reg[7]_lopt_replica/C is not reached by a timing clock +Related violations: + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpx b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpx new file mode 100644 index 0000000..544aec4 Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpx differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_opt.dcp b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_opt.dcp new file mode 100644 index 0000000..4557a7e Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_opt.dcp differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_placed.dcp b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_placed.dcp new file mode 100644 index 0000000..5fc71f5 Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_placed.dcp differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_power_routed.rpt b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_power_routed.rpt new file mode 100644 index 0000000..7417f2a --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_power_routed.rpt @@ -0,0 +1,152 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:42:08 2017 +| Host : comparch-VirtualBox running 64-bit unknown +| Command : report_power -file lab2_wrapper_power_routed.rpt -pb lab2_wrapper_power_summary_routed.pb -rpx lab2_wrapper_power_routed.rpx +| Design : lab2_wrapper +| Device : xc7z010clg400-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+-------+ +| Total On-Chip Power (W) | 0.803 | +| Dynamic (W) | 0.693 | +| Device Static (W) | 0.110 | +| Effective TJA (C/W) | 11.5 | +| Max Ambient (C) | 75.7 | +| Junction Temperature (C) | 34.3 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+-------+ + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.087 | 56 | --- | --- | +| LUT as Logic | 0.074 | 9 | 17600 | 0.05 | +| Register | 0.007 | 30 | 35200 | 0.09 | +| BUFG | 0.006 | 1 | 32 | 3.13 | +| Others | 0.000 | 10 | --- | --- | +| Signals | 0.060 | 36 | --- | --- | +| I/O | 0.546 | 16 | 100 | 16.00 | +| Static Power | 0.110 | | | | +| Total | 0.803 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.168 | 0.163 | 0.005 | +| Vccaux | 1.800 | 0.031 | 0.019 | 0.011 | +| Vcco33 | 3.300 | 0.151 | 0.150 | 0.001 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccpint | 1.000 | 0.021 | 0.000 | 0.021 | +| Vccpaux | 1.800 | 0.010 | 0.000 | 0.010 | +| Vccpll | 1.800 | 0.003 | 0.000 | 0.003 | +| Vcco_ddr | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco_mio0 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco_mio1 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 11.5 | +| Airflow (LFM) | 250 | +| Heat Sink | none | +| ThetaSA (C/W) | 0.0 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 8to11 (8 to 11 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++----------------------+-----------+ +| Name | Power (W) | ++----------------------+-----------+ +| lab2_wrapper | 0.693 | +| mid | 0.122 | +| SCLKCond | 0.040 | +| parallelLoadCond | 0.042 | +| serialInCond | 0.034 | +| shift | 0.005 | ++----------------------+-----------+ + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_power_routed.rpx b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_power_routed.rpx new file mode 100644 index 0000000..0e85626 Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_power_routed.rpx differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_power_summary_routed.pb b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_power_summary_routed.pb new file mode 100644 index 0000000..4c09087 Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_power_summary_routed.pb differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_route_status.pb b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_route_status.pb new file mode 100644 index 0000000..67b0300 Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_route_status.pb differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_route_status.rpt b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_route_status.rpt new file mode 100644 index 0000000..38f1d73 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 69 : + # of nets not needing routing.......... : 31 : + # of internally routed nets........ : 31 : + # of routable nets..................... : 38 : + # of fully routed nets............. : 38 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_routed.dcp b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_routed.dcp new file mode 100644 index 0000000..47d2883 Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_routed.dcp differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_timing_summary_routed.rpt b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_timing_summary_routed.rpt new file mode 100644 index 0000000..7fbb953 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_timing_summary_routed.rpt @@ -0,0 +1,173 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:42:08 2017 +| Host : comparch-VirtualBox running 64-bit unknown +| Command : report_timing_summary -warn_on_violation -max_paths 10 -file lab2_wrapper_timing_summary_routed.rpt -rpx lab2_wrapper_timing_summary_routed.rpx +| Design : lab2_wrapper +| Device : 7z010-clg400 +| Speed File : -1 PRODUCTION 1.11 2014-09-11 +----------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 30 register/latch pins with no clock driven by root clock pin: clk (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 50 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 3 input ports with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 9 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_timing_summary_routed.rpx b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_timing_summary_routed.rpx new file mode 100644 index 0000000..d14cceb Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_timing_summary_routed.rpx differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_utilization_placed.pb b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_utilization_placed.pb new file mode 100644 index 0000000..aa7f286 Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_utilization_placed.pb differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_utilization_placed.rpt b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_utilization_placed.rpt new file mode 100644 index 0000000..63a8fb8 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/lab2_wrapper_utilization_placed.rpt @@ -0,0 +1,204 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:41:44 2017 +| Host : comparch-VirtualBox running 64-bit Ubuntu 16.04.3 LTS +| Command : report_utilization -file lab2_wrapper_utilization_placed.rpt -pb lab2_wrapper_utilization_placed.pb +| Design : lab2_wrapper +| Device : 7z010clg400-1 +| Design State : Fully Placed +--------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 9 | 0 | 17600 | 0.05 | +| LUT as Logic | 9 | 0 | 17600 | 0.05 | +| LUT as Memory | 0 | 0 | 6000 | 0.00 | +| Slice Registers | 30 | 0 | 35200 | 0.09 | +| Register as Flip Flop | 30 | 0 | 35200 | 0.09 | +| Register as Latch | 0 | 0 | 35200 | 0.00 | +| F7 Muxes | 0 | 0 | 8800 | 0.00 | +| F8 Muxes | 0 | 0 | 4400 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 2 | Yes | Set | - | +| 28 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++-------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------------------------+------+-------+-----------+-------+ +| Slice | 13 | 0 | 4400 | 0.30 | +| SLICEL | 3 | 0 | | | +| SLICEM | 10 | 0 | | | +| LUT as Logic | 9 | 0 | 17600 | 0.05 | +| using O5 output only | 0 | | | | +| using O6 output only | 3 | | | | +| using O5 and O6 | 6 | | | | +| LUT as Memory | 0 | 0 | 6000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 8 | 0 | 17600 | 0.05 | +| fully used LUT-FF pairs | 6 | | | | +| LUT-FF pairs with one unused LUT output | 2 | | | | +| LUT-FF pairs with one unused Flip Flop | 2 | | | | +| Unique Control Sets | 2 | | | | ++-------------------------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 60 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 60 | 0.00 | +| RAMB18 | 0 | 0 | 120 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 80 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 16 | 16 | 100 | 16.00 | +| IOB Master Pads | 6 | | | | +| IOB Slave Pads | 8 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 2 | 0.00 | +| PHASER_REF | 0 | 0 | 2 | 0.00 | +| OUT_FIFO | 0 | 0 | 8 | 0.00 | +| IN_FIFO | 0 | 0 | 8 | 0.00 | +| IDELAYCTRL | 0 | 0 | 2 | 0.00 | +| IBUFDS | 0 | 0 | 96 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 | +| ILOGIC | 0 | 0 | 100 | 0.00 | +| OLOGIC | 0 | 0 | 100 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 8 | 0.00 | +| MMCME2_ADV | 0 | 0 | 2 | 0.00 | +| PLLE2_ADV | 0 | 0 | 2 | 0.00 | +| BUFMRCE | 0 | 0 | 4 | 0.00 | +| BUFHCE | 0 | 0 | 48 | 0.00 | +| BUFR | 0 | 0 | 8 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 28 | Flop & Latch | +| OBUF | 9 | IO | +| LUT4 | 9 | LUT | +| IBUF | 4 | IO | +| OBUFT | 3 | IO | +| LUT3 | 3 | LUT | +| LUT5 | 2 | LUT | +| FDSE | 2 | Flop & Latch | +| LUT2 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/opt_design.pb b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..f4cd8a0 Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/opt_design.pb differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/place_design.pb b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/place_design.pb new file mode 100644 index 0000000..b515221 Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/place_design.pb differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/project.wdf b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/project.wdf new file mode 100644 index 0000000..cb5b706 --- /dev/null +++ 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0000000..dedee3e Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/route_design.pb differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/rundef.js b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/rundef.js new file mode 100644 index 0000000..4ab95d5 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/rundef.js @@ -0,0 +1,44 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/opt/Xilinx/SDK/2017.2/bin:/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2017.2/bin;"; +} else { + PathVal = "/opt/Xilinx/SDK/2017.2/bin:/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2017.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "write_bitstream", "begin" ); +ISEStep( "vivado", + "-log lab2_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/runme.bat b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/runme.bat new file mode 100644 index 0000000..220ba68 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/runme.log b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/runme.log new file mode 100644 index 0000000..c4a7f8a --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/runme.log @@ -0,0 +1,442 @@ + +*** Running vivado + with args -log lab2_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace + + +****** Vivado v2017.2 (64-bit) + **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 + **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 + ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + +source lab2_wrapper.tcl -notrace +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1307.199 ; gain = 222.145 ; free physical = 70 ; free virtual = 1346 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command opt_design + +Starting DRC Task +Command: report_drc (run_mandatory_drcs) for: opt_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.33 . Memory (MB): peak = 1316.203 ; gain = 9.004 ; free physical = 67 ; free virtual = 1344 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1713a94cd + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 92 ; free virtual = 989 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1713a94cd + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 91 ; free virtual = 989 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: cad9f257 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 88 ; free virtual = 989 +INFO: [Opt 31-389] Phase Sweep created 5 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: cad9f257 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 87 ; free virtual = 989 +INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: cad9f257 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 87 ; free virtual = 989 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 87 ; free virtual = 989 +Ending Logic Optimization Task | Checksum: cad9f257 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 87 ; free virtual = 989 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1b281726d + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 84 ; free virtual = 989 +20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:16 . Memory (MB): peak = 1772.695 ; gain = 465.496 ; free physical = 83 ; free virtual = 989 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1772.695 ; gain = 0.000 ; free physical = 75 ; free virtual = 989 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper_opt.dcp' has been generated. +Command: report_drc -file lab2_wrapper_drc_opted.rpt +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper_drc_opted.rpt. +report_drc completed successfully +INFO: [Chipscope 16-241] No debug cores found in the current design. +Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) +or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Command: report_drc (run_mandatory_drcs) for: incr_eco_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +Command: report_drc (run_mandatory_drcs) for: placer_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 980 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 16eb3a3f6 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 980 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 980 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f9eb0a13 + +Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.92 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 66 ; free virtual = 980 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1a55c9a0e + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.98 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 63 ; free virtual = 980 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1a55c9a0e + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 979 +Phase 1 Placer Initialization | Checksum: 1a55c9a0e + +Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 979 + +Phase 2 Global Placement +WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 131b360c7 + +Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 978 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 131b360c7 + +Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 978 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1ef7f9f6e + +Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 978 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 154ee63e4 + +Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 978 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 154ee63e4 + +Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 74 ; free virtual = 978 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 +Phase 3 Detail Placement | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: a5397dd8 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: f40da953 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: f40da953 + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 977 +Ending Placer Task | Checksum: 902b657c + +Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 70 ; free virtual = 978 +31 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 69 ; free virtual = 980 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper_placed.dcp' has been generated. +report_io: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 81 ; free virtual = 971 +report_utilization: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 87 ; free virtual = 979 +report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1780.699 ; gain = 0.000 ; free physical = 85 ; free virtual = 977 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command route_design +Command: report_drc (run_mandatory_drcs) for: router_checks +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +Checksum: PlaceDB: 3337b348 ConstDB: 0 ShapeSum: 5cf3b234 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 16ed4557e + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1820.699 ; gain = 40.000 ; free physical = 91 ; free virtual = 902 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 16ed4557e + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1824.699 ; gain = 44.000 ; free physical = 81 ; free virtual = 899 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 16ed4557e + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1824.699 ; gain = 44.000 ; free physical = 81 ; free virtual = 899 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: c9ab31ea + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 892 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 5e036487 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 74 ; free virtual = 894 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 893 +Phase 4 Rip-up And Reroute | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 893 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 894 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 894 +Phase 6 Post Hold Fix | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 894 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.0343468 % + Global Horizontal Routing Utilization = 0.00804228 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 17.1171%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. +Phase 7 Route finalize | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1832.699 ; gain = 52.000 ; free physical = 73 ; free virtual = 894 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: a7484467 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1834.699 ; gain = 54.000 ; free physical = 73 ; free virtual = 893 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 86e4b1c5 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1834.699 ; gain = 54.000 ; free physical = 72 ; free virtual = 893 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1834.699 ; gain = 54.000 ; free physical = 70 ; free virtual = 895 + +Routing Is Done. +37 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 1868.590 ; gain = 87.891 ; free physical = 64 ; free virtual = 895 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1868.590 ; gain = 0.000 ; free physical = 79 ; free virtual = 888 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper_routed.dcp' has been generated. +Command: report_drc -file lab2_wrapper_drc_routed.rpt -pb lab2_wrapper_drc_routed.pb -rpx lab2_wrapper_drc_routed.rpx +INFO: [Coretcl 2-168] The results of DRC are in file /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper_drc_routed.rpt. +report_drc completed successfully +Command: report_methodology -file lab2_wrapper_methodology_drc_routed.rpt -rpx lab2_wrapper_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper_methodology_drc_routed.rpt. +report_methodology completed successfully +Command: report_power -file lab2_wrapper_power_routed.rpt -pb lab2_wrapper_power_summary_routed.pb -rpx lab2_wrapper_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +42 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:42:09 2017... + +*** Running vivado + with args -log lab2_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace + + +****** Vivado v2017.2 (64-bit) + **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 + **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 + ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + +source lab2_wrapper.tcl -notrace +Command: open_checkpoint lab2_wrapper_routed.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1083.039 ; gain = 0.000 ; free physical = 485 ; free virtual = 1615 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +/opt/Xilinx/Vivado/2017.2/bin/loader: line 179: 14511 Killed "$RDI_PROG" "$@" + +*** Running vivado + with args -log lab2_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace + + +****** Vivado v2017.2 (64-bit) + **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 + **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 + ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + +source lab2_wrapper.tcl -notrace +Command: open_checkpoint lab2_wrapper_routed.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1083.047 ; gain = 0.000 ; free physical = 386 ; free virtual = 1598 +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2017.2 +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14667-comparch-VirtualBox/dcp3/lab2_wrapper.xdc] +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/.Xil/Vivado-14667-comparch-VirtualBox/dcp3/lab2_wrapper.xdc] +Reading XDEF placement. +Reading placer database... +Reading XDEF routing. +Read XDEF File: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1304.207 ; gain = 0.000 ; free physical = 114 ; free virtual = 1343 +Restored from archive | CPU: 0.010000 secs | Memory: 0.063492 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1304.207 ; gain = 0.000 ; free physical = 114 ; free virtual = 1343 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2017.2 (64-bit) build 1909853 +open_checkpoint: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1304.207 ; gain = 221.160 ; free physical = 115 ; free virtual = 1342 +Command: write_bitstream -force lab2_wrapper.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010-clg400' +Running DRC as a precondition to command write_bitstream +Command: report_drc (run_mandatory_drcs) for: bitstream_checks +WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. +report_drc (run_mandatory_drcs) completed successfully +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./lab2_wrapper.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-186] '/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Wed Oct 25 21:44:09 2017. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. +14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:23 . Memory (MB): peak = 1718.027 ; gain = 413.820 ; free physical = 362 ; free virtual = 1318 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:44:09 2017... diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/runme.sh b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/runme.sh new file mode 100755 index 0000000..2433908 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/opt/Xilinx/SDK/2017.2/bin:/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2017.2/bin +else + PATH=/opt/Xilinx/SDK/2017.2/bin:/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2017.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64 +else + LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .write_bitstream.begin.rst +EAStep vivado -log lab2_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/usage_statistics_webtalk.html b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/usage_statistics_webtalk.html new file mode 100644 index 0000000..123be0e --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/usage_statistics_webtalk.html @@ -0,0 +1,462 @@ +Device Usage Statistics Report +

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version1909853
date_generatedWed Oct 25 21:44:05 2017os_platformLIN64
product_versionVivado v2017.2 (64-bit)project_idbf3d9855daff4eaa8028db1a5c4ed7e4
project_iteration1random_id260071bf-5dad-4818-bd9c-a4f9ad540bfd
registration_id260071bf-5dad-4818-bd9c-a4f9ad540bfdroute_designTRUE
target_devicexc7z010target_familyzynq
target_packageclg400target_speed-1
tool_flowVivado

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Core(TM) i7-4610M CPU @ 3.00GHzcpu_speed2993.344 MHz
os_nameUbuntuos_releaseUbuntu 16.04.3 LTS
system_ram2.000 GBtotal_processors1

+ + +
vivado_usage
+ + + + + + + +
java_command_handlers
addsources=2autoconnecttarget=1openhardwaremanager=1runbitgen=2
runimplementation=1runsynthesis=1
+ + + +
other_data
guimode=1
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
project_data
constraintsetcount=1core_container=falsecurrentimplrun=impl_1currentsynthesisrun=synth_1
default_library=xil_defaultlibdesignmode=RTLexport_simulation_activehdl=0export_simulation_ies=0
export_simulation_modelsim=0export_simulation_questa=0export_simulation_riviera=0export_simulation_vcs=0
export_simulation_xsim=0implstrategy=Vivado Implementation Defaultslaunch_simulation_activehdl=0launch_simulation_ies=0
launch_simulation_modelsim=0launch_simulation_questa=0launch_simulation_riviera=0launch_simulation_vcs=0
launch_simulation_xsim=0simulator_language=Mixedsrcsetcount=4synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilogtarget_simulator=XSimtotalimplruns=1totalsynthesisruns=1
+
+ + + + +
unisim_transformation
+ + + + + + + + + + + + + + +
post_unisim_transformation
bufg=1fdre=24fdse=1gnd=5
ibuf=4lut2=1lut3=3lut4=9
lut5=2obuf=9obuft=3vcc=5
+
+ + + + + + + + + + + + + + +
pre_unisim_transformation
bufg=1fdre=24fdse=1gnd=5
ibuf=4lut2=1lut3=3lut4=9
lut5=2obuf=9obuft=3vcc=5
+

+ + + + +
report_drc
+ + + + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-messages=default::[not_specified]-name=default::[not_specified]-return_string=default::[not_specified]
-ruledecks=default::[not_specified]-upgrade_cw=default::[not_specified]-waived=default::[not_specified]
+
+ + + +
results
zps7-1=1
+

+ + + + + + + + + +
report_utilization
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
clocking
bufgctrl_available=32bufgctrl_fixed=0bufgctrl_used=1bufgctrl_util_percentage=3.13
bufhce_available=48bufhce_fixed=0bufhce_used=0bufhce_util_percentage=0.00
bufio_available=8bufio_fixed=0bufio_used=0bufio_util_percentage=0.00
bufmrce_available=4bufmrce_fixed=0bufmrce_used=0bufmrce_util_percentage=0.00
bufr_available=8bufr_fixed=0bufr_used=0bufr_util_percentage=0.00
mmcme2_adv_available=2mmcme2_adv_fixed=0mmcme2_adv_used=0mmcme2_adv_util_percentage=0.00
plle2_adv_available=2plle2_adv_fixed=0plle2_adv_used=0plle2_adv_util_percentage=0.00
+
+ + + + + + +
dsp
dsps_available=80dsps_fixed=0dsps_used=0dsps_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
io_standard
blvds_25=0diff_hstl_i=0diff_hstl_i_18=0diff_hstl_ii=0
diff_hstl_ii_18=0diff_hsul_12=0diff_mobile_ddr=0diff_sstl135=0
diff_sstl135_r=0diff_sstl15=0diff_sstl15_r=0diff_sstl18_i=0
diff_sstl18_ii=0hstl_i=0hstl_i_18=0hstl_ii=0
hstl_ii_18=0hsul_12=0lvcmos12=0lvcmos15=0
lvcmos18=0lvcmos25=0lvcmos33=1lvds_25=0
lvttl=0mini_lvds_25=0mobile_ddr=0pci33_3=0
ppds_25=0rsds_25=0sstl135=0sstl135_r=0
sstl15=0sstl15_r=0sstl18_i=0sstl18_ii=0
tmds_33=0
+
+ + + + + + + + + + + + + + +
memory
block_ram_tile_available=60block_ram_tile_fixed=0block_ram_tile_used=0block_ram_tile_util_percentage=0.00
ramb18_available=120ramb18_fixed=0ramb18_used=0ramb18_util_percentage=0.00
ramb36_fifo_available=60ramb36_fifo_fixed=0ramb36_fifo_used=0ramb36_fifo_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + +
primitives
bufg_functional_category=Clockbufg_used=1fdre_functional_category=Flop & Latchfdre_used=28
fdse_functional_category=Flop & Latchfdse_used=2ibuf_functional_category=IOibuf_used=4
lut2_functional_category=LUTlut2_used=1lut3_functional_category=LUTlut3_used=3
lut4_functional_category=LUTlut4_used=9lut5_functional_category=LUTlut5_used=2
obuf_functional_category=IOobuf_used=9obuft_functional_category=IOobuft_used=3
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
slice_logic
f7_muxes_available=8800f7_muxes_fixed=0f7_muxes_used=0f7_muxes_util_percentage=0.00
f8_muxes_available=4400f8_muxes_fixed=0f8_muxes_used=0f8_muxes_util_percentage=0.00
lut_as_logic_available=17600lut_as_logic_fixed=0lut_as_logic_used=9lut_as_logic_util_percentage=0.05
lut_as_memory_available=6000lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=35200register_as_flip_flop_fixed=0register_as_flip_flop_used=30register_as_flip_flop_util_percentage=0.09
register_as_latch_available=35200register_as_latch_fixed=0register_as_latch_used=0register_as_latch_util_percentage=0.00
slice_luts_available=17600slice_luts_fixed=0slice_luts_used=9slice_luts_util_percentage=0.05
slice_registers_available=35200slice_registers_fixed=0slice_registers_used=30slice_registers_util_percentage=0.09
fully_used_lut_ff_pairs_fixed=0.09fully_used_lut_ff_pairs_used=6lut_as_distributed_ram_fixed=0lut_as_distributed_ram_used=0
lut_as_logic_available=17600lut_as_logic_fixed=0lut_as_logic_used=9lut_as_logic_util_percentage=0.05
lut_as_memory_available=6000lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0lut_as_shift_register_used=0lut_ff_pairs_with_one_unused_flip_flop_fixed=0lut_ff_pairs_with_one_unused_flip_flop_used=2
lut_ff_pairs_with_one_unused_lut_output_fixed=2lut_ff_pairs_with_one_unused_lut_output_used=2lut_flip_flop_pairs_available=17600lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=8lut_flip_flop_pairs_util_percentage=0.05slice_available=4400slice_fixed=0
slice_used=13slice_util_percentage=0.30slicel_fixed=0slicel_used=3
slicem_fixed=0slicem_used=10unique_control_sets_used=2using_o5_and_o6_fixed=2
using_o5_and_o6_used=6using_o5_output_only_fixed=6using_o5_output_only_used=0using_o6_output_only_fixed=0
using_o6_output_only_used=3
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
specific_feature
bscane2_available=4bscane2_fixed=0bscane2_used=0bscane2_util_percentage=0.00
capturee2_available=1capturee2_fixed=0capturee2_used=0capturee2_util_percentage=0.00
dna_port_available=1dna_port_fixed=0dna_port_used=0dna_port_util_percentage=0.00
efuse_usr_available=1efuse_usr_fixed=0efuse_usr_used=0efuse_usr_util_percentage=0.00
frame_ecce2_available=1frame_ecce2_fixed=0frame_ecce2_used=0frame_ecce2_util_percentage=0.00
icape2_available=2icape2_fixed=0icape2_used=0icape2_util_percentage=0.00
startupe2_available=1startupe2_fixed=0startupe2_used=0startupe2_util_percentage=0.00
xadc_available=1xadc_fixed=0xadc_used=0xadc_util_percentage=0.00
+

+ + + +
router
+ + + + + + + + + + + + + + + + + + + + + + + + + +
usage
actual_expansions=118571bogomips=5986bram18=0bram36=0
bufg=0bufr=0ctrls=2dsp=0
effort=2estimated_expansions=34068ff=30global_clocks=1
high_fanout_nets=0iob=16lut=9movable_instances=72
nets=77pins=269pll=0router_runtime=0.000000
router_timing_driven=1threads=1timing_constraints_exist=1
+

+ + + + +
synthesis
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-assert=default::[not_specified]-bufg=default::12-cascade_dsp=default::auto-constrset=default::[not_specified]
-control_set_opt_threshold=default::auto-directive=default::default-fanout_limit=default::10000-flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto-gated_clock_conversion=default::off-generic=default::[not_specified]-include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified]-max_bram=default::-1-max_bram_cascade_height=default::-1-max_dsp=default::-1
-max_uram=default::-1-max_uram_cascade_height=default::-1-mode=default::default-name=default::[not_specified]
-no_lc=default::[not_specified]-no_srlextract=default::[not_specified]-no_timing_driven=default::[not_specified]-part=xc7z010clg400-1
-resource_sharing=default::auto-retiming=default::[not_specified]-rtl=default::[not_specified]-rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified]-seu_protect=default::none-sfcu=default::[not_specified]-shreg_min_size=default::3
-top=lab2_wrapper-verilog_define=default::[not_specified]
+
+ + + + + + +
usage
elapsed=00:00:20shls_ip=0memory_gain=382.328MBmemory_peak=1467.387MB
+

+ + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/usage_statistics_webtalk.xml b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..53ba66d --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,410 @@ + + +
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+ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/vivado.jou b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/vivado.jou new file mode 100644 index 0000000..4114d9d --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:43:13 2017 +# Process ID: 14667 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1 +# Command line: vivado -log lab2_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/vivado.pb b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/vivado.pb new file mode 100644 index 0000000..d2bdfb3 Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/vivado.pb differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/vivado_14391.backup.jou b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/vivado_14391.backup.jou new file mode 100644 index 0000000..983b899 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/vivado_14391.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:40:50 2017 +# Process ID: 14391 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1 +# Command line: vivado -log lab2_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/vivado_14511.backup.jou b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/vivado_14511.backup.jou new file mode 100644 index 0000000..36e6208 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/vivado_14511.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:42:20 2017 +# Process ID: 14511 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1 +# Command line: vivado -log lab2_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source lab2_wrapper.tcl -notrace +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/lab2_wrapper.vdi +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/impl_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/write_bitstream.pb b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..eb8a834 Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/impl_1/write_bitstream.pb differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/.Vivado_Synthesis.queue.rst b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/.Xil/lab2_wrapper_propImpl.xdc b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/.Xil/lab2_wrapper_propImpl.xdc new file mode 100644 index 0000000..b433506 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/.Xil/lab2_wrapper_propImpl.xdc @@ -0,0 +1,43 @@ +set_property SRC_FILE_INFO {cfile:/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc rfile:../../../project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L11P_T1_SRCC_35 Sch=sysclk +set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=SW0 +set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=SW1 +set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=SW2 +set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=SW3 +set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L20N_T3_34 Sch=BTN0 +set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=BTN1 +set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L18P_T2_34 Sch=BTN2 +set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=BTN3 +set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=LED0 +set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=LED1 +set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35=Sch=LED2 +set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3 +set_property src_info {type:XDC file:1 line:114 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=JE1 +set_property src_info {type:XDC file:1 line:115 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=JE2 +set_property src_info {type:XDC file:1 line:116 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=JE3 +set_property src_info {type:XDC file:1 line:117 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=JE4 +set_property src_info {type:XDC file:1 line:118 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=JE7 +set_property src_info {type:XDC file:1 line:119 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=JE8 +set_property src_info {type:XDC file:1 line:120 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=JE9 +set_property src_info {type:XDC file:1 line:121 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=JE10 diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/.vivado.begin.rst b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/.vivado.begin.rst new file mode 100644 index 0000000..f37801e --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/.vivado.end.rst b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/ISEWrap.js b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/ISEWrap.js new file mode 100755 index 0000000..8284d2d --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/ISEWrap.js @@ -0,0 +1,244 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/ISEWrap.sh b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/ISEWrap.sh new file mode 100755 index 0000000..e1a8f5d --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/ISEWrap.sh @@ -0,0 +1,63 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/gen_run.xml b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..9ba63be --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/gen_run.xml @@ -0,0 +1,75 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/htr.txt b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/htr.txt new file mode 100644 index 0000000..eb9437d --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# + +vivado -log lab2_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source lab2_wrapper.tcl diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/lab2_wrapper.dcp b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/lab2_wrapper.dcp new file mode 100644 index 0000000..927b105 Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/lab2_wrapper.dcp differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/lab2_wrapper.tcl b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/lab2_wrapper.tcl new file mode 100644 index 0000000..d52a101 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/lab2_wrapper.tcl @@ -0,0 +1,41 @@ +# +# Synthesis run script generated by Vivado +# + +set_param xicom.use_bs_reader 1 +create_project -in_memory -part xc7z010clg400-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.cache/wt [current_project] +set_property parent.project_path /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property board_part digilentinc.com:zybo:part0:1.0 [current_project] +set_property ip_output_repo /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib { + /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/inputconditioner.v + /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/shiftregister.v + /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/midpoint.v + /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/lab2wrapper.v +} +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc +set_property used_in_implementation false [get_files /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] + + +synth_design -top lab2_wrapper -part xc7z010clg400-1 + + +write_checkpoint -force -noxdef lab2_wrapper.dcp + +catch { report_utilization -file lab2_wrapper_utilization_synth.rpt -pb lab2_wrapper_utilization_synth.pb } diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/lab2_wrapper.vds b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/lab2_wrapper.vds new file mode 100644 index 0000000..c6d1dca --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/lab2_wrapper.vds @@ -0,0 +1,327 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:39:31 2017 +# Process ID: 13818 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/synth_1 +# Command line: vivado -log lab2_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source lab2_wrapper.tcl +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/synth_1/lab2_wrapper.vds +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/synth_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace +Command: synth_design -top lab2_wrapper -part xc7z010clg400-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010-clg400' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 14032 +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module inputconditioner [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/inputconditioner.v:9] +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module shiftregister [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/shiftregister.v:9] +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module inputconditioner [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/inputconditioner.v:9] +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module shiftregister [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/shiftregister.v:9] +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module midpoint [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/midpoint.v:7] +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1146.891 ; gain = 49.246 ; free physical = 186 ; free virtual = 1507 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'lab2_wrapper' [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/lab2wrapper.v:23] +INFO: [Synth 8-638] synthesizing module 'midpoint' [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/midpoint.v:7] + Parameter width bound to: 8 - type: integer +INFO: [Synth 8-638] synthesizing module 'inputconditioner' [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/inputconditioner.v:9] + Parameter counterwidth bound to: 3 - type: integer + Parameter waittime bound to: 3 - type: integer +INFO: [Synth 8-256] done synthesizing module 'inputconditioner' (1#1) [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/inputconditioner.v:9] +INFO: [Synth 8-638] synthesizing module 'shiftregister' [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/shiftregister.v:9] + Parameter width bound to: 8 - type: integer +INFO: [Synth 8-256] done synthesizing module 'shiftregister' (2#1) [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/shiftregister.v:9] +INFO: [Synth 8-256] done synthesizing module 'midpoint' (3#1) [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/midpoint.v:7] +WARNING: [Synth 8-3848] Net led in module/entity lab2_wrapper does not have driver. [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/lab2wrapper.v:28] +INFO: [Synth 8-256] done synthesizing module 'lab2_wrapper' (4#1) [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/lab2wrapper.v:23] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[1] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port sw[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port sw[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[1] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1172.141 ; gain = 74.496 ; free physical = 201 ; free virtual = 1523 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 1172.141 ; gain = 74.496 ; free physical = 201 ; free virtual = 1524 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/lab2_wrapper_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/lab2_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1467.379 ; gain = 0.000 ; free physical = 93 ; free virtual = 1277 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 170 ; free virtual = 1361 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z010clg400-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 170 ; free virtual = 1361 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 170 ; free virtual = 1361 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5544] ROM "conditioned" won't be mapped to Block RAM because address size (3) smaller than threshold (5) +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:30 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 161 ; free virtual = 1353 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 3 ++---Registers : + 8 Bit Registers := 1 + 3 Bit Registers := 3 + 1 Bit Registers := 15 ++---Muxes : + 2 Input 8 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 3 + 2 Input 1 Bit Muxes := 15 + 3 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module inputconditioner +Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 1 ++---Registers : + 3 Bit Registers := 1 + 1 Bit Registers := 5 ++---Muxes : + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 +Module shiftregister +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 1 ++---Muxes : + 2 Input 8 Bit Muxes := 1 + 3 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 80 (col length:40) +BRAMs: 120 (col length: RAMB18 40 RAMB36 20) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[1] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port sw[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port sw[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[1] +WARNING: [Synth 8-3332] Sequential element (mid/parallelLoadCond/positiveedge_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/positiveedge_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/negativeedge_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/SCLKCond/negativeedge_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/parallelLoadCond/counter_reg[2]) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/counter_reg[2]) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/SCLKCond/counter_reg[2]) is unused and will be removed from module lab2_wrapper. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:30 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 150 ; free virtual = 1344 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:43 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 75 ; free virtual = 1216 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:43 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 75 ; free virtual = 1216 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:19 ; elapsed = 00:00:43 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 85 ; free virtual = 1215 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 85 ; free virtual = 1215 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 85 ; free virtual = 1215 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 85 ; free virtual = 1215 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 85 ; free virtual = 1215 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 85 ; free virtual = 1215 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 85 ; free virtual = 1215 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |BUFG | 1| +|2 |LUT2 | 1| +|3 |LUT3 | 3| +|4 |LUT4 | 9| +|5 |LUT5 | 2| +|6 |FDRE | 24| +|7 |FDSE | 1| +|8 |IBUF | 4| +|9 |OBUF | 9| +|10 |OBUFT | 3| ++------+------+------+ + +Report Instance Areas: ++------+---------------------+-------------------+------+ +| |Instance |Module |Cells | ++------+---------------------+-------------------+------+ +|1 |top | | 57| +|2 | mid |midpoint | 40| +|3 | SCLKCond |inputconditioner | 10| +|4 | parallelLoadCond |inputconditioner_0 | 11| +|5 | serialInCond |inputconditioner_1 | 8| +|6 | shift |shiftregister | 11| ++------+---------------------+-------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 85 ; free virtual = 1215 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 15 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:32 . Memory (MB): peak = 1467.379 ; gain = 74.496 ; free physical = 143 ; free virtual = 1274 +Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.387 ; gain = 369.734 ; free physical = 143 ; free virtual = 1274 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +20 Infos, 32 Warnings, 5 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:46 . Memory (MB): peak = 1467.387 ; gain = 382.328 ; free physical = 119 ; free virtual = 1233 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/synth_1/lab2_wrapper.dcp' has been generated. +report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.47 . Memory (MB): peak = 1467.387 ; gain = 0.000 ; free physical = 109 ; free virtual = 1231 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:40:40 2017... diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/lab2_wrapper_utilization_synth.pb b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/lab2_wrapper_utilization_synth.pb new file mode 100644 index 0000000..9a92d8a Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/lab2_wrapper_utilization_synth.pb differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/lab2_wrapper_utilization_synth.rpt b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/lab2_wrapper_utilization_synth.rpt new file mode 100644 index 0000000..ca553c9 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/lab2_wrapper_utilization_synth.rpt @@ -0,0 +1,177 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017 +| Date : Wed Oct 25 21:40:39 2017 +| Host : comparch-VirtualBox running 64-bit Ubuntu 16.04.3 LTS +| Command : report_utilization -file lab2_wrapper_utilization_synth.rpt -pb lab2_wrapper_utilization_synth.pb +| Design : lab2_wrapper +| Device : 7z010clg400-1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 9 | 0 | 17600 | 0.05 | +| LUT as Logic | 9 | 0 | 17600 | 0.05 | +| LUT as Memory | 0 | 0 | 6000 | 0.00 | +| Slice Registers | 25 | 0 | 35200 | 0.07 | +| Register as Flip Flop | 25 | 0 | 35200 | 0.07 | +| Register as Latch | 0 | 0 | 35200 | 0.00 | +| F7 Muxes | 0 | 0 | 8800 | 0.00 | +| F8 Muxes | 0 | 0 | 4400 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 1 | Yes | Set | - | +| 24 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 60 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 60 | 0.00 | +| RAMB18 | 0 | 0 | 120 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 80 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 16 | 0 | 100 | 16.00 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 2 | 0.00 | +| PHASER_REF | 0 | 0 | 2 | 0.00 | +| OUT_FIFO | 0 | 0 | 8 | 0.00 | +| IN_FIFO | 0 | 0 | 8 | 0.00 | +| IDELAYCTRL | 0 | 0 | 2 | 0.00 | +| IBUFDS | 0 | 0 | 96 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 | +| ILOGIC | 0 | 0 | 100 | 0.00 | +| OLOGIC | 0 | 0 | 100 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 8 | 0.00 | +| MMCME2_ADV | 0 | 0 | 2 | 0.00 | +| PLLE2_ADV | 0 | 0 | 2 | 0.00 | +| BUFMRCE | 0 | 0 | 4 | 0.00 | +| BUFHCE | 0 | 0 | 48 | 0.00 | +| BUFR | 0 | 0 | 8 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 24 | Flop & Latch | +| OBUF | 9 | IO | +| LUT4 | 9 | LUT | +| IBUF | 4 | IO | +| OBUFT | 3 | IO | +| LUT3 | 3 | LUT | +| LUT5 | 2 | LUT | +| LUT2 | 1 | LUT | +| FDSE | 1 | Flop & Latch | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/project.wdf b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/project.wdf new file mode 100644 index 0000000..cb5b706 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/project.wdf @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:34:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6266336439383535646166663465616138303238646231613563346564376534:506172656e742050412070726f6a656374204944:00 +eof:2667136787 diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/rundef.js b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/rundef.js new file mode 100644 index 0000000..cc9dd21 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/opt/Xilinx/SDK/2017.2/bin:/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2017.2/bin;"; +} else { + PathVal = "/opt/Xilinx/SDK/2017.2/bin:/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2017.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log lab2_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source lab2_wrapper.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/runme.bat b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/runme.bat new file mode 100644 index 0000000..220ba68 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/runme.log b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/runme.log new file mode 100644 index 0000000..6f4ffd4 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/runme.log @@ -0,0 +1,326 @@ + +*** Running vivado + with args -log lab2_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source lab2_wrapper.tcl + + +****** Vivado v2017.2 (64-bit) + **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 + **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 + ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. + +source lab2_wrapper.tcl -notrace +Command: synth_design -top lab2_wrapper -part xc7z010clg400-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010-clg400' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010-clg400' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 14032 +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module inputconditioner [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/inputconditioner.v:9] +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module shiftregister [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/shiftregister.v:9] +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module inputconditioner [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/inputconditioner.v:9] +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module shiftregister [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/shiftregister.v:9] +CRITICAL WARNING: [Synth 8-2490] overwriting previous definition of module midpoint [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/midpoint.v:7] +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1146.891 ; gain = 49.246 ; free physical = 186 ; free virtual = 1507 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'lab2_wrapper' [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/lab2wrapper.v:23] +INFO: [Synth 8-638] synthesizing module 'midpoint' [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/midpoint.v:7] + Parameter width bound to: 8 - type: integer +INFO: [Synth 8-638] synthesizing module 'inputconditioner' [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/inputconditioner.v:9] + Parameter counterwidth bound to: 3 - type: integer + Parameter waittime bound to: 3 - type: integer +INFO: [Synth 8-256] done synthesizing module 'inputconditioner' (1#1) [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/inputconditioner.v:9] +INFO: [Synth 8-638] synthesizing module 'shiftregister' [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/shiftregister.v:9] + Parameter width bound to: 8 - type: integer +INFO: [Synth 8-256] done synthesizing module 'shiftregister' (2#1) [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/shiftregister.v:9] +INFO: [Synth 8-256] done synthesizing module 'midpoint' (3#1) [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/midpoint.v:7] +WARNING: [Synth 8-3848] Net led in module/entity lab2_wrapper does not have driver. [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/lab2wrapper.v:28] +INFO: [Synth 8-256] done synthesizing module 'lab2_wrapper' (4#1) [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/sources_1/imports/Lab2/lab2wrapper.v:23] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[1] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port sw[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port sw[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[1] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1172.141 ; gain = 74.496 ; free physical = 201 ; free virtual = 1523 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 1172.141 ; gain = 74.496 ; free physical = 201 ; free virtual = 1524 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7z010clg400-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +Finished Parsing XDC File [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/lab2_wrapper_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/lab2_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1467.379 ; gain = 0.000 ; free physical = 93 ; free virtual = 1277 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 170 ; free virtual = 1361 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z010clg400-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 170 ; free virtual = 1361 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:29 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 170 ; free virtual = 1361 +--------------------------------------------------------------------------------- +INFO: [Synth 8-5544] ROM "conditioned" won't be mapped to Block RAM because address size (3) smaller than threshold (5) +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:30 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 161 ; free virtual = 1353 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 3 ++---Registers : + 8 Bit Registers := 1 + 3 Bit Registers := 3 + 1 Bit Registers := 15 ++---Muxes : + 2 Input 8 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 3 + 2 Input 1 Bit Muxes := 15 + 3 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module inputconditioner +Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 1 ++---Registers : + 3 Bit Registers := 1 + 1 Bit Registers := 5 ++---Muxes : + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 +Module shiftregister +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 1 ++---Muxes : + 2 Input 8 Bit Muxes := 1 + 3 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 80 (col length:40) +BRAMs: 120 (col length: RAMB18 40 RAMB36 20) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port led[1] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port sw[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port sw[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[3] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[2] +WARNING: [Synth 8-3331] design lab2_wrapper has unconnected port btn[1] +WARNING: [Synth 8-3332] Sequential element (mid/parallelLoadCond/positiveedge_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/positiveedge_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/negativeedge_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/SCLKCond/negativeedge_reg) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/parallelLoadCond/counter_reg[2]) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/serialInCond/counter_reg[2]) is unused and will be removed from module lab2_wrapper. +WARNING: [Synth 8-3332] Sequential element (mid/SCLKCond/counter_reg[2]) is unused and will be removed from module lab2_wrapper. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:30 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 150 ; free virtual = 1344 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:43 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 75 ; free virtual = 1216 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:43 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 75 ; free virtual = 1216 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:19 ; elapsed = 00:00:43 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 85 ; free virtual = 1215 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:20 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 85 ; free virtual = 1215 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:20 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 85 ; free virtual = 1215 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:20 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 85 ; free virtual = 1215 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:20 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 85 ; free virtual = 1215 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:20 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 85 ; free virtual = 1215 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:20 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 85 ; free virtual = 1215 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |BUFG | 1| +|2 |LUT2 | 1| +|3 |LUT3 | 3| +|4 |LUT4 | 9| +|5 |LUT5 | 2| +|6 |FDRE | 24| +|7 |FDSE | 1| +|8 |IBUF | 4| +|9 |OBUF | 9| +|10 |OBUFT | 3| ++------+------+------+ + +Report Instance Areas: ++------+---------------------+-------------------+------+ +| |Instance |Module |Cells | ++------+---------------------+-------------------+------+ +|1 |top | | 57| +|2 | mid |midpoint | 40| +|3 | SCLKCond |inputconditioner | 10| +|4 | parallelLoadCond |inputconditioner_0 | 11| +|5 | serialInCond |inputconditioner_1 | 8| +|6 | shift |shiftregister | 11| ++------+---------------------+-------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:20 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.379 ; gain = 369.734 ; free physical = 85 ; free virtual = 1215 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 15 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:32 . Memory (MB): peak = 1467.379 ; gain = 74.496 ; free physical = 143 ; free virtual = 1274 +Synthesis Optimization Complete : Time (s): cpu = 00:00:20 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.387 ; gain = 369.734 ; free physical = 143 ; free virtual = 1274 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +20 Infos, 32 Warnings, 5 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:46 . Memory (MB): peak = 1467.387 ; gain = 382.328 ; free physical = 119 ; free virtual = 1233 +INFO: [Common 17-1381] The checkpoint '/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/synth_1/lab2_wrapper.dcp' has been generated. +report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.47 . Memory (MB): peak = 1467.387 ; gain = 0.000 ; free physical = 109 ; free virtual = 1231 +INFO: [Common 17-206] Exiting Vivado at Wed Oct 25 21:40:40 2017... diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/runme.sh b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/runme.sh new file mode 100755 index 0000000..9329c9e --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/opt/Xilinx/SDK/2017.2/bin:/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2017.2/bin +else + PATH=/opt/Xilinx/SDK/2017.2/bin:/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2017.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64 +else + LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2017.2/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log lab2_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source lab2_wrapper.tcl diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/vivado.jou b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/vivado.jou new file mode 100644 index 0000000..8d4b74e --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2017.2 (64-bit) +# SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 +# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 +# Start of session at: Wed Oct 25 21:39:31 2017 +# Process ID: 13818 +# Current directory: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/synth_1 +# Command line: vivado -log lab2_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source lab2_wrapper.tcl +# Log file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/synth_1/lab2_wrapper.vds +# Journal file: /home/comparch/Desktop/LoganLab2/Lab2/project_2_freshstart/project_2_freshstart.runs/synth_1/vivado.jou +#----------------------------------------------------------- +source lab2_wrapper.tcl -notrace diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/vivado.pb b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/vivado.pb new file mode 100644 index 0000000..583f432 Binary files /dev/null and b/Lab2Vivado_FreshStart/project_2_freshstart.runs/synth_1/vivado.pb differ diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc b/Lab2Vivado_FreshStart/project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc new file mode 100644 index 0000000..a20dc59 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.srcs/constrs_1/imports/Desktop/ZYBO_Master.xdc @@ -0,0 +1,146 @@ +## This file is a general .xdc for the ZYBO Rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used signals according to the project + + +##Clock signal +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L11P_T1_SRCC_35 Sch=sysclk +#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }]; + + +##Switches +set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=SW0 +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=SW1 +set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=SW2 +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=SW3 + + +##Buttons +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L20N_T3_34 Sch=BTN0 +set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=BTN1 +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L18P_T2_34 Sch=BTN2 +set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=BTN3 + + +##LEDs +set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=LED0 +set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=LED1 +set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35=Sch=LED2 +set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3 + + +##I2S Audio Codec +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports ac_bclk]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK +#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports ac_mclk]; #IO_25_34 Sch=AC_MCLK +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports ac_muten]; #IO_L23N_T3_34 Sch=AC_MUTEN +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports ac_pbdat]; #IO_L8P_T1_AD10P_35 Sch=AC_PBDAT +#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports ac_pblrc]; #IO_L11N_T1_SRCC_35 Sch=AC_PBLRC +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports ac_recdat]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports ac_reclrc]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC + + +##Audio Codec/external EEPROM IIC bus +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports ac_scl]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports ac_sda]; #IO_L23P_T3_34 Sch=AC_SDA + + +##Additional Ethernet signals +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports eth_int_b]; #IO_L6P_T0_35 Sch=ETH_INT_B +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports eth_rst_b]; #IO_L3P_T0_DQS_AD1P_35 Sch=ETH_RST_B + + +##HDMI Signals +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_n]; #IO_L13N_T2_MRCC_35 Sch=HDMI_CLK_N +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_p]; #IO_L13P_T2_MRCC_35 Sch=HDMI_CLK_P +#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[0] }]; #IO_L4N_T0_35 Sch=HDMI_D0_N +#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[0] }]; #IO_L4P_T0_35 Sch=HDMI_D0_P +#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=HDMI_D1_N +#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=HDMI_D1_P +#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=HDMI_D2_N +#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=HDMI_D2_P +#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports hdmi_cec]; #IO_L5N_T0_AD9N_35 Sch=HDMI_CEC +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports hdmi_hpd]; #IO_L5P_T0_AD9P_35 Sch=HDMI_HPD +#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports hdmi_out_en]; #IO_L6N_T0_VREF_35 Sch=HDMI_OUT_EN +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports hdmi_scl]; #IO_L16P_T2_35 Sch=HDMI_SCL +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports hdmi_sda]; #IO_L16N_T2_35 Sch=HDMI_SDA + + +##Pmod Header JA (XADC) +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja_p[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P +#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[0] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N +#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N +#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N + + +##Pmod Header JB +#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[0] }]; #IO_L15P_T2_DQS_34 Sch=JB1_p +#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[0] }]; #IO_L15N_T2_DQS_34 Sch=JB1_N +#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L16P_T2_34 Sch=JB2_P +#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L16N_T2_34 Sch=JB2_N +#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L17P_T2_34 Sch=JB3_P +#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L17N_T2_34 Sch=JB3_N +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L22P_T3_34 Sch=JB4_P +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L22N_T3_34 Sch=JB4_N + + +##Pmod Header JC +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc_p[0] }]; #IO_L10P_T1_34 Sch=JC1_P +#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc_n[0] }]; #IO_L10N_T1_34 Sch=JC1_N +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc_p[1] }]; #IO_L1P_T0_34 Sch=JC2_P +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc_n[1] }]; #IO_L1N_T0_34 Sch=JC2_N +#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc_p[2] }]; #IO_L8P_T1_34 Sch=JC3_P +#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc_n[2] }]; #IO_L8N_T1_34 Sch=JC3_N +#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc_p[3] }]; #IO_L2P_T0_34 Sch=JC4_P +#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc_n[3] }]; #IO_L2N_T0_34 Sch=JC4_N + + +##Pmod Header JD +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[0] }]; #IO_L5P_T0_34 Sch=JD1_P +#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[0] }]; #IO_L5N_T0_34 Sch=JD1_N +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[1] }]; #IO_L6P_T0_34 Sch=JD2_P +#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd_n[1] }]; #IO_L6N_T0_VREF_34 Sch=JD2_N +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[2] }]; #IO_L11P_T1_SRCC_34 Sch=JD3_P +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[2] }]; #IO_L11N_T1_SRCC_34 Sch=JD3_N +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd_p[3] }]; #IO_L21P_T3_DQS_34 Sch=JD4_P +#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd_n[3] }]; #IO_L21N_T3_DQS_34 Sch=JD4_N + + +##Pmod Header JE +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=JE1 +set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=JE2 +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=JE3 +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=JE4 +set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=JE7 +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=JE8 +set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=JE9 +set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=JE10 + + +##USB-OTG overcurrent detect pin +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports otg_oc]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=OTG_OC + + +##VGA Connector +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L7P_T1_AD2P_35 Sch=VGA_R1 +#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=VGA_R2 +#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L17P_T2_AD5P_35 Sch=VGA_R3 +#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L18N_T2_AD13N_35 Sch=VGA_R4 +#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_AD12P_35 Sch=VGA_R5 +#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=VGA_G0 +#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L14P_T2_SRCC_34 Sch=VGA_G1 +#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=VGA_G2 +#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L10N_T1_AD11N_35 Sch=VGA_G3 +#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L17N_T2_AD5N_35 Sch=VGA_G4 +#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L15N_T2_DQS_AD12N_35 Sch=VGA=G5 +#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L14N_T2_SRCC_34 Sch=VGA_B1 +#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L7N_T1_AD2N_35 Sch=VGA_B2 +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L10P_T1_AD11P_35 Sch=VGA_B3 +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=VGA_B4 +#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L18P_T2_AD13P_35 Sch=VGA_B5 +#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports vga_hs]; #IO_L13N_T2_MRCC_34 Sch=VGA_HS +#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports vga_vs]; #IO_0_34 Sch=VGA_VS diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.srcs/sources_1/imports/Lab2/inputconditioner.v b/Lab2Vivado_FreshStart/project_2_freshstart.srcs/sources_1/imports/Lab2/inputconditioner.v new file mode 100644 index 0000000..7940cce --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.srcs/sources_1/imports/Lab2/inputconditioner.v @@ -0,0 +1,52 @@ +//------------------------------------------------------------------------ +// Input Conditioner +// 1) Synchronizes input to clock domain +// 2) Debounces input +// 3) Creates pulses at edge transitions +//------------------------------------------------------------------------ +// 50 MHz is 2 * 1-^-8 seconds per cycle + +module inputconditioner +( +input clk, // Clock domain to synchronize input to +input noisysignal, // (Potentially) noisy input signal +output reg conditioned, // Conditioned output signal +output reg positiveedge, // 1 clk pulse at rising edge of conditioned +output reg negativeedge // 1 clk pulse at falling edge of conditioned +); + + parameter counterwidth = 3; // Counter size, in bits, >= log2(waittime) (maybe this could be 2 since 2^2 > 3) + parameter waittime = 3; // Debounce delay, in clock cycles + + reg[counterwidth-1:0] counter = 0; + reg synchronizer0 = 0; + reg synchronizer1 = 0; // you need 2 synchronizers so you can calculate + and - edge + +always @(posedge clk ) begin + +if(conditioned == synchronizer1) + counter <= 0; +else begin + if(counter == waittime) begin + counter <= 0; + conditioned <= synchronizer1; + if(conditioned == 0 & synchronizer1 ==1) + positiveedge <= 1; + if(conditioned == 1 & synchronizer1 ==0) + negativeedge <= 1; + end + else + counter <= counter+1; +end // end to the else begin statement + +if(positiveedge == 1) + positiveedge <= 0; +if(negativeedge == 1) + negativeedge <= 0; + +synchronizer0 <= noisysignal; // these happen every time there's a clk edge +synchronizer1 <= synchronizer0; +end + +endmodule + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.srcs/sources_1/imports/Lab2/lab2wrapper.v b/Lab2Vivado_FreshStart/project_2_freshstart.srcs/sources_1/imports/Lab2/lab2wrapper.v new file mode 100644 index 0000000..0a5b4c3 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.srcs/sources_1/imports/Lab2/lab2wrapper.v @@ -0,0 +1,49 @@ +//-------------------------------------------------------------------------------- +// Wrapper for Lab 0: Full Adder +// +// Rationale: +// The ZYBO board has 4 buttons, 4 switches, and 4 LEDs. +// +// This wrapper module allows for one bit to be loaded in at a time and to then show all data at once +// +// +// Usage: +// btn0 - Parallel Load +// sw0 - SerialIn +// sw1 - SCLCK +// +// Note: Buttons, switches, and LEDs have the least-significant (0) position +// on the right. +//-------------------------------------------------------------------------------- + +`timescale 1ns / 1ps +`include "midpoint.v" + + +module lab2_wrapper +( + input clk, + input [3:0] sw, // Built-in switches, used for input opA + input [3:0] btn, + output [3:0] led, // Built-in LED, used to display opA for sanity checking + output [7:0] je // Plug LD8 into JE, used to display sum, cout, overflow +); + + wire [7:0] parallelDataIn; + wire serialOut; + wire[7:0] res; + assign parallelDataIn = 8'b10010011; + assign je[7:0] = res; + assign serialOut = led[0]; + + midpoint mid(.switch0(sw[0]), .switch1(sw[1]), .button(btn[0]), .clk(clk), .parallelDataIn(parallelDataIn), .parallelDataOut2(res), .serialDataOut(serialOut)); + +endmodule + + + + + + + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.srcs/sources_1/imports/Lab2/midpoint.v b/Lab2Vivado_FreshStart/project_2_freshstart.srcs/sources_1/imports/Lab2/midpoint.v new file mode 100644 index 0000000..af182ec --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.srcs/sources_1/imports/Lab2/midpoint.v @@ -0,0 +1,43 @@ +// Midpoint deliverable file + +`include "inputconditioner.v" +`include "shiftregister.v" + + +module midpoint +#(parameter width = 8) +( +input switch0, // SerialDataIn +input switch1, // peripheralClkEdge +input button, // ParallelLoad +input clk, +input [width-1:0] parallelDataIn, +output [width-1:0] parallelDataOut2, +output wire serialDataOut +); + +wire conditioned0; +wire positiveedge0; +wire negativeedge0; + +wire conditioned1; +wire positiveedge1; +wire negativeedge1; + +wire conditioned2; +wire positiveedge2; +wire negativeedge2; + + + +inputconditioner parallelLoadCond(clk, button, conditioned0, positiveedge0, negativeedge0); // negativeedge0 is your cleaned up button/ParallelLoad + +inputconditioner serialInCond(clk, switch0, conditioned1, positiveedge1, negativeedge1); // conditioned1 is your cleaned up SerialDataIn + +inputconditioner SCLKCond(clk, switch1, conditioned2, positiveedge2, negativeedge2); // positiveedge2 is your cleaned up peripheralClkEdge + +shiftregister shift(clk, positiveedge2, negativeedge0, parallelDataIn, conditioned1, parallelDataOut2, serialDataOut); + +endmodule + + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.srcs/sources_1/imports/Lab2/shiftregister.v b/Lab2Vivado_FreshStart/project_2_freshstart.srcs/sources_1/imports/Lab2/shiftregister.v new file mode 100644 index 0000000..bc72137 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.srcs/sources_1/imports/Lab2/shiftregister.v @@ -0,0 +1,44 @@ +//------------------------------------------------------------------------ +// Shift Register +// Parameterized width (in bits) +// Shift register can operate in two modes: +// - serial in, parallel out +// - parallel in, serial out +//------------------------------------------------------------------------ + +module shiftregister +#(parameter width = 8) +( +input clk, // FPGA Clock +input peripheralClkEdge, // Edge indicator +input parallelLoad, // 1 = Load shift reg with parallelDataIn +input [width-1:0] parallelDataIn, // Load shift reg in parallel +input serialDataIn, // Load shift reg serially +output wire [width-1:0] parallelDataOut, // Shift reg data contents +output wire serialDataOut // Positive edge synchronized +); + +reg [width-1:0] shiftregistermem; +assign parallelDataOut = shiftregistermem; +assign serialDataOut = shiftregistermem[width-1]; + +always @(posedge clk) begin + + if(parallelLoad ==1) begin // do thisfor parallel data in + + shiftregistermem <= parallelDataIn; + + end + + else if(parallelLoad ==0) begin // We are deciding that parallelLoad will win. This takes priority over serial shift - peripheralClkEdge only matters if parallelLoad = 0. + if (peripheralClkEdge == 1) begin + shiftregistermem <= {shiftregistermem[width-2:0], serialDataIn}; + + + end + end + +end + +endmodule + diff --git a/Lab2Vivado_FreshStart/project_2_freshstart.xpr b/Lab2Vivado_FreshStart/project_2_freshstart.xpr new file mode 100644 index 0000000..0e8c3d2 --- /dev/null +++ b/Lab2Vivado_FreshStart/project_2_freshstart.xpr @@ -0,0 +1,176 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + diff --git a/Maggie and Logan Work Plan b/Maggie and Logan Work Plan new file mode 100644 index 0000000..061d559 --- /dev/null +++ b/Maggie and Logan Work Plan @@ -0,0 +1,21 @@ +CompArch Lab 2 Work Plan +Logan and Maggie +10/20/17 + +Understand what SPI memory is. Time: 1 hours. Due:10/22 +Create input conditioner. Time: 1 hour. Due: End of day, 10/22 +Write test bench for input conditioner. Time: 1 hour. Due: End of day, 10/23 +Create shift register. Time: 3 hours. Due: 9 pm, 10/24 +Write test bench for input conditioner. Time: 2 hours. Due: 10 pm, 10/24 +Load input conditioner & shift register onto FPGA. Time: 2 hours. Due: End of day, October 24 +Write complete test bench for what we have so far Time: 1 hours Due: End of day, October 25 +Midpoint Deliverable writeup Time: 2 hours Due: End of day October 25 +Read about FSM & Maggie double checks her understanding of things. Time: 1 hour. Due: 10/24 +Create drawing of FSM Time: 0.5 hours Due: End of day October 24 +Check FSM with an instructor Time: 0.5 hours Due: End of day October 24 +Code FSM Time: 2 hours Due: End of day October 25 +Finish SPI module Time: 5 hours Due: End of day October 28 +Write and evaluate testbench Time: 3 hours Due: End of day October 30 +Write report Time: 2 hours Due: End of day November 1 + +Total time: 27 hours diff --git a/SPI.vcd b/SPI.vcd new file mode 100644 index 0000000..83f0239 --- /dev/null +++ b/SPI.vcd @@ -0,0 +1,7004 @@ +$date + Tue Oct 31 19:25:04 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1ps +$end +$scope module spitest $end +$var wire 4 ! leds [3:0] $end +$var wire 1 " miso_pin $end +$var reg 1 # clk $end +$var reg 1 $ cs_pin $end +$var reg 1 % mosi_pin $end +$var reg 1 & sclk_pin $end +$scope module spitime $end +$var wire 1 ' ADDR_WE $end +$var wire 1 ( ChipSel $end +$var wire 1 ) DM_WE $end +$var wire 1 * MISO $end +$var wire 1 + MISO_BUFE $end +$var wire 1 , MISO_PreBuff $end +$var wire 1 - MOSI $end +$var wire 1 . SCLKEdge $end +$var wire 1 / SR_WE $end +$var wire 7 0 address [6:0] $end +$var wire 1 1 clk $end +$var wire 1 2 conditioned1 $end +$var wire 1 3 cs_pin $end +$var wire 8 4 dataMemOut [7:0] $end +$var wire 4 5 leds [3:0] $end +$var wire 1 " miso_pin $end +$var wire 1 6 mosi_pin $end +$var wire 1 7 negativeedge0 $end +$var wire 1 8 negativeedge1 $end +$var wire 1 9 negativeedge2 $end +$var wire 1 : positiveedge0 $end +$var wire 1 ; positiveedge2 $end +$var wire 1 < sclk_pin $end +$var wire 8 = shiftRegOutP [7:0] $end +$scope module serialInCond $end +$var wire 1 1 clk $end +$var wire 1 6 noisysignal $end +$var reg 1 > conditioned $end +$var reg 3 ? counter [2:0] $end +$var reg 1 @ negativeedge $end +$var reg 1 A positiveedge $end +$var reg 1 B synchronizer0 $end +$var reg 1 C synchronizer1 $end +$upscope $end +$scope module SCLKCond $end +$var wire 1 1 clk $end +$var wire 1 < noisysignal $end +$var reg 1 D conditioned $end +$var reg 3 E counter [2:0] $end +$var reg 1 F negativeedge $end +$var reg 1 G positiveedge $end +$var reg 1 H synchronizer0 $end +$var reg 1 I synchronizer1 $end +$upscope $end +$scope module ChipSelCond $end +$var wire 1 1 clk $end +$var wire 1 3 noisysignal $end +$var reg 1 J conditioned $end +$var reg 3 K counter [2:0] $end +$var reg 1 L negativeedge $end +$var reg 1 M positiveedge $end +$var reg 1 N synchronizer0 $end +$var reg 1 O synchronizer1 $end +$upscope $end +$scope module SPIShift $end +$var wire 1 1 clk $end +$var wire 8 P parallelDataIn [7:0] $end +$var wire 8 Q parallelDataOut [7:0] $end +$var wire 1 / parallelLoad $end +$var wire 1 . peripheralClkEdge $end +$var wire 1 - serialDataIn $end +$var wire 1 * serialDataOut $end +$var reg 8 R shiftregistermem [7:0] $end +$upscope $end +$scope module DFFAddr $end +$var wire 7 S d [6:0] $end +$var wire 1 ' enable $end +$var wire 1 1 trigger $end +$var reg 7 T q [6:0] $end +$upscope $end +$scope module SPIFSM $end +$var wire 1 ( ChipSelCond $end +$var wire 1 . SCLKEdge $end +$var wire 1 1 clk $end +$var wire 1 U shiftRegOutPZero $end +$var reg 1 V ADDR_WE $end +$var reg 1 W DM_WE $end +$var reg 1 X MISO_BUFE $end +$var reg 1 Y SR_WE $end +$var reg 1 Z WriteController $end +$var reg 5 [ counter [4:0] $end +$upscope $end +$scope module DFFMISO $end +$var wire 1 * d $end +$var wire 1 8 enable $end +$var wire 1 1 trigger $end +$var reg 1 \ q $end +$upscope $end +$scope module data $end +$var wire 7 ] address [6:0] $end +$var wire 1 1 clk $end +$var wire 8 ^ dataIn [7:0] $end +$var wire 1 ) writeEnable $end +$var reg 8 _ dataOut [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +bx _ +bx ^ +bx ] +x\ +b0 [ +xZ +xY +xX +xW +xV +xU +bx T +bx S +bx R +bx Q +bx P +0O +0N +xM +xL +b0 K +xJ +0I +0H +xG +xF +b0 E +xD +0C +0B +xA +x@ +b0 ? +x> +bx = +1< +x; +x: +x9 +x8 +x7 +06 +bz 5 +bx 4 +13 +x2 +01 +bx 0 +x/ +x. +x- +x, +x+ +x* +x) +x( +x' +1& +0% +1$ +0# +x" +bz ! +$end +#10000 +b1 ? +1H +b1 E +1N +b1 K +1# +11 +#20000 +0# +01 +#30000 +1O +b10 K +1I +b10 E +b10 ? +1# +11 +#40000 +0# +01 +#50000 +b11 ? +b11 E +b11 K +1# +11 +#60000 +0# +01 +#70000 +1J +1( +b0 K +1D +12 +b0 E +0> +0- +b0 ? +1# +11 +#80000 +0# +01 +#90000 +1# +11 +#100000 +0# +01 +#110000 +1# +11 +#120000 +0# +01 +#130000 +1# +11 +#140000 +0# +01 +#150000 +1# +11 +#160000 +0# +01 +#170000 +1# +11 +#180000 +0# +01 +#190000 +1# +11 +#200000 +0# +01 +0& +0< +0$ +03 +#210000 +0H +0N +1# +11 +#220000 +0# +01 +#230000 +0O +0I +1# +11 +#240000 +0# +01 +#250000 +b1 E +b1 K +1# +11 +#260000 +0# +01 +#270000 +b10 K +b10 E +1# +11 +#280000 +0# +01 +#290000 +b11 E +b11 K +1# +11 +#300000 +0# +01 +#310000 +1L +19 +0J +0( +b0 K +1F +18 +0D +02 +b0 E +1# +11 +#320000 +0# +01 +#330000 +0F +08 +0L +09 +1# +11 +#340000 +0# +01 +#350000 +1# +11 +#360000 +0# +01 +#370000 +1# +11 +#380000 +0# +01 +1& +1< +1$ +13 +#390000 +1N +1H +1# +11 +#400000 +0# +01 +#410000 +1I +1O +1# +11 +#420000 +0# +01 +#430000 +b1 K +b1 E +1# +11 +#440000 +0# +01 +#450000 +b10 E +b10 K +1# +11 +#460000 +0# +01 +#470000 +b11 K +b11 E +1# +11 +#480000 +0# +01 +#490000 +1G +1. +1D +12 +b0 E +1M +1; +1J +1( +b0 K +1# +11 +#500000 +0# +01 +#510000 +0X +0+ +z" +0Y +0/ +0V +0' +0W +0) +0Z +0M +0; +0G +0. +1# +11 +#520000 +0# +01 +#530000 +1# +11 +#540000 +0# +01 +#550000 +1# +11 +#560000 +0# +01 +#570000 +1# +11 +#580000 +0# +01 +1% +16 +0& +0< +#590000 +0H +1B +1# +11 +#600000 +0# +01 +#610000 +1C +0I +1# +11 +#620000 +0# +01 +#628000 +1& +1< +#630000 +1H +b1 E +b1 ? +1# +11 +#640000 +0# +01 +#650000 +b10 ? +1I +b10 E +1# +11 +#660000 +0# +01 +#670000 +b0 E +b11 ? +1# +11 +#676000 +0% +06 +0& +0< +#680000 +0# +01 +#690000 +0B +1A +1: +1> +1- +b0 ? +0H +1# +11 +#700000 +0# +01 +#710000 +0I +0C +0A +0: +1# +11 +#720000 +0# +01 +#724000 +1& +1< +#730000 +b1 ? +1H +b1 E +1# +11 +#740000 +0# +01 +#750000 +1I +b10 E +b10 ? +1# +11 +#760000 +0# +01 +#770000 +b11 ? +b0 E +1# +11 +#772000 +0& +0< +#780000 +0# +01 +#790000 +0H +1@ +17 +0> +0- +b0 ? +1# +11 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a/finite b/finite new file mode 100755 index 0000000..e560aef --- /dev/null +++ b/finite @@ -0,0 +1,1439 @@ +#! /usr/bin/vvp +:ivl_version "0.9.7 " "(v0_9_7)"; +:vpi_time_precision - 12; +:vpi_module "system"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x1dd6760 .scope module, "spitest" "spitest" 2 3; + .timescale -9 -12; +v0x1e83220_0 .var "clk", 0 0; +v0x1e832a0_0 .var "cs_pin", 0 0; +v0x1e83320_0 .net "leds", 3 0, C4; 0 drivers +v0x1e833a0_0 .net8 "miso_pin", 0 0, L_0x1e83880; 1 drivers, strength-aware +v0x1e83420_0 .var "mosi_pin", 0 0; +v0x1e834f0_0 .var "sclk_pin", 0 0; +S_0x1dd3f60 .scope module, "spitime" "spiMemory" 2 12, 3 9, S_0x1dd6760; + .timescale -9 -12; +P_0x1de94c8 .param/l "size" 3 18, +C4<01000>; +L_0x1e83880 .functor BUFIF1 1, v0x1e7f580_0, v0x1e7fab0_0, C4<0>, C4<0>; +v0x1e81fe0_0 .net "ADDR_WE", 0 0, v0x1e7f8c0_0; 1 drivers +v0x1e820d0_0 .net "ChipSel", 0 0, v0x1e80d20_0; 1 drivers +v0x1e821a0_0 .net "DM_WE", 0 0, v0x1e7fa00_0; 1 drivers +v0x1e82270_0 .net "MISO", 0 0, L_0x1e835c0; 1 drivers +v0x1e82340_0 .net "MISO_BUFE", 0 0, v0x1e7fab0_0; 1 drivers +v0x1e823c0_0 .net "MISO_PreBuff", 0 0, v0x1e7f580_0; 1 drivers +v0x1e82440_0 .net "MOSI", 0 0, v0x1e81b50_0; 1 drivers +v0x1e82510_0 .net "SCLKEdge", 0 0, v0x1e81660_0; 1 drivers +v0x1e825e0_0 .net "SR_WE", 0 0, v0x1e7fbe0_0; 1 drivers +v0x1e826b0_0 .net "address", 6 0, v0x1e802b0_0; 1 drivers +v0x1e82790_0 .net "clk", 0 0, v0x1e83220_0; 1 drivers +v0x1e805d0_0 .net "conditioned1", 0 0, v0x1e813f0_0; 1 drivers +v0x1e82990_0 .net "cs_pin", 0 0, v0x1e832a0_0; 1 drivers +v0x1e82a10_0 .net "dataMemOut", 7 0, v0x1e7f080_0; 1 drivers +v0x1e82b60_0 .alias "leds", 3 0, v0x1e83320_0; +v0x1e82be0_0 .alias "miso_pin", 0 0, v0x1e833a0_0; +v0x1e82a90_0 .net "mosi_pin", 0 0, v0x1e83420_0; 1 drivers +v0x1e82cf0_0 .net "negativeedge0", 0 0, v0x1e81c50_0; 1 drivers +v0x1e82c60_0 .net "negativeedge1", 0 0, v0x1e81530_0; 1 drivers +v0x1e82e60_0 .net "negativeedge2", 0 0, v0x1e80e50_0; 1 drivers +v0x1e82d70_0 .net "positiveedge0", 0 0, v0x1e81d70_0; 1 drivers +v0x1e82f90_0 .net "positiveedge2", 0 0, v0x1e80f80_0; 1 drivers +v0x1e82ee0_0 .net "sclk_pin", 0 0, v0x1e834f0_0; 1 drivers +v0x1e830d0_0 .net "shiftRegOutP", 7 0, L_0x1e82730; 1 drivers +L_0x1e836b0 .part L_0x1e82730, 1, 7; +L_0x1e837e0 .part L_0x1e82730, 0, 1; +S_0x1e818e0 .scope module, "serialInCond" "inputconditioner" 3 49, 4 9, S_0x1dd3f60; + .timescale -9 -12; +P_0x1e819d8 .param/l "counterwidth" 4 18, +C4<011>; +P_0x1e81a00 .param/l "waittime" 4 19, +C4<011>; +v0x1e81ad0_0 .alias "clk", 0 0, v0x1e82790_0; +v0x1e81b50_0 .var "conditioned", 0 0; +v0x1e81bd0_0 .var "counter", 2 0; +v0x1e81c50_0 .var "negativeedge", 0 0; +v0x1e81cd0_0 .alias "noisysignal", 0 0, v0x1e82a90_0; +v0x1e81d70_0 .var "positiveedge", 0 0; +v0x1e81e50_0 .var "synchronizer0", 0 0; +v0x1e81ef0_0 .var "synchronizer1", 0 0; +S_0x1e81180 .scope module, "SCLKCond" "inputconditioner" 3 51, 4 9, S_0x1dd3f60; + .timescale -9 -12; +P_0x1e81278 .param/l "counterwidth" 4 18, +C4<011>; +P_0x1e812a0 .param/l "waittime" 4 19, +C4<011>; +v0x1e81370_0 .alias "clk", 0 0, v0x1e82790_0; +v0x1e813f0_0 .var "conditioned", 0 0; +v0x1e81490_0 .var "counter", 2 0; +v0x1e81530_0 .var "negativeedge", 0 0; +v0x1e815e0_0 .alias "noisysignal", 0 0, v0x1e82ee0_0; +v0x1e81660_0 .var "positiveedge", 0 0; +v0x1e81770_0 .var "synchronizer0", 0 0; +v0x1e817f0_0 .var "synchronizer1", 0 0; +S_0x1e80b10 .scope module, "ChipSelCond" "inputconditioner" 3 53, 4 9, S_0x1dd3f60; + .timescale -9 -12; +P_0x1e80c08 .param/l "counterwidth" 4 18, +C4<011>; +P_0x1e80c30 .param/l "waittime" 4 19, +C4<011>; +v0x1e80ca0_0 .alias "clk", 0 0, v0x1e82790_0; +v0x1e80d20_0 .var "conditioned", 0 0; +v0x1e80dd0_0 .var "counter", 2 0; +v0x1e80e50_0 .var "negativeedge", 0 0; +v0x1e80f00_0 .alias "noisysignal", 0 0, v0x1e82990_0; +v0x1e80f80_0 .var "positiveedge", 0 0; +v0x1e81040_0 .var "synchronizer0", 0 0; +v0x1e810e0_0 .var "synchronizer1", 0 0; +S_0x1e803e0 .scope module, "SPIShift" "shiftregister" 3 55, 5 9, S_0x1dd3f60; + .timescale -9 -12; +P_0x1e804d8 .param/l "width" 5 10, +C4<01000>; +L_0x1e82730 .functor BUFZ 8, v0x1e80a90_0, C4<00000000>, C4<00000000>, C4<00000000>; +v0x1e80550_0 .alias "clk", 0 0, v0x1e82790_0; +v0x1e80660_0 .alias "parallelDataIn", 7 0, v0x1e82a10_0; +v0x1e80710_0 .alias "parallelDataOut", 7 0, v0x1e830d0_0; +v0x1e807c0_0 .alias "parallelLoad", 0 0, v0x1e825e0_0; +v0x1e808a0_0 .alias "peripheralClkEdge", 0 0, v0x1e82510_0; +v0x1e80950_0 .alias "serialDataIn", 0 0, v0x1e82440_0; +v0x1e80a10_0 .alias "serialDataOut", 0 0, v0x1e82270_0; +v0x1e80a90_0 .var "shiftregistermem", 7 0; +L_0x1e835c0 .part v0x1e80a90_0, 7, 1; +S_0x1e80020 .scope module, "DFFAddr" "dffADDR" 3 57, 3 84, S_0x1dd3f60; + .timescale -9 -12; +P_0x1e7fc68 .param/l "W" 3 84, +C4<0111>; +v0x1e80190_0 .net "d", 6 0, L_0x1e836b0; 1 drivers +v0x1e80230_0 .alias "enable", 0 0, v0x1e81fe0_0; +v0x1e802b0_0 .var "q", 6 0; +v0x1e80330_0 .alias "trigger", 0 0, v0x1e82790_0; +S_0x1e7f6d0 .scope module, "SPIFSM" "FSM" 3 59, 6 8, S_0x1dd3f60; + .timescale -9 -12; +P_0x1e7f7c8 .param/l "counterwidth" 6 23, +C4<0101>; +P_0x1e7f7f0 .param/l "width" 6 22, +C4<01000>; +v0x1e7f8c0_0 .var "ADDR_WE", 0 0; +v0x1e7f960_0 .alias "ChipSelCond", 0 0, v0x1e820d0_0; +v0x1e7fa00_0 .var "DM_WE", 0 0; +v0x1e7fab0_0 .var "MISO_BUFE", 0 0; +v0x1e7fb60_0 .alias "SCLKEdge", 0 0, v0x1e82510_0; +v0x1e7fbe0_0 .var "SR_WE", 0 0; +v0x1e7fcc0_0 .var "WriteController", 0 0; +v0x1e7fd60_0 .alias "clk", 0 0, v0x1e82790_0; +v0x1e7fe80_0 .var "counter", 4 0; +v0x1e7ff20_0 .net "shiftRegOutPZero", 0 0, L_0x1e837e0; 1 drivers +S_0x1e7f290 .scope module, "DFFMISO" "dff" 3 61, 3 70, S_0x1dd3f60; + .timescale -9 -12; +P_0x1e7f388 .param/l "W" 3 70, +C4<01>; +v0x1e7f440_0 .alias "d", 0 0, v0x1e82270_0; +v0x1e7f4e0_0 .alias "enable", 0 0, v0x1e82c60_0; +v0x1e7f580_0 .var "q", 0 0; +v0x1e7f620_0 .alias "trigger", 0 0, v0x1e82790_0; +S_0x1dd2c90 .scope module, "data" "datamemory" 3 63, 7 8, S_0x1dd3f60; + .timescale -9 -12; +P_0x1de01d8 .param/l "addresswidth" 7 10, +C4<0111>; +P_0x1de0200 .param/l "depth" 7 11, +C4<010000000>; +P_0x1de0228 .param/l "width" 7 12, +C4<01000>; +v0x1de6ac0_0 .alias "address", 6 0, v0x1e826b0_0; +v0x1e7ef40_0 .alias "clk", 0 0, v0x1e82790_0; +v0x1e7efe0_0 .alias "dataIn", 7 0, v0x1e830d0_0; +v0x1e7f080_0 .var "dataOut", 7 0; +v0x1e7f130 .array "memory", 0 127, 7 0; +v0x1e7f1b0_0 .alias "writeEnable", 0 0, v0x1e821a0_0; +E_0x1dcea60 .event posedge, v0x1e7ef40_0; + .scope S_0x1e818e0; +T_0 ; + %set/v v0x1e81bd0_0, 0, 3; + %end; + .thread T_0; + .scope S_0x1e818e0; +T_1 ; + %set/v v0x1e81e50_0, 0, 1; + %end; + .thread T_1; + .scope S_0x1e818e0; +T_2 ; + %set/v v0x1e81ef0_0, 0, 1; + %end; + .thread T_2; + .scope S_0x1e818e0; +T_3 ; + %wait E_0x1dcea60; + %load/v 8, v0x1e81b50_0, 1; + %load/v 9, v0x1e81ef0_0, 1; + %cmp/u 8, 9, 1; + %jmp/0xz T_3.0, 4; + %ix/load 0, 3, 0; + %assign/v0 v0x1e81bd0_0, 0, 0; + %jmp T_3.1; +T_3.0 ; + %load/v 8, v0x1e81bd0_0, 3; + %mov 11, 0, 1; + %cmpi/u 8, 3, 4; + %jmp/0xz T_3.2, 4; + %ix/load 0, 3, 0; + %assign/v0 v0x1e81bd0_0, 0, 0; + %load/v 8, v0x1e81ef0_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1e81b50_0, 0, 8; + %load/v 8, v0x1e81b50_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %mov 8, 4, 1; + %load/v 9, v0x1e81ef0_0, 1; + %mov 10, 0, 2; + %cmpi/u 9, 1, 3; + %mov 9, 4, 1; + %and 8, 9, 1; + %jmp/0xz T_3.4, 8; + %ix/load 0, 1, 0; + %assign/v0 v0x1e81d70_0, 0, 1; +T_3.4 ; + %load/v 8, v0x1e81b50_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %mov 8, 4, 1; + %load/v 9, v0x1e81ef0_0, 1; + %mov 10, 0, 1; + %cmpi/u 9, 0, 2; + %mov 9, 4, 1; + %and 8, 9, 1; + %jmp/0xz T_3.6, 8; + %ix/load 0, 1, 0; + %assign/v0 v0x1e81c50_0, 0, 1; +T_3.6 ; + %jmp T_3.3; +T_3.2 ; + %load/v 8, v0x1e81bd0_0, 3; + %mov 11, 0, 29; + %addi 8, 1, 32; + %ix/load 0, 3, 0; + %assign/v0 v0x1e81bd0_0, 0, 8; +T_3.3 ; +T_3.1 ; + %load/v 8, v0x1e81d70_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_3.8, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1e81d70_0, 0, 0; +T_3.8 ; + %load/v 8, v0x1e81c50_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_3.10, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1e81c50_0, 0, 0; +T_3.10 ; + %load/v 8, v0x1e81cd0_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1e81e50_0, 0, 8; + %load/v 8, v0x1e81e50_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1e81ef0_0, 0, 8; + %jmp T_3; + .thread T_3; + .scope S_0x1e81180; +T_4 ; + %set/v v0x1e81490_0, 0, 3; + %end; + .thread T_4; + .scope S_0x1e81180; +T_5 ; + %set/v v0x1e81770_0, 0, 1; + %end; + .thread T_5; + .scope S_0x1e81180; +T_6 ; + %set/v v0x1e817f0_0, 0, 1; + %end; + .thread T_6; + .scope S_0x1e81180; +T_7 ; + %wait E_0x1dcea60; + %load/v 8, v0x1e813f0_0, 1; + %load/v 9, v0x1e817f0_0, 1; + %cmp/u 8, 9, 1; + %jmp/0xz T_7.0, 4; + %ix/load 0, 3, 0; + %assign/v0 v0x1e81490_0, 0, 0; + %jmp T_7.1; +T_7.0 ; + %load/v 8, v0x1e81490_0, 3; + %mov 11, 0, 1; + %cmpi/u 8, 3, 4; + %jmp/0xz T_7.2, 4; + %ix/load 0, 3, 0; + %assign/v0 v0x1e81490_0, 0, 0; + %load/v 8, v0x1e817f0_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1e813f0_0, 0, 8; + %load/v 8, v0x1e813f0_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %mov 8, 4, 1; + %load/v 9, v0x1e817f0_0, 1; + %mov 10, 0, 2; + %cmpi/u 9, 1, 3; + %mov 9, 4, 1; + %and 8, 9, 1; + %jmp/0xz T_7.4, 8; + %ix/load 0, 1, 0; + %assign/v0 v0x1e81660_0, 0, 1; +T_7.4 ; + %load/v 8, v0x1e813f0_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %mov 8, 4, 1; + %load/v 9, v0x1e817f0_0, 1; + %mov 10, 0, 1; + %cmpi/u 9, 0, 2; + %mov 9, 4, 1; + %and 8, 9, 1; + %jmp/0xz T_7.6, 8; + %ix/load 0, 1, 0; + %assign/v0 v0x1e81530_0, 0, 1; +T_7.6 ; + %jmp T_7.3; +T_7.2 ; + %load/v 8, v0x1e81490_0, 3; + %mov 11, 0, 29; + %addi 8, 1, 32; + %ix/load 0, 3, 0; + %assign/v0 v0x1e81490_0, 0, 8; +T_7.3 ; +T_7.1 ; + %load/v 8, v0x1e81660_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_7.8, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1e81660_0, 0, 0; +T_7.8 ; + %load/v 8, v0x1e81530_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_7.10, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1e81530_0, 0, 0; +T_7.10 ; + %load/v 8, v0x1e815e0_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1e81770_0, 0, 8; + %load/v 8, v0x1e81770_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1e817f0_0, 0, 8; + %jmp T_7; + .thread T_7; + .scope S_0x1e80b10; +T_8 ; + %set/v v0x1e80dd0_0, 0, 3; + %end; + .thread T_8; + .scope S_0x1e80b10; +T_9 ; + %set/v v0x1e81040_0, 0, 1; + %end; + .thread T_9; + .scope S_0x1e80b10; +T_10 ; + %set/v v0x1e810e0_0, 0, 1; + %end; + .thread T_10; + .scope S_0x1e80b10; +T_11 ; + %wait E_0x1dcea60; + %load/v 8, v0x1e80d20_0, 1; + %load/v 9, v0x1e810e0_0, 1; + %cmp/u 8, 9, 1; + %jmp/0xz T_11.0, 4; + %ix/load 0, 3, 0; + %assign/v0 v0x1e80dd0_0, 0, 0; + %jmp T_11.1; +T_11.0 ; + %load/v 8, v0x1e80dd0_0, 3; + %mov 11, 0, 1; + %cmpi/u 8, 3, 4; + %jmp/0xz T_11.2, 4; + %ix/load 0, 3, 0; + %assign/v0 v0x1e80dd0_0, 0, 0; + %load/v 8, v0x1e810e0_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1e80d20_0, 0, 8; + %load/v 8, v0x1e80d20_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %mov 8, 4, 1; + %load/v 9, v0x1e810e0_0, 1; + %mov 10, 0, 2; + %cmpi/u 9, 1, 3; + %mov 9, 4, 1; + %and 8, 9, 1; + %jmp/0xz T_11.4, 8; + %ix/load 0, 1, 0; + %assign/v0 v0x1e80f80_0, 0, 1; +T_11.4 ; + %load/v 8, v0x1e80d20_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %mov 8, 4, 1; + %load/v 9, v0x1e810e0_0, 1; + %mov 10, 0, 1; + %cmpi/u 9, 0, 2; + %mov 9, 4, 1; + %and 8, 9, 1; + %jmp/0xz T_11.6, 8; + %ix/load 0, 1, 0; + %assign/v0 v0x1e80e50_0, 0, 1; +T_11.6 ; + %jmp T_11.3; +T_11.2 ; + %load/v 8, v0x1e80dd0_0, 3; + %mov 11, 0, 29; + %addi 8, 1, 32; + %ix/load 0, 3, 0; + %assign/v0 v0x1e80dd0_0, 0, 8; +T_11.3 ; +T_11.1 ; + %load/v 8, v0x1e80f80_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_11.8, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1e80f80_0, 0, 0; +T_11.8 ; + %load/v 8, v0x1e80e50_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_11.10, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1e80e50_0, 0, 0; +T_11.10 ; + %load/v 8, v0x1e80f00_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1e81040_0, 0, 8; + %load/v 8, v0x1e81040_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1e810e0_0, 0, 8; + %jmp T_11; + .thread T_11; + .scope S_0x1e803e0; +T_12 ; + %wait E_0x1dcea60; + %load/v 8, v0x1e807c0_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_12.0, 4; + %load/v 8, v0x1e80660_0, 8; + %ix/load 0, 8, 0; + %assign/v0 v0x1e80a90_0, 0, 8; + %jmp T_12.1; +T_12.0 ; + %load/v 8, v0x1e807c0_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %jmp/0xz T_12.2, 4; + %load/v 8, v0x1e808a0_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_12.4, 4; + %load/v 8, v0x1e80950_0, 1; + %load/v 9, v0x1e80a90_0, 7; Select 7 out of 8 bits + %ix/load 0, 8, 0; + %assign/v0 v0x1e80a90_0, 0, 8; +T_12.4 ; +T_12.2 ; +T_12.1 ; + %jmp T_12; + .thread T_12; + .scope S_0x1e80020; +T_13 ; + %wait E_0x1dcea60; + %load/v 8, v0x1e80230_0, 1; + %jmp/0xz T_13.0, 8; + %load/v 8, v0x1e80190_0, 7; + %ix/load 0, 7, 0; + %assign/v0 v0x1e802b0_0, 0, 8; +T_13.0 ; + %jmp T_13; + .thread T_13; + .scope S_0x1e7f6d0; +T_14 ; + %set/v v0x1e7fe80_0, 0, 5; + %end; + .thread T_14; + .scope S_0x1e7f6d0; +T_15 ; + %set/v v0x1e7fcc0_0, 0, 1; + %end; + .thread T_15; + .scope S_0x1e7f6d0; +T_16 ; + %wait E_0x1dcea60; + %load/v 8, v0x1e7fb60_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_16.0, 4; + %load/v 8, v0x1e7f960_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %jmp/0xz T_16.2, 4; + %load/v 8, v0x1e7fe80_0, 5; + %mov 13, 0, 27; + %addi 8, 1, 32; + %ix/load 0, 5, 0; + %assign/v0 v0x1e7fe80_0, 0, 8; + %load/v 8, v0x1e7fe80_0, 5; + %mov 13, 0, 2; + %cmpi/u 8, 7, 7; + %jmp/0xz T_16.4, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1e7f8c0_0, 0, 1; +T_16.4 ; + %load/v 8, v0x1e7fe80_0, 5; + %mov 13, 0, 1; + %cmpi/u 8, 8, 6; + %jmp/0xz T_16.6, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1e7f8c0_0, 0, 0; + %load/v 8, v0x1e7ff20_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %jmp/0xz T_16.8, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1e7fcc0_0, 0, 1; + %jmp T_16.9; +T_16.8 ; + %load/v 8, v0x1e7ff20_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_16.10, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1e7fbe0_0, 0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1e7fab0_0, 0, 1; +T_16.10 ; +T_16.9 ; + %jmp T_16.7; +T_16.6 ; + %movi 8, 7, 7; + %load/v 15, v0x1e7fe80_0, 5; + %mov 20, 0, 2; + %cmp/u 8, 15, 7; + %jmp/0xz T_16.12, 5; + %ix/load 0, 1, 0; + %assign/v0 v0x1e7f8c0_0, 0, 0; + %jmp T_16.13; +T_16.12 ; + %load/v 8, v0x1e7fe80_0, 5; + %mov 13, 0, 1; + %cmpi/u 8, 15, 6; + %jmp/0xz T_16.14, 4; + %ix/load 0, 5, 0; + %assign/v0 v0x1e7fe80_0, 0, 0; + %load/v 8, v0x1e7fcc0_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_16.16, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1e7fa00_0, 0, 1; +T_16.16 ; +T_16.14 ; +T_16.13 ; +T_16.7 ; + %jmp T_16.3; +T_16.2 ; + %load/v 8, v0x1e7f960_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_16.18, 4; + %ix/load 0, 5, 0; + %assign/v0 v0x1e7fe80_0, 0, 0; + %ix/load 0, 1, 0; + %assign/v0 v0x1e7fa00_0, 0, 0; + %ix/load 0, 1, 0; + %assign/v0 v0x1e7f8c0_0, 0, 0; + %ix/load 0, 1, 0; + %assign/v0 v0x1e7fbe0_0, 0, 0; + %ix/load 0, 1, 0; + %assign/v0 v0x1e7fab0_0, 0, 0; +T_16.18 ; +T_16.3 ; +T_16.0 ; + %jmp T_16; + .thread T_16; + .scope S_0x1e7f290; +T_17 ; + %wait E_0x1dcea60; + %load/v 8, v0x1e7f4e0_0, 1; + %jmp/0xz T_17.0, 8; + %load/v 8, v0x1e7f440_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1e7f580_0, 0, 8; +T_17.0 ; + %jmp T_17; + .thread T_17; + .scope S_0x1dd2c90; +T_18 ; + %wait E_0x1dcea60; + %load/v 8, v0x1e7f1b0_0, 1; + %jmp/0xz T_18.0, 8; + %load/v 8, v0x1e7efe0_0, 8; + %ix/getv 3, v0x1de6ac0_0; + %jmp/1 t_0, 4; + %ix/load 0, 8, 0; word width + %ix/load 1, 0, 0; part off + %assign/av v0x1e7f130, 0, 8; +t_0 ; +T_18.0 ; + %ix/getv 3, v0x1de6ac0_0; + %load/av 8, v0x1e7f130, 8; + %ix/load 0, 8, 0; + %assign/v0 v0x1e7f080_0, 0, 8; + %jmp T_18; + .thread T_18; + .scope S_0x1dd6760; +T_19 ; + %set/v v0x1e83220_0, 0, 1; + %end; + .thread T_19; + .scope S_0x1dd6760; +T_20 ; + %delay 10000, 0; + %load/v 8, v0x1e83220_0, 1; + %inv 8, 1; + %set/v v0x1e83220_0, 8, 1; + %jmp T_20; + .thread T_20; + .scope S_0x1dd6760; +T_21 ; + %vpi_call 2 18 "$dumpfile", "SPI.vcd"; + %vpi_call 2 19 "$dumpvars"; + %vpi_call 2 22 "$display", "CS_pin | sclk_pin | MOSI | MISO \011"; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 2000000, 0; + %set/v v0x1e832a0_0, 0, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 1600000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 2000000, 0; + %set/v v0x1e832a0_0, 0, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 1600000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 2000000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 1600000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 2000000, 0; + %set/v v0x1e832a0_0, 0, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 1600000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 1, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 1, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %set/v v0x1e832a0_0, 1, 1; + %set/v v0x1e834f0_0, 0, 1; + %set/v v0x1e83420_0, 0, 1; + %delay 48000, 0; + %vpi_call 2 257 "$finish"; + %end; + .thread T_21; +# The file index is used to find the file name in the following table. +:file_names 8; + "N/A"; + ""; + "spimemory.t.v"; + "./spimemory.v"; + "./inputconditioner.v"; + "./shiftregister.v"; + "./FSM.v"; + "./datamemory.v"; diff --git a/fsm b/fsm new file mode 100755 index 0000000..8168829 --- /dev/null +++ b/fsm @@ -0,0 +1,325 @@ +#! /usr/bin/vvp +:ivl_version "0.9.7 " "(v0_9_7)"; +:vpi_time_precision - 12; +:vpi_module "system"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0xe7e690 .scope module, "FSMtest" "FSMtest" 2 4; + .timescale -9 -12; +v0xead2e0_0 .net "ADDR_WE", 0 0, v0xe8c750_0; 1 drivers +v0xead380_0 .var "ChipSelCond", 0 0; +v0xead430_0 .net "DM_WE", 0 0, v0xeacd80_0; 1 drivers +v0xead4e0_0 .net "MISO_BUFE", 0 0, v0xeace30_0; 1 drivers +v0xead5c0_0 .var "SCLKEdge", 0 0; +v0xead670_0 .net "SR_WE", 0 0, v0xeacfb0_0; 1 drivers +v0xead6f0_0 .var "clk", 0 0; +v0xead7a0_0 .var "shiftRegOutPZero", 0 0; +S_0xe92e70 .scope module, "trial1" "FSM" 2 16, 3 8, S_0xe7e690; + .timescale -9 -12; +P_0xe92f68 .param/l "counterwidth" 3 23, +C4<0101>; +P_0xe92f90 .param/l "width" 3 22, +C4<01000>; +v0xe8c750_0 .var "ADDR_WE", 0 0; +v0xeacc40_0 .var "CSWire", 0 0; +v0xeacce0_0 .net "ChipSelCond", 0 0, v0xead380_0; 1 drivers +v0xeacd80_0 .var "DM_WE", 0 0; +v0xeace30_0 .var "MISO_BUFE", 0 0; +v0xeaced0_0 .net "SCLKEdge", 0 0, v0xead5c0_0; 1 drivers +v0xeacfb0_0 .var "SR_WE", 0 0; +v0xead050_0 .net "clk", 0 0, v0xead6f0_0; 1 drivers +v0xead140_0 .var "counter", 4 0; +v0xead1e0_0 .net "shiftRegOutPZero", 0 0, v0xead7a0_0; 1 drivers +E_0xe7e8c0 .event posedge, v0xead050_0; +S_0xe8e160 .scope module, "inputconditioner" "inputconditioner" 4 9; + .timescale -9 -12; +P_0xe8e258 .param/l "counterwidth" 4 18, +C4<011>; +P_0xe8e280 .param/l "waittime" 4 19, +C4<011>; +v0xead880_0 .net "clk", 0 0, C4; 0 drivers +v0xead900_0 .var "conditioned", 0 0; +v0xead980_0 .var "counter", 2 0; +v0xeada00_0 .var "negativeedge", 0 0; +v0xeadab0_0 .net "noisysignal", 0 0, C4; 0 drivers +v0xeadb30_0 .var "positiveedge", 0 0; +v0xeadbb0_0 .var "synchronizer0", 0 0; +v0xeadc30_0 .var "synchronizer1", 0 0; +E_0xead850 .event posedge, v0xead880_0; +S_0xe8e2b0 .scope module, "shiftregister" "shiftregister" 5 9; + .timescale -9 -12; +P_0xe8c5a8 .param/l "width" 5 10, +C4<01000>; +L_0xeae2e0 .functor BUFZ 8, v0xeae1f0_0, C4<00000000>, C4<00000000>, C4<00000000>; +v0xeadd60_0 .net "clk", 0 0, C4; 0 drivers +v0xeade20_0 .net "parallelDataIn", 7 0, C4; 0 drivers +v0xeadec0_0 .net "parallelDataOut", 7 0, L_0xeae2e0; 1 drivers +v0xeadf60_0 .net "parallelLoad", 0 0, C4; 0 drivers +v0xeae010_0 .net "peripheralClkEdge", 0 0, C4; 0 drivers +v0xeae0b0_0 .net "serialDataIn", 0 0, C4; 0 drivers +v0xeae150_0 .net "serialDataOut", 0 0, L_0xeae390; 1 drivers +v0xeae1f0_0 .var "shiftregistermem", 7 0; +E_0xeada80 .event posedge, v0xeadd60_0; +L_0xeae390 .part v0xeae1f0_0, 7, 1; + .scope S_0xe92e70; +T_0 ; + %set/v v0xead140_0, 0, 5; + %end; + .thread T_0; + .scope S_0xe92e70; +T_1 ; + %wait E_0xe7e8c0; + %load/v 8, v0xeaced0_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_1.0, 4; + %load/v 8, v0xeacce0_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %jmp/0xz T_1.2, 4; + %load/v 8, v0xead140_0, 5; + %mov 13, 0, 27; + %addi 8, 1, 32; + %ix/load 0, 5, 0; + %assign/v0 v0xead140_0, 0, 8; + %load/v 8, v0xead140_0, 5; + %mov 13, 0, 2; + %cmpi/u 8, 6, 7; + %or 5, 4, 1; + %jmp/0xz T_1.4, 5; + %ix/load 0, 1, 0; + %assign/v0 v0xe8c750_0, 0, 1; + %jmp T_1.5; +T_1.4 ; + %load/v 8, v0xead140_0, 5; + %mov 13, 0, 2; + %cmpi/u 8, 7, 7; + %jmp/0xz T_1.6, 4; + %ix/load 0, 1, 0; + %assign/v0 v0xe8c750_0, 0, 0; + %load/v 8, v0xead1e0_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %jmp/0xz T_1.8, 4; + %ix/load 0, 1, 0; + %assign/v0 v0xeacd80_0, 0, 1; + %jmp T_1.9; +T_1.8 ; + %load/v 8, v0xead1e0_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_1.10, 4; + %ix/load 0, 1, 0; + %assign/v0 v0xeacfb0_0, 0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0xeace30_0, 0, 1; +T_1.10 ; +T_1.9 ; + %jmp T_1.7; +T_1.6 ; + %movi 8, 7, 7; + %load/v 15, v0xead140_0, 5; + %mov 20, 0, 2; + %cmp/u 8, 15, 7; + %jmp/0xz T_1.12, 5; + %ix/load 0, 1, 0; + %assign/v0 v0xe8c750_0, 0, 0; + %jmp T_1.13; +T_1.12 ; + %load/v 8, v0xead140_0, 5; + %mov 13, 0, 1; + %cmpi/u 8, 15, 6; + %jmp/0xz T_1.14, 4; + %ix/load 0, 5, 0; + %assign/v0 v0xead140_0, 0, 0; + %ix/load 0, 1, 0; + %assign/v0 v0xeacc40_0, 0, 1; +T_1.14 ; +T_1.13 ; +T_1.7 ; +T_1.5 ; + %jmp T_1.3; +T_1.2 ; + %load/v 8, v0xeacce0_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_1.16, 4; + %ix/load 0, 5, 0; + %assign/v0 v0xead140_0, 0, 0; + %ix/load 0, 1, 0; + %assign/v0 v0xeacd80_0, 0, 0; + %ix/load 0, 1, 0; + %assign/v0 v0xe8c750_0, 0, 0; + %ix/load 0, 1, 0; + %assign/v0 v0xeacfb0_0, 0, 0; + %ix/load 0, 1, 0; + %assign/v0 v0xeace30_0, 0, 0; +T_1.16 ; +T_1.3 ; +T_1.0 ; + %jmp T_1; + .thread T_1; + .scope S_0xe7e690; +T_2 ; + %set/v v0xead6f0_0, 0, 1; + %end; + .thread T_2; + .scope S_0xe7e690; +T_3 ; + %delay 10000, 0; + %load/v 8, v0xead6f0_0, 1; + %inv 8, 1; + %set/v v0xead6f0_0, 8, 1; + %jmp T_3; + .thread T_3; + .scope S_0xe7e690; +T_4 ; + %vpi_call 2 25 "$dumpfile", "FSM.vcd"; + %vpi_call 2 26 "$dumpvars"; + %vpi_call 2 29 "$display", "CS | MISO_BUFE \011| DM_WE | ADDR_WE \011| SR_WE"; + %set/v v0xead380_0, 1, 1; + %set/v v0xead5c0_0, 1, 1; + %delay 200000, 0; + %vpi_call 2 31 "$display", "%b | %b\011\011| %b \011| %b \011\011| %b ", v0xead380_0, v0xead4e0_0, v0xead430_0, v0xead2e0_0, v0xead670_0; + %set/v v0xead380_0, 0, 1; + %set/v v0xead5c0_0, 1, 1; + %set/v v0xead7a0_0, 0, 1; + %delay 200000, 0; + %vpi_call 2 36 "$display", "%b | %b\011\011| %b \011| %b \011\011| %b ", v0xead380_0, v0xead4e0_0, v0xead430_0, v0xead2e0_0, v0xead670_0; + %set/v v0xead380_0, 1, 1; + %set/v v0xead5c0_0, 1, 1; + %set/v v0xead7a0_0, 1, 1; + %delay 200000, 0; + %vpi_call 2 40 "$display", "%b | %b\011\011| %b \011| %b \011\011| %b ", v0xead380_0, v0xead4e0_0, v0xead430_0, v0xead2e0_0, v0xead670_0; + %set/v v0xead380_0, 0, 1; + %set/v v0xead5c0_0, 1, 1; + %set/v v0xead7a0_0, 1, 1; + %delay 200000, 0; + %vpi_call 2 45 "$display", "%b | %b\011\011| %b \011| %b \011\011| %b ", v0xead380_0, v0xead4e0_0, v0xead430_0, v0xead2e0_0, v0xead670_0; + %vpi_call 2 47 "$finish"; + %end; + .thread T_4; + .scope S_0xe8e160; +T_5 ; + %set/v v0xead980_0, 0, 3; + %end; + .thread T_5; + .scope S_0xe8e160; +T_6 ; + %set/v v0xeadbb0_0, 0, 1; + %end; + .thread T_6; + .scope S_0xe8e160; +T_7 ; + %set/v v0xeadc30_0, 0, 1; + %end; + .thread T_7; + .scope S_0xe8e160; +T_8 ; + %wait E_0xead850; + %load/v 8, v0xead900_0, 1; + %load/v 9, v0xeadc30_0, 1; + %cmp/u 8, 9, 1; + %jmp/0xz T_8.0, 4; + %ix/load 0, 3, 0; + %assign/v0 v0xead980_0, 0, 0; + %jmp T_8.1; +T_8.0 ; + %load/v 8, v0xead980_0, 3; + %mov 11, 0, 1; + %cmpi/u 8, 3, 4; + %jmp/0xz T_8.2, 4; + %ix/load 0, 3, 0; + %assign/v0 v0xead980_0, 0, 0; + %load/v 8, v0xeadc30_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0xead900_0, 0, 8; + %load/v 8, v0xead900_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %mov 8, 4, 1; + %load/v 9, v0xeadc30_0, 1; + %mov 10, 0, 2; + %cmpi/u 9, 1, 3; + %mov 9, 4, 1; + %and 8, 9, 1; + %jmp/0xz T_8.4, 8; + %ix/load 0, 1, 0; + %assign/v0 v0xeadb30_0, 0, 1; +T_8.4 ; + %load/v 8, v0xead900_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %mov 8, 4, 1; + %load/v 9, v0xeadc30_0, 1; + %mov 10, 0, 1; + %cmpi/u 9, 0, 2; + %mov 9, 4, 1; + %and 8, 9, 1; + %jmp/0xz T_8.6, 8; + %ix/load 0, 1, 0; + %assign/v0 v0xeada00_0, 0, 1; +T_8.6 ; + %jmp T_8.3; +T_8.2 ; + %load/v 8, v0xead980_0, 3; + %mov 11, 0, 29; + %addi 8, 1, 32; + %ix/load 0, 3, 0; + %assign/v0 v0xead980_0, 0, 8; +T_8.3 ; +T_8.1 ; + %load/v 8, v0xeadb30_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_8.8, 4; + %ix/load 0, 1, 0; + %assign/v0 v0xeadb30_0, 0, 0; +T_8.8 ; + %load/v 8, v0xeada00_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_8.10, 4; + %ix/load 0, 1, 0; + %assign/v0 v0xeada00_0, 0, 0; +T_8.10 ; + %load/v 8, v0xeadab0_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0xeadbb0_0, 0, 8; + %load/v 8, v0xeadbb0_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0xeadc30_0, 0, 8; + %jmp T_8; + .thread T_8; + .scope S_0xe8e2b0; +T_9 ; + %wait E_0xeada80; + %load/v 8, v0xeadf60_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_9.0, 4; + %load/v 8, v0xeade20_0, 8; + %ix/load 0, 8, 0; + %assign/v0 v0xeae1f0_0, 0, 8; + %jmp T_9.1; +T_9.0 ; + %load/v 8, v0xeadf60_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %jmp/0xz T_9.2, 4; + %load/v 8, v0xeae010_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_9.4, 4; + %load/v 8, v0xeae0b0_0, 1; + %load/v 9, v0xeae1f0_0, 7; Select 7 out of 8 bits + %ix/load 0, 8, 0; + %assign/v0 v0xeae1f0_0, 0, 8; +T_9.4 ; +T_9.2 ; +T_9.1 ; + %jmp T_9; + .thread T_9; +# The file index is used to find the file name in the following table. +:file_names 6; + "N/A"; + ""; + "FSM.t.v"; + "./FSM.v"; + "./inputconditioner.v"; + "./shiftregister.v"; diff --git a/inputconditioner.t.v b/inputconditioner.t.v index 2814163..77fd5eb 100644 --- a/inputconditioner.t.v +++ b/inputconditioner.t.v @@ -1,6 +1,7 @@ //------------------------------------------------------------------------ // Input Conditioner test bench //------------------------------------------------------------------------ +`include "inputconditioner.v" module testConditioner(); @@ -14,16 +15,34 @@ module testConditioner(); .noisysignal(pin), .conditioned(conditioned), .positiveedge(rising), - .negativeedge(falling)) + .negativeedge(falling)); - - // Generate clock (50MHz) initial clk=0; - always #10 clk=!clk; // 50MHz Clock - + always #10 clk=!clk; // 50MHz Clock initial begin - // Your Test Code - // Be sure to test each of the three conditioner functions: - // Synchronization, Debouncing, Edge Detection - + +$dumpfile("inputconditioner.vcd"); +$dumpvars(); + +$display(" clk | pin | conditioned | -edge| + edge"); +pin = 0; #40 +$display("%b | %b | %b | %b | %b", clk, pin, conditioned, rising, falling ); +pin = 1; #100 +$display("%b | %b | %b | %b | %b", clk, pin, conditioned, rising, falling ); +pin = 0; #2 +$display("%b | %b | %b | %b | %b", clk, pin, conditioned, rising, falling ); +pin = 1; #100 +$display("%b | %b | %b | %b | %b", clk, pin, conditioned, rising, falling ); +pin = 0; #300 +$display("%b | %b | %b | %b | %b", clk, pin, conditioned, rising, falling ); +pin = 1; #3 +$display("%b | %b | %b | %b | %b", clk, pin, conditioned, rising, falling ); +pin = 0; #100 +$display("%b | %b | %b | %b | %b", clk, pin, conditioned, rising, falling ); +pin = 1; #200 +$display("%b | %b | %b | %b | %b", clk, pin, conditioned, rising, falling ); + +$finish; +end + endmodule diff --git a/inputconditioner.v b/inputconditioner.v index 736a866..7940cce 100644 --- a/inputconditioner.v +++ b/inputconditioner.v @@ -4,6 +4,7 @@ // 2) Debounces input // 3) Creates pulses at edge transitions //------------------------------------------------------------------------ +// 50 MHz is 2 * 1-^-8 seconds per cycle module inputconditioner ( @@ -14,25 +15,38 @@ output reg positiveedge, // 1 clk pulse at rising edge of conditioned output reg negativeedge // 1 clk pulse at falling edge of conditioned ); - parameter counterwidth = 3; // Counter size, in bits, >= log2(waittime) + parameter counterwidth = 3; // Counter size, in bits, >= log2(waittime) (maybe this could be 2 since 2^2 > 3) parameter waittime = 3; // Debounce delay, in clock cycles reg[counterwidth-1:0] counter = 0; reg synchronizer0 = 0; - reg synchronizer1 = 0; + reg synchronizer1 = 0; // you need 2 synchronizers so you can calculate + and - edge + +always @(posedge clk ) begin - always @(posedge clk ) begin - if(conditioned == synchronizer1) - counter <= 0; - else begin - if( counter == waittime) begin - counter <= 0; - conditioned <= synchronizer1; - end - else - counter <= counter+1; - end - synchronizer0 <= noisysignal; - synchronizer1 <= synchronizer0; - end +if(conditioned == synchronizer1) + counter <= 0; +else begin + if(counter == waittime) begin + counter <= 0; + conditioned <= synchronizer1; + if(conditioned == 0 & synchronizer1 ==1) + positiveedge <= 1; + if(conditioned == 1 & synchronizer1 ==0) + negativeedge <= 1; + end + else + counter <= counter+1; +end // end to the else begin statement + +if(positiveedge == 1) + positiveedge <= 0; +if(negativeedge == 1) + negativeedge <= 0; + +synchronizer0 <= noisysignal; // these happen every time there's a clk edge +synchronizer1 <= synchronizer0; +end + endmodule + diff --git a/inputconditioner.vcd b/inputconditioner.vcd new file mode 100644 index 0000000..822e1d8 --- /dev/null +++ b/inputconditioner.vcd @@ -0,0 +1,465 @@ +$date + Tue Oct 31 14:18:16 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module testConditioner $end +$var wire 1 ! conditioned $end +$var wire 1 " falling $end +$var wire 1 # rising $end +$var reg 1 $ clk $end +$var reg 1 % pin $end +$scope module dut $end +$var wire 1 & clk $end +$var wire 1 ' noisysignal $end +$var reg 1 ( conditioned $end +$var reg 3 ) counter [2:0] $end +$var reg 1 * negativeedge $end +$var reg 1 + positiveedge $end +$var reg 1 , synchronizer0 $end +$var reg 1 - synchronizer1 $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +0- +0, +x+ +x* +b0 ) +x( +0' +0& +0% +0$ +x# +x" +x! +$end +#10 +b1 ) +1$ +1& +#20 +0$ +0& +#30 +b10 ) +1$ +1& +#40 +0$ +0& +#50 +b11 ) +1$ +1& +#60 +0$ +0& +#70 +0( +0! +b0 ) +1$ +1& +#80 +0$ +0& +#90 +1$ +1& +#100 +0$ +0& +#110 +1$ +1& +#120 +0$ +0& +#130 +1$ +1& +#140 +0$ +0& +#150 +1$ +1& +#160 +0$ +0& +#170 +1$ +1& +#180 +0$ +0& +#190 +1$ +1& +#200 +0$ +0& +#210 +1$ +1& +#220 +0$ +0& +#230 +1$ +1& +#240 +0$ +0& +#250 +1$ +1& +#260 +0$ +0& +#270 +1$ +1& +#280 +0$ +0& +#290 +1$ +1& +#300 +0$ +0& +#310 +1$ +1& +#320 +0$ +0& +#330 +1$ +1& +#340 +0$ +0& +#350 +1$ +1& +#360 +0$ +0& +#370 +1$ +1& +#380 +0$ +0& +#390 +1$ +1& +#400 +0$ +0& +1% +1' +#410 +1, +1$ +1& +#420 +0$ +0& +#430 +1- +1$ +1& +#440 +0$ +0& +#450 +b1 ) +1$ +1& +#460 +0$ +0& +#470 +b10 ) +1$ +1& +#480 +0$ +0& +#490 +b11 ) +1$ +1& +#500 +0$ +0& +0% +0' +#502 +1% +1' +#510 +1+ +1# +1( +1! +b0 ) +1$ +1& +#520 +0$ +0& +#530 +0+ +0# +1$ +1& +#540 +0$ +0& +#550 +1$ +1& +#560 +0$ +0& +#570 +1$ +1& +#580 +0$ +0& +#590 +1$ +1& +#600 +0$ +0& +#602 +0% +0' +#610 +0, +1$ +1& +#620 +0$ +0& +#630 +0- +1$ +1& +#640 +0$ +0& +#650 +b1 ) +1$ +1& +#660 +0$ +0& +#670 +b10 ) +1$ +1& +#680 +0$ +0& +#690 +b11 ) +1$ +1& +#700 +0$ +0& +#710 +1* +1" +0( +0! +b0 ) +1$ +1& +#720 +0$ +0& +#730 +0* +0" +1$ +1& +#740 +0$ +0& +#750 +1$ +1& +#760 +0$ +0& +#770 +1$ +1& +#780 +0$ +0& +#790 +1$ +1& +#800 +0$ +0& +#810 +1$ +1& +#820 +0$ +0& +#830 +1$ +1& +#840 +0$ +0& +#850 +1$ +1& +#860 +0$ +0& +#870 +1$ +1& +#880 +0$ +0& +#890 +1$ +1& +#900 +0$ +0& +#902 +1% +1' +#905 +0% +0' +#910 +1$ +1& +#920 +0$ +0& +#930 +1$ +1& +#940 +0$ +0& +#950 +1$ +1& +#960 +0$ +0& +#970 +1$ +1& +#980 +0$ +0& +#990 +1$ +1& +#1000 +0$ +0& +#1005 +1% +1' +#1010 +1, +1$ +1& +#1020 +0$ +0& +#1030 +1- +1$ +1& +#1040 +0$ +0& +#1050 +b1 ) +1$ +1& +#1060 +0$ +0& +#1070 +b10 ) +1$ +1& +#1080 +0$ +0& +#1090 +b11 ) +1$ +1& +#1100 +0$ +0& +#1110 +1+ +1# +1( +1! +b0 ) +1$ +1& +#1120 +0$ +0& +#1130 +0+ +0# +1$ +1& +#1140 +0$ +0& +#1150 +1$ +1& +#1160 +0$ +0& +#1170 +1$ +1& +#1180 +0$ +0& +#1190 +1$ +1& +#1200 +0$ +0& +#1205 diff --git a/lab2wrapper.t.v b/lab2wrapper.t.v new file mode 100644 index 0000000..e69de29 diff --git a/lab2wrapper.v b/lab2wrapper.v new file mode 100644 index 0000000..0a5b4c3 --- /dev/null +++ b/lab2wrapper.v @@ -0,0 +1,49 @@ +//-------------------------------------------------------------------------------- +// Wrapper for Lab 0: Full Adder +// +// Rationale: +// The ZYBO board has 4 buttons, 4 switches, and 4 LEDs. +// +// This wrapper module allows for one bit to be loaded in at a time and to then show all data at once +// +// +// Usage: +// btn0 - Parallel Load +// sw0 - SerialIn +// sw1 - SCLCK +// +// Note: Buttons, switches, and LEDs have the least-significant (0) position +// on the right. +//-------------------------------------------------------------------------------- + +`timescale 1ns / 1ps +`include "midpoint.v" + + +module lab2_wrapper +( + input clk, + input [3:0] sw, // Built-in switches, used for input opA + input [3:0] btn, + output [3:0] led, // Built-in LED, used to display opA for sanity checking + output [7:0] je // Plug LD8 into JE, used to display sum, cout, overflow +); + + wire [7:0] parallelDataIn; + wire serialOut; + wire[7:0] res; + assign parallelDataIn = 8'b10010011; + assign je[7:0] = res; + assign serialOut = led[0]; + + midpoint mid(.switch0(sw[0]), .switch1(sw[1]), .button(btn[0]), .clk(clk), .parallelDataIn(parallelDataIn), .parallelDataOut2(res), .serialDataOut(serialOut)); + +endmodule + + + + + + + + diff --git a/midpoint.v b/midpoint.v new file mode 100644 index 0000000..af182ec --- /dev/null +++ b/midpoint.v @@ -0,0 +1,43 @@ +// Midpoint deliverable file + +`include "inputconditioner.v" +`include "shiftregister.v" + + +module midpoint +#(parameter width = 8) +( +input switch0, // SerialDataIn +input switch1, // peripheralClkEdge +input button, // ParallelLoad +input clk, +input [width-1:0] parallelDataIn, +output [width-1:0] parallelDataOut2, +output wire serialDataOut +); + +wire conditioned0; +wire positiveedge0; +wire negativeedge0; + +wire conditioned1; +wire positiveedge1; +wire negativeedge1; + +wire conditioned2; +wire positiveedge2; +wire negativeedge2; + + + +inputconditioner parallelLoadCond(clk, button, conditioned0, positiveedge0, negativeedge0); // negativeedge0 is your cleaned up button/ParallelLoad + +inputconditioner serialInCond(clk, switch0, conditioned1, positiveedge1, negativeedge1); // conditioned1 is your cleaned up SerialDataIn + +inputconditioner SCLKCond(clk, switch1, conditioned2, positiveedge2, negativeedge2); // positiveedge2 is your cleaned up peripheralClkEdge + +shiftregister shift(clk, positiveedge2, negativeedge0, parallelDataIn, conditioned1, parallelDataOut2, serialDataOut); + +endmodule + + diff --git a/shiftregister.t.v b/shiftregister.t.v index abe5b48..90a0fb3 100644 --- a/shiftregister.t.v +++ b/shiftregister.t.v @@ -2,6 +2,8 @@ // Shift Register test bench //------------------------------------------------------------------------ +`include "shiftregister.v" + module testshiftregister(); reg clk; @@ -11,7 +13,8 @@ module testshiftregister(); wire serialDataOut; reg[7:0] parallelDataIn; reg serialDataIn; - + + // Instantiate with parameter width = 8 shiftregister #(8) dut(.clk(clk), .peripheralClkEdge(peripheralClkEdge), @@ -20,9 +23,50 @@ module testshiftregister(); .serialDataIn(serialDataIn), .parallelDataOut(parallelDataOut), .serialDataOut(serialDataOut)); + + + initial clk=0; + always #10 clk=!clk; // 50MHz Clock initial begin - // Your Test Code + +$dumpfile("shiftregister.vcd"); +$dumpvars(); + + + +// Check Parallel In, Serial Out + $display("PIn? | PDataIn | SDataOut"); + parallelLoad =1; parallelDataIn = 8'b00011111; #21 + $display("%b | %b | %b ", parallelLoad, parallelDataIn, serialDataOut); // expect 0 + parallelLoad =1; parallelDataIn = 8'b00111110; #21 + $display("%b | %b | %b", parallelLoad, parallelDataIn, serialDataOut); // expect 0 + parallelLoad =1; parallelDataIn = 8'b01111101; #21 + $display("%b | %b | %b", parallelLoad, parallelDataIn, serialDataOut); // expect 0 + parallelLoad =1; parallelDataIn = 8'b11111010; #21 + $display("%b | %b | %b", parallelLoad, parallelDataIn, serialDataOut); // expect 1 + parallelLoad =1; parallelDataIn = 8'b11110100; #500 + $display("%b | %b | %b", parallelLoad, parallelDataIn, serialDataOut); // expect 1 + +// Check Serial In, Parallel Out +// This is what we'll want to do on the FPGA + + $display("PIn? | SDataIn | PDataOut"); + parallelLoad =0; serialDataIn = 1; peripheralClkEdge = 1; #21 + $display("%b | %b | %b ", parallelLoad, serialDataIn, parallelDataOut); + parallelLoad =0; serialDataIn = 1;peripheralClkEdge = 1; #21 + $display("%b | %b | %b ", parallelLoad, serialDataIn, parallelDataOut); + parallelLoad =0; serialDataIn = 0;peripheralClkEdge = 1; #21 + $display("%b | %b | %b ", parallelLoad, serialDataIn, parallelDataOut); + parallelLoad =0; serialDataIn = 0;peripheralClkEdge = 1; #21 + $display("%b | %b | %b ", parallelLoad, serialDataIn, parallelDataOut); + parallelLoad =0; serialDataIn = 0;peripheralClkEdge = 1; #21 + $display("%b | %b | %b ", parallelLoad, serialDataIn, parallelDataOut); + parallelLoad =0; serialDataIn = 1;peripheralClkEdge = 1; #21 + $display("%b | %b | %b ", parallelLoad, serialDataIn, parallelDataOut); + + + $finish; end endmodule diff --git a/shiftregister.v b/shiftregister.v index b4ec057..bc72137 100644 --- a/shiftregister.v +++ b/shiftregister.v @@ -14,12 +14,31 @@ input peripheralClkEdge, // Edge indicator input parallelLoad, // 1 = Load shift reg with parallelDataIn input [width-1:0] parallelDataIn, // Load shift reg in parallel input serialDataIn, // Load shift reg serially -output [width-1:0] parallelDataOut, // Shift reg data contents -output serialDataOut // Positive edge synchronized +output wire [width-1:0] parallelDataOut, // Shift reg data contents +output wire serialDataOut // Positive edge synchronized ); - reg [width-1:0] shiftregistermem; - always @(posedge clk) begin - // Your Code Here - end +reg [width-1:0] shiftregistermem; +assign parallelDataOut = shiftregistermem; +assign serialDataOut = shiftregistermem[width-1]; + +always @(posedge clk) begin + + if(parallelLoad ==1) begin // do thisfor parallel data in + + shiftregistermem <= parallelDataIn; + + end + + else if(parallelLoad ==0) begin // We are deciding that parallelLoad will win. This takes priority over serial shift - peripheralClkEdge only matters if parallelLoad = 0. + if (peripheralClkEdge == 1) begin + shiftregistermem <= {shiftregistermem[width-2:0], serialDataIn}; + + + end + end + +end + endmodule + diff --git a/shiftregister.vcd b/shiftregister.vcd new file mode 100644 index 0000000..43adda3 --- /dev/null +++ b/shiftregister.vcd @@ -0,0 +1,325 @@ +$date + Tue Oct 31 18:22:21 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module testshiftregister $end +$var wire 8 ! parallelDataOut [7:0] $end +$var wire 1 " serialDataOut $end +$var reg 1 # clk $end +$var reg 8 $ parallelDataIn [7:0] $end +$var reg 1 % parallelLoad $end +$var reg 1 & peripheralClkEdge $end +$var reg 1 ' serialDataIn $end +$scope module dut $end +$var wire 1 ( clk $end +$var wire 8 ) parallelDataIn [7:0] $end +$var wire 8 * parallelDataOut [7:0] $end +$var wire 1 + parallelLoad $end +$var wire 1 , peripheralClkEdge $end +$var wire 1 - serialDataIn $end +$var wire 1 " serialDataOut $end +$var reg 8 . shiftregistermem [7:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +bx . +x- +x, +1+ +bx * +b11111 ) +0( +x' +x& +1% +b11111 $ +0# +x" +bx ! +$end +#10 +0" +b11111 . +b11111 ! +b11111 * +1# +1( +#20 +0# +0( +#21 +b111110 $ +b111110 ) +#30 +b111110 . +b111110 ! +b111110 * +1# +1( +#40 +0# +0( +#42 +b1111101 $ +b1111101 ) +#50 +b1111101 . +b1111101 ! +b1111101 * +1# +1( +#60 +0# +0( +#63 +b11111010 $ +b11111010 ) +#70 +1" +b11111010 . +b11111010 ! +b11111010 * +1# +1( +#80 +0# +0( +#84 +b11110100 $ +b11110100 ) +#90 +b11110100 . +b11110100 ! +b11110100 * +1# +1( +#100 +0# +0( +#110 +1# +1( +#120 +0# +0( +#130 +1# +1( +#140 +0# +0( +#150 +1# +1( +#160 +0# +0( +#170 +1# +1( +#180 +0# +0( +#190 +1# +1( +#200 +0# +0( +#210 +1# +1( +#220 +0# +0( +#230 +1# +1( +#240 +0# +0( +#250 +1# +1( +#260 +0# +0( +#270 +1# +1( +#280 +0# +0( +#290 +1# +1( +#300 +0# +0( +#310 +1# +1( +#320 +0# +0( +#330 +1# +1( +#340 +0# +0( +#350 +1# +1( +#360 +0# +0( +#370 +1# +1( +#380 +0# +0( +#390 +1# +1( +#400 +0# +0( +#410 +1# +1( +#420 +0# +0( +#430 +1# +1( +#440 +0# +0( +#450 +1# +1( +#460 +0# +0( +#470 +1# +1( +#480 +0# +0( +#490 +1# +1( +#500 +0# +0( +#510 +1# +1( +#520 +0# +0( +#530 +1# +1( +#540 +0# +0( +#550 +1# +1( +#560 +0# +0( +#570 +1# +1( +#580 +0# +0( +#584 +1& +1, +1' +1- +0% +0+ +#590 +b11101001 . +b11101001 ! +b11101001 * +1# +1( +#600 +0# +0( +#610 +b11010011 . +b11010011 ! +b11010011 * +1# +1( +#620 +0# +0( +#626 +0' +0- +#630 +b10100110 . +b10100110 ! +b10100110 * +1# +1( +#640 +0# +0( +#650 +0" +b1001100 . +b1001100 ! +b1001100 * +1# +1( +#660 +0# +0( +#670 +1" +b10011000 . +b10011000 ! +b10011000 * +1# +1( +#680 +0# +0( +#689 +1' +1- +#690 +0" +b110001 . +b110001 ! +b110001 * +1# +1( +#700 +0# +0( +#710 +b1100011 . +b1100011 ! +b1100011 * +1# +1( diff --git a/spimemory.t.v b/spimemory.t.v new file mode 100644 index 0000000..32d21c1 --- /dev/null +++ b/spimemory.t.v @@ -0,0 +1,185 @@ +`include "spimemory.v" + +module spitest(); + reg clk; // FPGA clock + reg sclk_pin; // SPI clock + reg cs_pin; // SPI chip select + wire miso_pin; // SPI master in slave out + reg mosi_pin; // SPI master out slave in + wire [3:0] leds; // LEDs for debugging + +//FSM trial1(clk, SCLKEdge, ChipSelCond, shiftRegOutPZero, MISO_BUFE, DM_WE, ADDR_WE, SR_WE); +spiMemory spitime(clk, sclk_pin, cs_pin, miso_pin, mosi_pin, leds); + +initial clk=0; +always #10 clk=!clk; // 50MHz Clock + +initial begin +$dumpfile("SPI.vcd"); +$dumpvars(); + + +$display("CS_pin | sclk_pin | MOSI | MISO "); + +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #200 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #180 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #200 + + +/* TESTING FOR CHIP SELECT 1 DOES NOTHING +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +*/ + +cs_pin = 1; sclk_pin= 0; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #48 +cs_pin = 1; sclk_pin= 0; mosi_pin = 1; #48 +cs_pin = 1; sclk_pin= 1; mosi_pin = 1; #48 + + +// TURN CHIP SELECT ON +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 1; #160 +cs_pin = 0; sclk_pin= 0; mosi_pin = 1; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 // THESE SET IT TO WRITE +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 // SET TO WRITE +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 // 0 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 // 1 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 // 2 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 // 3 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 1; #160 // 4 +cs_pin = 0; sclk_pin= 0; mosi_pin = 1; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 1; #160 // 5 +cs_pin = 0; sclk_pin= 0; mosi_pin = 1; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 // 6 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 // 7 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 // 8 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #600 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #600 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #600 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #600 +// start counting address again - FOR READING +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 1; #160 +cs_pin = 0; sclk_pin= 0; mosi_pin = 1; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 1; #160 // SET TO READ +cs_pin = 0; sclk_pin= 0; mosi_pin = 1; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 // 0 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 // 1 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 // 2 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 // 3 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 1; #160 // 4 +cs_pin = 0; sclk_pin= 0; mosi_pin = 1; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 1; #160 // 5 +cs_pin = 0; sclk_pin= 0; mosi_pin = 1; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 // 6 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 // 7 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 0; sclk_pin= 1; mosi_pin = 0; #160 // 8 +cs_pin = 0; sclk_pin= 0; mosi_pin = 0; #160 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #600 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #600 +cs_pin = 1; sclk_pin= 0; mosi_pin = 0; #600 +cs_pin = 1; sclk_pin= 1; mosi_pin = 0; #600 + + + +$finish; +end + +endmodule diff --git a/spimemory.v b/spimemory.v index c6ed4f7..9a4b901 100644 --- a/spimemory.v +++ b/spimemory.v @@ -2,6 +2,10 @@ // SPI Memory //------------------------------------------------------------------------ +`timescale 1 ns / 1 ps +`include "FSM.v" +`include "datamemory.v" + module spiMemory ( input clk, // FPGA clock @@ -10,8 +14,85 @@ module spiMemory output miso_pin, // SPI master in slave out input mosi_pin, // SPI master out slave in output [3:0] leds // LEDs for debugging -) +); +parameter size = 8; // for now + +// MOSI conditioned variables +wire MOSI; +wire positiveedge0; +wire negativeedge0; + +// SCLK conditioned variables +wire conditioned1; +wire SCLKEdge; +wire negativeedge1; + +// Chip Select conditioned variables +wire ChipSel; +wire positiveedge2; +wire negativeedge2; + +// Other variables +wire MISO; +wire MISO_PreBuff; +wire [size-1:0] shiftRegOutP; +wire [6:0] address; +wire [size-1:0] dataMemOut; +wire MISO_BUFE; +wire DM_WE; +wire ADDR_WE; +wire SR_WE; + +// parameter counterwidth = 5; // Counter size, in bits, >= log2(waittime) +// reg[counterwidth-1:0] counter = 0; + +inputconditioner serialInCond(clk, mosi_pin, MOSI, positiveedge0, negativeedge0); // MOSICond is cleaned up MOSI / Serial In + +inputconditioner SCLKCond(clk, sclk_pin, conditioned1, SCLKEdge, negativeedge1); // positive edge is your cleaned up SCLKEdge + +inputconditioner ChipSelCond(clk, cs_pin, ChipSel, positiveedge2, negativeedge2); // conditioned2 is your cleaned up Chip Select + + shiftregister SPIShift(clk, SCLKEdge, SR_WE, dataMemOut, MOSI, shiftRegOutP, MISO); + + dffADDR DFFAddr(clk, ADDR_WE, shiftRegOutP[7:1], address); + FSM SPIFSM(clk, SCLKEdge, ChipSel, shiftRegOutP[0], MISO_BUFE, DM_WE, ADDR_WE, SR_WE); + + dff DFFMISO(clk, negativeedge1, MISO, MISO_PreBuff); + + datamemory data(clk, dataMemOut, address, DM_WE, shiftRegOutP); + + bufif1 covefefe(miso_pin, MISO_PreBuff, MISO_BUFE); endmodule + +module dff #( parameter W = 1 ) +( + input trigger, + input enable, + input [W-1:0] d, + output reg [W-1:0] q +); + always @(posedge trigger) begin + if(enable) begin + q <= d; + end + end +endmodule + +module dffADDR #( parameter W = 7 ) +( + input trigger, + input enable, + input [W-1:0] d, + output reg [W-1:0] q +); + always @(posedge trigger) begin + if(enable) begin + q <= d; + end + end +endmodule + + diff --git a/test b/test new file mode 100755 index 0000000..ca2ba8e --- /dev/null +++ b/test @@ -0,0 +1,975 @@ +#! /usr/bin/vvp +:ivl_version "0.9.7 " "(v0_9_7)"; +:vpi_time_precision - 12; +:vpi_module "system"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x1e40190 .scope module, "spitest" "spitest" 2 3; + .timescale -9 -12; +v0x1eab860_0 .var "clk", 0 0; +v0x1eab8e0_0 .var "cs_pin", 0 0; +v0x1eab960_0 .net "leds", 3 0, C4; 0 drivers +v0x1eab9e0_0 .net8 "miso_pin", 0 0, L_0x1eabec0; 1 drivers, strength-aware +v0x1eaba60_0 .var "mosi_pin", 0 0; +v0x1eabb30_0 .var "sclk_pin", 0 0; +S_0x1e3d9f0 .scope module, "spitime" "spiMemory" 2 12, 3 9, S_0x1e40190; + .timescale -9 -12; +P_0x1e44fe8 .param/l "size" 3 18, +C4<01000>; +L_0x1eabec0 .functor BUFIF1 1, v0x1ea7bc0_0, v0x1ea80f0_0, C4<0>, C4<0>; +v0x1eaa620_0 .net "ADDR_WE", 0 0, v0x1ea7f00_0; 1 drivers +v0x1eaa710_0 .net "ChipSel", 0 0, v0x1ea9360_0; 1 drivers +v0x1eaa7e0_0 .net "DM_WE", 0 0, v0x1ea8040_0; 1 drivers +v0x1eaa8b0_0 .net "MISO", 0 0, L_0x1eabc00; 1 drivers +v0x1eaa980_0 .net "MISO_BUFE", 0 0, v0x1ea80f0_0; 1 drivers +v0x1eaaa00_0 .net "MISO_PreBuff", 0 0, v0x1ea7bc0_0; 1 drivers +v0x1eaaa80_0 .net "MOSI", 0 0, v0x1eaa190_0; 1 drivers +v0x1eaab50_0 .net "SCLKEdge", 0 0, v0x1ea9ca0_0; 1 drivers +v0x1eaac20_0 .net "SR_WE", 0 0, v0x1ea8220_0; 1 drivers +v0x1eaacf0_0 .net "address", 6 0, v0x1ea88f0_0; 1 drivers +v0x1eaadd0_0 .net "clk", 0 0, v0x1eab860_0; 1 drivers +v0x1ea8c10_0 .net "conditioned1", 0 0, v0x1ea9a30_0; 1 drivers +v0x1eaafd0_0 .net "cs_pin", 0 0, v0x1eab8e0_0; 1 drivers +v0x1eab050_0 .net "dataMemOut", 7 0, v0x1ea76c0_0; 1 drivers +v0x1eab1a0_0 .alias "leds", 3 0, v0x1eab960_0; +v0x1eab220_0 .alias "miso_pin", 0 0, v0x1eab9e0_0; +v0x1eab0d0_0 .net "mosi_pin", 0 0, v0x1eaba60_0; 1 drivers +v0x1eab330_0 .net "negativeedge0", 0 0, v0x1eaa290_0; 1 drivers +v0x1eab2a0_0 .net "negativeedge1", 0 0, v0x1ea9b70_0; 1 drivers +v0x1eab4a0_0 .net "negativeedge2", 0 0, v0x1ea9490_0; 1 drivers +v0x1eab3b0_0 .net "positiveedge0", 0 0, v0x1eaa3b0_0; 1 drivers +v0x1eab5d0_0 .net "positiveedge2", 0 0, v0x1ea95c0_0; 1 drivers +v0x1eab520_0 .net "sclk_pin", 0 0, v0x1eabb30_0; 1 drivers +v0x1eab710_0 .net "shiftRegOutP", 7 0, L_0x1eaad70; 1 drivers +L_0x1eabcf0 .part L_0x1eaad70, 1, 7; +L_0x1eabe20 .part L_0x1eaad70, 0, 1; +S_0x1ea9f20 .scope module, "serialInCond" "inputconditioner" 3 49, 4 9, S_0x1e3d9f0; + .timescale -9 -12; +P_0x1eaa018 .param/l "counterwidth" 4 18, +C4<011>; +P_0x1eaa040 .param/l "waittime" 4 19, +C4<011>; +v0x1eaa110_0 .alias "clk", 0 0, v0x1eaadd0_0; +v0x1eaa190_0 .var "conditioned", 0 0; +v0x1eaa210_0 .var "counter", 2 0; +v0x1eaa290_0 .var "negativeedge", 0 0; +v0x1eaa310_0 .alias "noisysignal", 0 0, v0x1eab0d0_0; +v0x1eaa3b0_0 .var "positiveedge", 0 0; +v0x1eaa490_0 .var "synchronizer0", 0 0; +v0x1eaa530_0 .var "synchronizer1", 0 0; +S_0x1ea97c0 .scope module, "SCLKCond" "inputconditioner" 3 51, 4 9, S_0x1e3d9f0; + .timescale -9 -12; +P_0x1ea98b8 .param/l "counterwidth" 4 18, +C4<011>; +P_0x1ea98e0 .param/l "waittime" 4 19, +C4<011>; +v0x1ea99b0_0 .alias "clk", 0 0, v0x1eaadd0_0; +v0x1ea9a30_0 .var "conditioned", 0 0; +v0x1ea9ad0_0 .var "counter", 2 0; +v0x1ea9b70_0 .var "negativeedge", 0 0; +v0x1ea9c20_0 .alias "noisysignal", 0 0, v0x1eab520_0; +v0x1ea9ca0_0 .var "positiveedge", 0 0; +v0x1ea9db0_0 .var "synchronizer0", 0 0; +v0x1ea9e30_0 .var "synchronizer1", 0 0; +S_0x1ea9150 .scope module, "ChipSelCond" "inputconditioner" 3 53, 4 9, S_0x1e3d9f0; + .timescale -9 -12; +P_0x1ea9248 .param/l "counterwidth" 4 18, +C4<011>; +P_0x1ea9270 .param/l "waittime" 4 19, +C4<011>; +v0x1ea92e0_0 .alias "clk", 0 0, v0x1eaadd0_0; +v0x1ea9360_0 .var "conditioned", 0 0; +v0x1ea9410_0 .var "counter", 2 0; +v0x1ea9490_0 .var "negativeedge", 0 0; +v0x1ea9540_0 .alias "noisysignal", 0 0, v0x1eaafd0_0; +v0x1ea95c0_0 .var "positiveedge", 0 0; +v0x1ea9680_0 .var "synchronizer0", 0 0; +v0x1ea9720_0 .var "synchronizer1", 0 0; +S_0x1ea8a20 .scope module, "SPIShift" "shiftregister" 3 55, 5 9, S_0x1e3d9f0; + .timescale -9 -12; +P_0x1ea8b18 .param/l "width" 5 10, +C4<01000>; +L_0x1eaad70 .functor BUFZ 8, v0x1ea90d0_0, C4<00000000>, C4<00000000>, C4<00000000>; +v0x1ea8b90_0 .alias "clk", 0 0, v0x1eaadd0_0; +v0x1ea8ca0_0 .alias "parallelDataIn", 7 0, v0x1eab050_0; +v0x1ea8d50_0 .alias "parallelDataOut", 7 0, v0x1eab710_0; +v0x1ea8e00_0 .alias "parallelLoad", 0 0, v0x1eaac20_0; +v0x1ea8ee0_0 .alias "peripheralClkEdge", 0 0, v0x1eaab50_0; +v0x1ea8f90_0 .alias "serialDataIn", 0 0, v0x1eaaa80_0; +v0x1ea9050_0 .alias "serialDataOut", 0 0, v0x1eaa8b0_0; +v0x1ea90d0_0 .var "shiftregistermem", 7 0; +L_0x1eabc00 .part v0x1ea90d0_0, 7, 1; +S_0x1ea8660 .scope module, "DFFAddr" "dffADDR" 3 57, 3 84, S_0x1e3d9f0; + .timescale -9 -12; +P_0x1ea82a8 .param/l "W" 3 84, +C4<0111>; +v0x1ea87d0_0 .net "d", 6 0, L_0x1eabcf0; 1 drivers +v0x1ea8870_0 .alias "enable", 0 0, v0x1eaa620_0; +v0x1ea88f0_0 .var "q", 6 0; +v0x1ea8970_0 .alias "trigger", 0 0, v0x1eaadd0_0; +S_0x1ea7d10 .scope module, "SPIFSM" "FSM" 3 59, 6 8, S_0x1e3d9f0; + .timescale -9 -12; +P_0x1ea7e08 .param/l "counterwidth" 6 23, +C4<0101>; +P_0x1ea7e30 .param/l "width" 6 22, +C4<01000>; +v0x1ea7f00_0 .var "ADDR_WE", 0 0; +v0x1ea7fa0_0 .alias "ChipSelCond", 0 0, v0x1eaa710_0; +v0x1ea8040_0 .var "DM_WE", 0 0; +v0x1ea80f0_0 .var "MISO_BUFE", 0 0; +v0x1ea81a0_0 .alias "SCLKEdge", 0 0, v0x1eaab50_0; +v0x1ea8220_0 .var "SR_WE", 0 0; +v0x1ea8300_0 .var "WriteController", 0 0; +v0x1ea83a0_0 .alias "clk", 0 0, v0x1eaadd0_0; +v0x1ea84c0_0 .var "counter", 4 0; +v0x1ea8560_0 .net "shiftRegOutPZero", 0 0, L_0x1eabe20; 1 drivers +S_0x1ea78d0 .scope module, "DFFMISO" "dff" 3 61, 3 70, S_0x1e3d9f0; + .timescale -9 -12; +P_0x1ea79c8 .param/l "W" 3 70, +C4<01>; +v0x1ea7a80_0 .alias "d", 0 0, v0x1eaa8b0_0; +v0x1ea7b20_0 .alias "enable", 0 0, v0x1eab2a0_0; +v0x1ea7bc0_0 .var "q", 0 0; +v0x1ea7c60_0 .alias "trigger", 0 0, v0x1eaadd0_0; +S_0x1e3c720 .scope module, "data" "datamemory" 3 63, 7 8, S_0x1e3d9f0; + .timescale -9 -12; +P_0x1e491b8 .param/l "addresswidth" 7 10, +C4<0111>; +P_0x1e491e0 .param/l "depth" 7 11, +C4<010000000>; +P_0x1e49208 .param/l "width" 7 12, +C4<01000>; +v0x1e4fc00_0 .alias "address", 6 0, v0x1eaacf0_0; +v0x1ea7580_0 .alias "clk", 0 0, v0x1eaadd0_0; +v0x1ea7620_0 .alias "dataIn", 7 0, v0x1eab710_0; +v0x1ea76c0_0 .var "dataOut", 7 0; +v0x1ea7770 .array "memory", 0 127, 7 0; +v0x1ea77f0_0 .alias "writeEnable", 0 0, v0x1eaa7e0_0; +E_0x1e38510 .event posedge, v0x1ea7580_0; + .scope S_0x1ea9f20; +T_0 ; + %set/v v0x1eaa210_0, 0, 3; + %end; + .thread T_0; + .scope S_0x1ea9f20; +T_1 ; + %set/v v0x1eaa490_0, 0, 1; + %end; + .thread T_1; + .scope S_0x1ea9f20; +T_2 ; + %set/v v0x1eaa530_0, 0, 1; + %end; + .thread T_2; + .scope S_0x1ea9f20; +T_3 ; + %wait E_0x1e38510; + %load/v 8, v0x1eaa190_0, 1; + %load/v 9, v0x1eaa530_0, 1; + %cmp/u 8, 9, 1; + %jmp/0xz T_3.0, 4; + %ix/load 0, 3, 0; + %assign/v0 v0x1eaa210_0, 0, 0; + %jmp T_3.1; +T_3.0 ; + %load/v 8, v0x1eaa210_0, 3; + %mov 11, 0, 1; + %cmpi/u 8, 3, 4; + %jmp/0xz T_3.2, 4; + %ix/load 0, 3, 0; + %assign/v0 v0x1eaa210_0, 0, 0; + %load/v 8, v0x1eaa530_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1eaa190_0, 0, 8; + %load/v 8, v0x1eaa190_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %mov 8, 4, 1; + %load/v 9, v0x1eaa530_0, 1; + %mov 10, 0, 2; + %cmpi/u 9, 1, 3; + %mov 9, 4, 1; + %and 8, 9, 1; + %jmp/0xz T_3.4, 8; + %ix/load 0, 1, 0; + %assign/v0 v0x1eaa3b0_0, 0, 1; +T_3.4 ; + %load/v 8, v0x1eaa190_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %mov 8, 4, 1; + %load/v 9, v0x1eaa530_0, 1; + %mov 10, 0, 1; + %cmpi/u 9, 0, 2; + %mov 9, 4, 1; + %and 8, 9, 1; + %jmp/0xz T_3.6, 8; + %ix/load 0, 1, 0; + %assign/v0 v0x1eaa290_0, 0, 1; +T_3.6 ; + %jmp T_3.3; +T_3.2 ; + %load/v 8, v0x1eaa210_0, 3; + %mov 11, 0, 29; + %addi 8, 1, 32; + %ix/load 0, 3, 0; + %assign/v0 v0x1eaa210_0, 0, 8; +T_3.3 ; +T_3.1 ; + %load/v 8, v0x1eaa3b0_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_3.8, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1eaa3b0_0, 0, 0; +T_3.8 ; + %load/v 8, v0x1eaa290_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_3.10, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1eaa290_0, 0, 0; +T_3.10 ; + %load/v 8, v0x1eaa310_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1eaa490_0, 0, 8; + %load/v 8, v0x1eaa490_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1eaa530_0, 0, 8; + %jmp T_3; + .thread T_3; + .scope S_0x1ea97c0; +T_4 ; + %set/v v0x1ea9ad0_0, 0, 3; + %end; + .thread T_4; + .scope S_0x1ea97c0; +T_5 ; + %set/v v0x1ea9db0_0, 0, 1; + %end; + .thread T_5; + .scope S_0x1ea97c0; +T_6 ; + %set/v v0x1ea9e30_0, 0, 1; + %end; + .thread T_6; + .scope S_0x1ea97c0; +T_7 ; + %wait E_0x1e38510; + %load/v 8, v0x1ea9a30_0, 1; + %load/v 9, v0x1ea9e30_0, 1; + %cmp/u 8, 9, 1; + %jmp/0xz T_7.0, 4; + %ix/load 0, 3, 0; + %assign/v0 v0x1ea9ad0_0, 0, 0; + %jmp T_7.1; +T_7.0 ; + %load/v 8, v0x1ea9ad0_0, 3; + %mov 11, 0, 1; + %cmpi/u 8, 3, 4; + %jmp/0xz T_7.2, 4; + %ix/load 0, 3, 0; + %assign/v0 v0x1ea9ad0_0, 0, 0; + %load/v 8, v0x1ea9e30_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea9a30_0, 0, 8; + %load/v 8, v0x1ea9a30_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %mov 8, 4, 1; + %load/v 9, v0x1ea9e30_0, 1; + %mov 10, 0, 2; + %cmpi/u 9, 1, 3; + %mov 9, 4, 1; + %and 8, 9, 1; + %jmp/0xz T_7.4, 8; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea9ca0_0, 0, 1; +T_7.4 ; + %load/v 8, v0x1ea9a30_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %mov 8, 4, 1; + %load/v 9, v0x1ea9e30_0, 1; + %mov 10, 0, 1; + %cmpi/u 9, 0, 2; + %mov 9, 4, 1; + %and 8, 9, 1; + %jmp/0xz T_7.6, 8; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea9b70_0, 0, 1; +T_7.6 ; + %jmp T_7.3; +T_7.2 ; + %load/v 8, v0x1ea9ad0_0, 3; + %mov 11, 0, 29; + %addi 8, 1, 32; + %ix/load 0, 3, 0; + %assign/v0 v0x1ea9ad0_0, 0, 8; +T_7.3 ; +T_7.1 ; + %load/v 8, v0x1ea9ca0_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_7.8, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea9ca0_0, 0, 0; +T_7.8 ; + %load/v 8, v0x1ea9b70_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_7.10, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea9b70_0, 0, 0; +T_7.10 ; + %load/v 8, v0x1ea9c20_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea9db0_0, 0, 8; + %load/v 8, v0x1ea9db0_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea9e30_0, 0, 8; + %jmp T_7; + .thread T_7; + .scope S_0x1ea9150; +T_8 ; + %set/v v0x1ea9410_0, 0, 3; + %end; + .thread T_8; + .scope S_0x1ea9150; +T_9 ; + %set/v v0x1ea9680_0, 0, 1; + %end; + .thread T_9; + .scope S_0x1ea9150; +T_10 ; + %set/v v0x1ea9720_0, 0, 1; + %end; + .thread T_10; + .scope S_0x1ea9150; +T_11 ; + %wait E_0x1e38510; + %load/v 8, v0x1ea9360_0, 1; + %load/v 9, v0x1ea9720_0, 1; + %cmp/u 8, 9, 1; + %jmp/0xz T_11.0, 4; + %ix/load 0, 3, 0; + %assign/v0 v0x1ea9410_0, 0, 0; + %jmp T_11.1; +T_11.0 ; + %load/v 8, v0x1ea9410_0, 3; + %mov 11, 0, 1; + %cmpi/u 8, 3, 4; + %jmp/0xz T_11.2, 4; + %ix/load 0, 3, 0; + %assign/v0 v0x1ea9410_0, 0, 0; + %load/v 8, v0x1ea9720_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea9360_0, 0, 8; + %load/v 8, v0x1ea9360_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %mov 8, 4, 1; + %load/v 9, v0x1ea9720_0, 1; + %mov 10, 0, 2; + %cmpi/u 9, 1, 3; + %mov 9, 4, 1; + %and 8, 9, 1; + %jmp/0xz T_11.4, 8; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea95c0_0, 0, 1; +T_11.4 ; + %load/v 8, v0x1ea9360_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %mov 8, 4, 1; + %load/v 9, v0x1ea9720_0, 1; + %mov 10, 0, 1; + %cmpi/u 9, 0, 2; + %mov 9, 4, 1; + %and 8, 9, 1; + %jmp/0xz T_11.6, 8; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea9490_0, 0, 1; +T_11.6 ; + %jmp T_11.3; +T_11.2 ; + %load/v 8, v0x1ea9410_0, 3; + %mov 11, 0, 29; + %addi 8, 1, 32; + %ix/load 0, 3, 0; + %assign/v0 v0x1ea9410_0, 0, 8; +T_11.3 ; +T_11.1 ; + %load/v 8, v0x1ea95c0_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_11.8, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea95c0_0, 0, 0; +T_11.8 ; + %load/v 8, v0x1ea9490_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_11.10, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea9490_0, 0, 0; +T_11.10 ; + %load/v 8, v0x1ea9540_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea9680_0, 0, 8; + %load/v 8, v0x1ea9680_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea9720_0, 0, 8; + %jmp T_11; + .thread T_11; + .scope S_0x1ea8a20; +T_12 ; + %wait E_0x1e38510; + %load/v 8, v0x1ea8e00_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_12.0, 4; + %load/v 8, v0x1ea8ca0_0, 8; + %ix/load 0, 8, 0; + %assign/v0 v0x1ea90d0_0, 0, 8; + %jmp T_12.1; +T_12.0 ; + %load/v 8, v0x1ea8e00_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %jmp/0xz T_12.2, 4; + %load/v 8, v0x1ea8ee0_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_12.4, 4; + %load/v 8, v0x1ea8f90_0, 1; + %load/v 9, v0x1ea90d0_0, 7; Select 7 out of 8 bits + %ix/load 0, 8, 0; + %assign/v0 v0x1ea90d0_0, 0, 8; +T_12.4 ; +T_12.2 ; +T_12.1 ; + %jmp T_12; + .thread T_12; + .scope S_0x1ea8660; +T_13 ; + %wait E_0x1e38510; + %load/v 8, v0x1ea8870_0, 1; + %jmp/0xz T_13.0, 8; + %load/v 8, v0x1ea87d0_0, 7; + %ix/load 0, 7, 0; + %assign/v0 v0x1ea88f0_0, 0, 8; +T_13.0 ; + %jmp T_13; + .thread T_13; + .scope S_0x1ea7d10; +T_14 ; + %set/v v0x1ea84c0_0, 0, 5; + %end; + .thread T_14; + .scope S_0x1ea7d10; +T_15 ; + %wait E_0x1e38510; + %load/v 8, v0x1ea81a0_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_15.0, 4; + %load/v 8, v0x1ea7fa0_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %jmp/0xz T_15.2, 4; + %load/v 8, v0x1ea84c0_0, 5; + %mov 13, 0, 27; + %addi 8, 1, 32; + %ix/load 0, 5, 0; + %assign/v0 v0x1ea84c0_0, 0, 8; + %load/v 8, v0x1ea84c0_0, 5; + %mov 13, 0, 2; + %cmpi/u 8, 7, 7; + %jmp/0xz T_15.4, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea7f00_0, 0, 1; + %jmp T_15.5; +T_15.4 ; + %load/v 8, v0x1ea84c0_0, 5; + %mov 13, 0, 1; + %cmpi/u 8, 8, 6; + %jmp/0xz T_15.6, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea7f00_0, 0, 0; + %load/v 8, v0x1ea8560_0, 1; + %mov 9, 0, 1; + %cmpi/u 8, 0, 2; + %jmp/0xz T_15.8, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea8300_0, 0, 1; + %jmp T_15.9; +T_15.8 ; + %load/v 8, v0x1ea8560_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_15.10, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea8220_0, 0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea80f0_0, 0, 1; +T_15.10 ; +T_15.9 ; + %jmp T_15.7; +T_15.6 ; + %movi 8, 8, 6; + %load/v 14, v0x1ea84c0_0, 5; + %mov 19, 0, 1; + %cmp/u 8, 14, 6; + %jmp/0xz T_15.12, 5; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea7f00_0, 0, 0; + %load/v 8, v0x1ea84c0_0, 5; + %cmpi/u 8, 15, 5; + %jmp/0xz T_15.14, 4; + %ix/load 0, 5, 0; + %assign/v0 v0x1ea84c0_0, 0, 0; + %load/v 8, v0x1ea8300_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_15.16, 4; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea8040_0, 0, 1; +T_15.16 ; +T_15.14 ; +T_15.12 ; +T_15.7 ; +T_15.5 ; + %jmp T_15.3; +T_15.2 ; + %load/v 8, v0x1ea7fa0_0, 1; + %mov 9, 0, 2; + %cmpi/u 8, 1, 3; + %jmp/0xz T_15.18, 4; + %ix/load 0, 5, 0; + %assign/v0 v0x1ea84c0_0, 0, 0; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea8300_0, 0, 0; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea8040_0, 0, 0; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea7f00_0, 0, 0; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea8220_0, 0, 0; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea80f0_0, 0, 0; +T_15.18 ; +T_15.3 ; +T_15.0 ; + %jmp T_15; + .thread T_15; + .scope S_0x1ea78d0; +T_16 ; + %wait E_0x1e38510; + %load/v 8, v0x1ea7b20_0, 1; + %jmp/0xz T_16.0, 8; + %load/v 8, v0x1ea7a80_0, 1; + %ix/load 0, 1, 0; + %assign/v0 v0x1ea7bc0_0, 0, 8; +T_16.0 ; + %jmp T_16; + .thread T_16; + .scope S_0x1e3c720; +T_17 ; + %wait E_0x1e38510; + %load/v 8, v0x1ea77f0_0, 1; + %jmp/0xz T_17.0, 8; + %load/v 8, v0x1ea7620_0, 8; + %ix/getv 3, v0x1e4fc00_0; + %jmp/1 t_0, 4; + %ix/load 0, 8, 0; word width + %ix/load 1, 0, 0; part off + %assign/av v0x1ea7770, 0, 8; +t_0 ; +T_17.0 ; + %ix/getv 3, v0x1e4fc00_0; + %load/av 8, v0x1ea7770, 8; + %ix/load 0, 8, 0; + %assign/v0 v0x1ea76c0_0, 0, 8; + %jmp T_17; + .thread T_17; + .scope S_0x1e40190; +T_18 ; + %set/v v0x1eab860_0, 0, 1; + %end; + .thread T_18; + .scope S_0x1e40190; +T_19 ; + %delay 10000, 0; + %load/v 8, v0x1eab860_0, 1; + %inv 8, 1; + %set/v v0x1eab860_0, 8, 1; + %jmp T_19; + .thread T_19; + .scope S_0x1e40190; +T_20 ; + %vpi_call 2 18 "$dumpfile", "SPI.vcd"; + %vpi_call 2 19 "$dumpvars"; + %vpi_call 2 22 "$display", "CS_pin | sclk_pin | MOSI | MISO \011"; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 200000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 180000, 0; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 200000, 0; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 1, 1; + %delay 48000, 0; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 1, 1; + %delay 48000, 0; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 48000, 0; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 48000, 0; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 48000, 0; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 48000, 0; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 48000, 0; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 48000, 0; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 1, 1; + %delay 48000, 0; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 1, 1; + %delay 48000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 1, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 1, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 1, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 1, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 1, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 1, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 600000, 0; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 600000, 0; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 600000, 0; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 600000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 1, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 1, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 1, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 1, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 1, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 1, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 1, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 1, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 0, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 160000, 0; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 600000, 0; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 600000, 0; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 0, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 600000, 0; + %set/v v0x1eab8e0_0, 1, 1; + %set/v v0x1eabb30_0, 1, 1; + %set/v v0x1eaba60_0, 0, 1; + %delay 600000, 0; + %vpi_call 2 182 "$finish"; + %end; + .thread T_20; +# The file index is used to find the file name in the following table. +:file_names 8; + "N/A"; + ""; + "spimemory.t.v"; + "./spimemory.v"; + "./inputconditioner.v"; + "./shiftregister.v"; + "./FSM.v"; + "./datamemory.v";