diff --git a/Lab2.pdf b/Lab2.pdf
new file mode 100644
index 0000000..f46fa69
Binary files /dev/null and b/Lab2.pdf differ
diff --git a/ZYBO_Master.xdc b/ZYBO_Master.xdc
new file mode 100644
index 0000000..f3dbb71
--- /dev/null
+++ b/ZYBO_Master.xdc
@@ -0,0 +1,146 @@
+## This file is a general .xdc for the ZYBO Rev B board
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used signals according to the project
+
+
+##Clock signal
+set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L11P_T1_SRCC_35 Sch=sysclk
+#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];
+
+
+##Switches
+set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=SW0
+set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }];  #IO_L24P_T3_34 Sch=SW1
+set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=SW2
+set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=SW3
+
+
+##Buttons
+set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L20N_T3_34 Sch=BTN0
+set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=BTN1
+set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L18P_T2_34 Sch=BTN2
+set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=BTN3
+
+
+##LEDs
+set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=LED0
+set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=LED1
+set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35=Sch=LED2
+set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3
+
+
+##I2S Audio Codec
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports ac_bclk]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK
+#set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports ac_mclk]; #IO_25_34 Sch=AC_MCLK
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports ac_muten]; #IO_L23N_T3_34 Sch=AC_MUTEN
+#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports ac_pbdat]; #IO_L8P_T1_AD10P_35 Sch=AC_PBDAT
+#set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports ac_pblrc]; #IO_L11N_T1_SRCC_35 Sch=AC_PBLRC
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports ac_recdat]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports ac_reclrc]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC
+
+
+##Audio Codec/external EEPROM IIC bus
+#set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports ac_scl]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports ac_sda]; #IO_L23P_T3_34 Sch=AC_SDA
+
+
+##Additional Ethernet signals
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports eth_int_b]; #IO_L6P_T0_35 Sch=ETH_INT_B
+#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports eth_rst_b]; #IO_L3P_T0_DQS_AD1P_35 Sch=ETH_RST_B
+
+
+##HDMI Signals
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD TMDS_33 } [get_ports hdmi_clk_n]; #IO_L13N_T2_MRCC_35 Sch=HDMI_CLK_N
+#set_property -dict { PACKAGE_PIN H16   IOSTANDARD TMDS_33 } [get_ports hdmi_clk_p]; #IO_L13P_T2_MRCC_35 Sch=HDMI_CLK_P
+#set_property -dict { PACKAGE_PIN D20   IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[0] }]; #IO_L4N_T0_35 Sch=HDMI_D0_N
+#set_property -dict { PACKAGE_PIN D19   IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[0] }]; #IO_L4P_T0_35 Sch=HDMI_D0_P
+#set_property -dict { PACKAGE_PIN B20   IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=HDMI_D1_N
+#set_property -dict { PACKAGE_PIN C20   IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=HDMI_D1_P
+#set_property -dict { PACKAGE_PIN A20   IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=HDMI_D2_N
+#set_property -dict { PACKAGE_PIN B19   IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=HDMI_D2_P
+#set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports hdmi_cec]; #IO_L5N_T0_AD9N_35 Sch=HDMI_CEC
+#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports hdmi_hpd]; #IO_L5P_T0_AD9P_35 Sch=HDMI_HPD
+#set_property -dict { PACKAGE_PIN F17   IOSTANDARD LVCMOS33 } [get_ports hdmi_out_en]; #IO_L6N_T0_VREF_35 Sch=HDMI_OUT_EN
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports hdmi_scl]; #IO_L16P_T2_35 Sch=HDMI_SCL
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports hdmi_sda]; #IO_L16N_T2_35 Sch=HDMI_SDA
+
+
+##Pmod Header JA (XADC)
+#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { ja_p[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
+#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
+#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
+#set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P
+#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { ja_n[0] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N
+#set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N
+#set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N
+#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N
+
+
+##Pmod Header JB
+#set_property -dict { PACKAGE_PIN T20   IOSTANDARD LVCMOS33 } [get_ports { jb_p[0] }]; #IO_L15P_T2_DQS_34 Sch=JB1_p
+#set_property -dict { PACKAGE_PIN U20   IOSTANDARD LVCMOS33 } [get_ports { jb_n[0] }]; #IO_L15N_T2_DQS_34 Sch=JB1_N
+#set_property -dict { PACKAGE_PIN V20   IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L16P_T2_34 Sch=JB2_P
+#set_property -dict { PACKAGE_PIN W20   IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L16N_T2_34 Sch=JB2_N
+#set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L17P_T2_34 Sch=JB3_P
+#set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L17N_T2_34 Sch=JB3_N
+#set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L22P_T3_34 Sch=JB4_P
+#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L22N_T3_34 Sch=JB4_N
+
+
+##Pmod Header JC
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { jc_p[0] }]; #IO_L10P_T1_34 Sch=JC1_P
+#set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports { jc_n[0] }]; #IO_L10N_T1_34 Sch=JC1_N
+#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { jc_p[1] }]; #IO_L1P_T0_34 Sch=JC2_P
+#set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { jc_n[1] }]; #IO_L1N_T0_34 Sch=JC2_N
+#set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports { jc_p[2] }]; #IO_L8P_T1_34 Sch=JC3_P
+#set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS33 } [get_ports { jc_n[2] }]; #IO_L8N_T1_34 Sch=JC3_N
+#set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33 } [get_ports { jc_p[3] }]; #IO_L2P_T0_34 Sch=JC4_P
+#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { jc_n[3] }]; #IO_L2N_T0_34 Sch=JC4_N
+
+
+##Pmod Header JD
+#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { jd_p[0] }]; #IO_L5P_T0_34 Sch=JD1_P
+#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { jd_n[0] }]; #IO_L5N_T0_34 Sch=JD1_N
+#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { jd_p[1] }]; #IO_L6P_T0_34 Sch=JD2_P
+#set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33 } [get_ports { jd_n[1] }]; #IO_L6N_T0_VREF_34 Sch=JD2_N
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { jd_p[2] }]; #IO_L11P_T1_SRCC_34 Sch=JD3_P
+#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { jd_n[2] }]; #IO_L11N_T1_SRCC_34 Sch=JD3_N
+#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { jd_p[3] }]; #IO_L21P_T3_DQS_34 Sch=JD4_P
+#set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33 } [get_ports { jd_n[3] }]; #IO_L21N_T3_DQS_34 Sch=JD4_N
+
+
+##Pmod Header JE
+#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=JE1
+#set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=JE2
+#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=JE3
+#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=JE4
+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=JE7
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=JE8
+#set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=JE9
+#set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=JE10
+
+
+##USB-OTG overcurrent detect pin
+#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports otg_oc]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=OTG_OC
+
+
+##VGA Connector
+#set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L7P_T1_AD2P_35 Sch=VGA_R1
+#set_property -dict { PACKAGE_PIN L20   IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=VGA_R2
+#set_property -dict { PACKAGE_PIN J20   IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L17P_T2_AD5P_35 Sch=VGA_R3
+#set_property -dict { PACKAGE_PIN G20   IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L18N_T2_AD13N_35 Sch=VGA_R4
+#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_AD12P_35 Sch=VGA_R5
+#set_property -dict { PACKAGE_PIN H18   IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=VGA_G0
+#set_property -dict { PACKAGE_PIN N20   IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L14P_T2_SRCC_34 Sch=VGA_G1
+#set_property -dict { PACKAGE_PIN L19   IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=VGA_G2
+#set_property -dict { PACKAGE_PIN J19   IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L10N_T1_AD11N_35 Sch=VGA_G3
+#set_property -dict { PACKAGE_PIN H20   IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L17N_T2_AD5N_35 Sch=VGA_G4
+#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L15N_T2_DQS_AD12N_35 Sch=VGA=G5
+#set_property -dict { PACKAGE_PIN P20   IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L14N_T2_SRCC_34 Sch=VGA_B1
+#set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L7N_T1_AD2N_35 Sch=VGA_B2
+#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L10P_T1_AD11P_35 Sch=VGA_B3
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=VGA_B4
+#set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L18P_T2_AD13P_35 Sch=VGA_B5
+#set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports vga_hs]; #IO_L13N_T2_MRCC_34 Sch=VGA_HS
+#set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports vga_vs]; #IO_0_34 Sch=VGA_VS
diff --git a/datamemory.v b/datamemory.v
index 0d82131..02225af 100644
--- a/datamemory.v
+++ b/datamemory.v
@@ -17,7 +17,7 @@ module datamemory
     input [addresswidth-1:0]    address,
     input                       writeEnable,
     input [width-1:0]           dataIn
-)
+);
 
 
     reg [width-1:0] memory [depth-1:0];
diff --git a/input b/input
new file mode 100755
index 0000000..b481dd3
--- /dev/null
+++ b/input
@@ -0,0 +1,269 @@
+#! /usr/local/bin/vvp
+:ivl_version "0.10.0 (devel)" "(s20150513)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "system";
+:vpi_module "vhdl_sys";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x17656b0 .scope module, "testConditioner" "testConditioner" 2 6;
+ .timescale 0 0;
+v0x178a580_0 .var "clk", 0 0;
+v0x178a670_0 .net "conditioned", 0 0, v0x1789f20_0;  1 drivers
+v0x178a740_0 .var "dutpassed", 0 0;
+v0x178a810_0 .net "falling", 0 0, v0x178a0d0_0;  1 drivers
+v0x178a8e0_0 .var "i", 31 0;
+v0x178a9d0_0 .var "pin", 0 0;
+v0x178aa70_0 .net "rising", 0 0, v0x178a2a0_0;  1 drivers
+v0x178ab40_0 .var "shouldChange", 0 0;
+E_0x176a070 .event negedge, v0x1789f20_0;
+E_0x176a4f0 .event posedge, v0x1789f20_0;
+E_0x176a330 .event edge, v0x1789f20_0;
+S_0x1765830 .scope module, "dut" "inputconditioner" 2 17, 3 8 0, S_0x17656b0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk"
+    .port_info 1 /INPUT 1 "noisysignal"
+    .port_info 2 /OUTPUT 1 "conditioned"
+    .port_info 3 /OUTPUT 1 "positiveedge"
+    .port_info 4 /OUTPUT 1 "negativeedge"
+P_0x1766600 .param/l "counterwidth" 0 3 17, +C4<00000000000000000000000000000011>;
+P_0x1766640 .param/l "waittime" 0 3 18, +C4<00000000000000000000000000000011>;
+v0x1769930_0 .net "clk", 0 0, v0x178a580_0;  1 drivers
+v0x1789f20_0 .var "conditioned", 0 0;
+v0x1789fe0_0 .var "counter", 2 0;
+v0x178a0d0_0 .var "negativeedge", 0 0;
+v0x178a190_0 .net "noisysignal", 0 0, v0x178a9d0_0;  1 drivers
+v0x178a2a0_0 .var "positiveedge", 0 0;
+v0x178a360_0 .var "synchronizer0", 0 0;
+v0x178a420_0 .var "synchronizer1", 0 0;
+E_0x1769f70 .event posedge, v0x1769930_0;
+    .scope S_0x1765830;
+T_0 ;
+    %pushi/vec4 0, 0, 3;
+    %store/vec4 v0x1789fe0_0, 0, 3;
+    %end;
+    .thread T_0;
+    .scope S_0x1765830;
+T_1 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x178a360_0, 0, 1;
+    %end;
+    .thread T_1;
+    .scope S_0x1765830;
+T_2 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x178a420_0, 0, 1;
+    %end;
+    .thread T_2;
+    .scope S_0x1765830;
+T_3 ;
+    %wait E_0x1769f70;
+    %load/vec4 v0x1789f20_0;
+    %load/vec4 v0x178a420_0;
+    %cmp/e;
+    %jmp/0xz  T_3.0, 4;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0x1789fe0_0, 0;
+    %jmp T_3.1;
+T_3.0 ;
+    %load/vec4 v0x1789fe0_0;
+    %pad/u 32;
+    %cmpi/e 3, 0, 32;
+    %jmp/0xz  T_3.2, 4;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0x1789fe0_0, 0;
+    %load/vec4 v0x178a420_0;
+    %assign/vec4 v0x1789f20_0, 0;
+    %load/vec4 v0x1789f20_0;
+    %inv;
+    %load/vec4 v0x178a420_0;
+    %and;
+    %assign/vec4 v0x178a2a0_0, 0;
+    %load/vec4 v0x178a420_0;
+    %inv;
+    %load/vec4 v0x1789f20_0;
+    %and;
+    %assign/vec4 v0x178a0d0_0, 0;
+    %jmp T_3.3;
+T_3.2 ;
+    %load/vec4 v0x1789fe0_0;
+    %addi 1, 0, 3;
+    %assign/vec4 v0x1789fe0_0, 0;
+T_3.3 ;
+T_3.1 ;
+    %load/vec4 v0x178a2a0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_3.4, 8;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0x178a2a0_0, 0;
+T_3.4 ;
+    %load/vec4 v0x178a0d0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_3.6, 8;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0x178a0d0_0, 0;
+T_3.6 ;
+    %load/vec4 v0x178a190_0;
+    %assign/vec4 v0x178a360_0, 0;
+    %load/vec4 v0x178a360_0;
+    %assign/vec4 v0x178a420_0, 0;
+    %jmp T_3;
+    .thread T_3;
+    .scope S_0x17656b0;
+T_4 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x178a580_0, 0, 1;
+    %end;
+    .thread T_4;
+    .scope S_0x17656b0;
+T_5 ;
+    %delay 10, 0;
+    %load/vec4 v0x178a580_0;
+    %nor/r;
+    %store/vec4 v0x178a580_0, 0, 1;
+    %jmp T_5;
+    .thread T_5;
+    .scope S_0x17656b0;
+T_6 ;
+    %wait E_0x176a330;
+    %vpi_func 2 28 "$time" 64 {0 0 0};
+    %pushi/vec4 20, 0, 64;
+    %mod;
+    %cmpi/ne 10, 0, 64;
+    %jmp/0xz  T_6.0, 4;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x178a740_0, 0, 1;
+    %vpi_call 2 31 "$display", "synchronization failed %d", $time {0 0 0};
+T_6.0 ;
+    %load/vec4 v0x178ab40_0;
+    %nor/r;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_6.2, 8;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x178a740_0, 0, 1;
+    %vpi_call 2 35 "$display", "output changed too early on debounce test" {0 0 0};
+T_6.2 ;
+    %jmp T_6;
+    .thread T_6, $push;
+    .scope S_0x17656b0;
+T_7 ;
+    %wait E_0x176a4f0;
+    %delay 1, 0;
+    %load/vec4 v0x178aa70_0;
+    %nor/r;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_7.0, 8;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x178a740_0, 0, 1;
+    %vpi_call 2 44 "$display", "positive edge missed" {0 0 0};
+T_7.0 ;
+    %delay 20, 0;
+    %load/vec4 v0x178aa70_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_7.2, 8;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x178a740_0, 0, 1;
+    %vpi_call 2 49 "$display", "positive edge pulsed too long" {0 0 0};
+T_7.2 ;
+    %jmp T_7;
+    .thread T_7;
+    .scope S_0x17656b0;
+T_8 ;
+    %wait E_0x176a070;
+    %delay 1, 0;
+    %load/vec4 v0x178a810_0;
+    %nor/r;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_8.0, 8;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x178a740_0, 0, 1;
+    %vpi_call 2 57 "$display", "negative edge missed" {0 0 0};
+T_8.0 ;
+    %delay 20, 0;
+    %load/vec4 v0x178aa70_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_8.2, 8;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x178a740_0, 0, 1;
+    %vpi_call 2 62 "$display", "negative edge pulsed too long" {0 0 0};
+T_8.2 ;
+    %jmp T_8;
+    .thread T_8;
+    .scope S_0x17656b0;
+T_9 ;
+    %vpi_call 2 67 "$dumpfile", "inputconditioner.vcd" {0 0 0};
+    %vpi_call 2 68 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x17656b0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x178a740_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x178ab40_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x178a9d0_0, 0, 1;
+    %delay 200, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x178a9d0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x178a9d0_0, 0, 1;
+    %delay 200, 0;
+    %load/vec4 v0x178a670_0;
+    %pad/u 32;
+    %cmpi/ne 1, 0, 32;
+    %jmp/0xz  T_9.0, 4;
+    %vpi_call 2 76 "$display", "output did not change on on synchronization test" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x178a740_0, 0, 1;
+T_9.0 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x178a9d0_0, 0, 1;
+    %delay 200, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x178ab40_0, 0, 1;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x178a8e0_0, 0, 32;
+T_9.2 ;
+    %load/vec4 v0x178a8e0_0;
+    %cmpi/u 4, 0, 32;
+    %jmp/0xz T_9.3, 5;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x178a9d0_0, 0, 1;
+    %delay 7, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x178a9d0_0, 0, 1;
+    %delay 3, 0;
+    %load/vec4 v0x178a8e0_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0x178a8e0_0, 0, 32;
+    %jmp T_9.2;
+T_9.3 ;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x178ab40_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x178a9d0_0, 0, 1;
+    %delay 300, 0;
+    %load/vec4 v0x178a670_0;
+    %pad/u 32;
+    %cmpi/ne 1, 0, 32;
+    %jmp/0xz  T_9.4, 4;
+    %vpi_call 2 89 "$display", "output did not change on on debounce test" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x178a740_0, 0, 1;
+T_9.4 ;
+    %load/vec4 v0x178a740_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_9.6, 8;
+    %vpi_call 2 94 "$display", "DUT passed" {0 0 0};
+    %jmp T_9.7;
+T_9.6 ;
+    %vpi_call 2 97 "$display", "DUT failed" {0 0 0};
+T_9.7 ;
+    %delay 100, 0;
+    %vpi_call 2 101 "$finish" {0 0 0};
+    %end;
+    .thread T_9;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "inputconditioner.t.v";
+    "./inputconditioner.v";
diff --git a/inputconditioner.t.v b/inputconditioner.t.v
index 2814163..e0879ba 100644
--- a/inputconditioner.t.v
+++ b/inputconditioner.t.v
@@ -1,6 +1,7 @@
 //------------------------------------------------------------------------
 // Input Conditioner test bench
 //------------------------------------------------------------------------
+`include "inputconditioner.v"
 
 module testConditioner();
 
@@ -9,21 +10,94 @@ module testConditioner();
     wire conditioned;
     wire rising;
     wire falling;
-    
+    reg  dutpassed;
+    reg  shouldChange;
+    reg[31:0] i;
+
     inputconditioner dut(.clk(clk),
     			 .noisysignal(pin),
 			 .conditioned(conditioned),
 			 .positiveedge(rising),
-			 .negativeedge(falling))
-
+			 .negativeedge(falling));
 
     // Generate clock (50MHz)
-    initial clk=0;
+    initial clk = 0;
     always #10 clk=!clk;    // 50MHz Clock
+
+    always @ (conditioned) begin
+      if($time%20 != 10) begin
+        //synchronization test
+        dutpassed = 0;
+        $display("synchronization failed %d",$time);
+      end
+      if(!shouldChange) begin
+        dutpassed = 0;
+        $display("output changed too early on debounce test");
+      end
+    end
     
+    //edge detection
+    always @(posedge conditioned) begin
+      #1;
+      if(!rising) begin
+        dutpassed = 0;
+        $display("positive edge missed");
+      end
+      #20;
+      if(rising) begin
+        dutpassed = 0;
+        $display("positive edge pulsed too long");
+      end
+    end
+
+    always @(negedge conditioned) begin
+      #1;
+      if(!falling) begin
+        dutpassed = 0;
+        $display("negative edge missed");
+      end
+      #20;
+      if(rising) begin
+        dutpassed = 0;
+        $display("negative edge pulsed too long");
+      end
+    end
+
     initial begin
-    // Your Test Code
-    // Be sure to test each of the three conditioner functions:
-    // Synchronization, Debouncing, Edge Detection
-    
+    $dumpfile("inputconditioner.vcd");
+    $dumpvars(0, testConditioner);
+    dutpassed = 1;
+    shouldChange = 1;
+    pin = 0; #200;
+    // Synchronization:
+    pin = 0; #5;
+    pin = 1; #200;
+    if(conditioned != 1) begin
+      $display("output did not change on on synchronization test");
+      dutpassed = 0;
+    end
+    pin = 0; #200;
+    //Debounces
+    shouldChange = 0;
+    for(i = 0; i<4; i = i + 1) begin
+      pin = 1; #7;
+      pin = 0; #3;
+    end
+    shouldChange = 1;
+    pin = 1; #300;
+    if(conditioned != 1) begin
+      $display("output did not change on on debounce test");
+      dutpassed = 0;
+    end
+
+    if(dutpassed) begin
+      $display("DUT passed");
+    end
+    else begin
+      $display("DUT failed");
+    end
+
+    #100;
+    $finish();
+    end
 endmodule
diff --git a/inputconditioner.v b/inputconditioner.v
index 736a866..60c80d8 100644
--- a/inputconditioner.v
+++ b/inputconditioner.v
@@ -16,22 +16,32 @@ output reg  negativeedge    // 1 clk pulse at falling edge of conditioned
 
     parameter counterwidth = 3; // Counter size, in bits, >= log2(waittime)
     parameter waittime = 3;     // Debounce delay, in clock cycles
-    
+
     reg[counterwidth-1:0] counter = 0;
     reg synchronizer0 = 0;
     reg synchronizer1 = 0;
-    
+
     always @(posedge clk ) begin
         if(conditioned == synchronizer1)
             counter <= 0;
         else begin
             if( counter == waittime) begin
                 counter <= 0;
-                conditioned <= synchronizer1;
+                conditioned  <= synchronizer1;
+                positiveedge <= (~conditioned)   & synchronizer1;
+                negativeedge <= (~synchronizer1) & conditioned;
             end
-            else 
+            else
                 counter <= counter+1;
         end
+
+        if(positiveedge) begin
+            positiveedge <= 0;
+        end
+        if(negativeedge) begin
+            negativeedge <= 0;
+        end
+
         synchronizer0 <= noisysignal;
         synchronizer1 <= synchronizer0;
     end
diff --git a/inputconditioner.vcd b/inputconditioner.vcd
new file mode 100644
index 0000000..a3d1f32
--- /dev/null
+++ b/inputconditioner.vcd
@@ -0,0 +1,316 @@
+$date
+	Mon Oct 23 16:35:11 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module testConditioner $end
+$var wire 1 ! rising $end
+$var wire 1 " falling $end
+$var wire 1 # conditioned $end
+$var reg 1 $ clk $end
+$var reg 1 % dutpassed $end
+$var reg 32 & i [31:0] $end
+$var reg 1 ' pin $end
+$var reg 1 ( shouldChange $end
+$scope module dut $end
+$var wire 1 $ clk $end
+$var wire 1 ' noisysignal $end
+$var reg 1 # conditioned $end
+$var reg 3 ) counter [2:0] $end
+$var reg 1 " negativeedge $end
+$var reg 1 ! positiveedge $end
+$var reg 1 * synchronizer0 $end
+$var reg 1 + synchronizer1 $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+0+
+0*
+b0 )
+1(
+0'
+bx &
+1%
+0$
+x#
+x"
+x!
+$end
+#10
+b1 )
+1$
+#20
+0$
+#30
+b10 )
+1$
+#40
+0$
+#50
+b11 )
+1$
+#60
+0$
+#70
+0!
+0#
+b0 )
+1$
+#80
+0$
+#90
+1$
+#100
+0$
+#110
+1$
+#120
+0$
+#130
+1$
+#140
+0$
+#150
+1$
+#160
+0$
+#170
+1$
+#180
+0$
+#190
+1$
+#200
+0$
+#205
+1'
+#210
+1*
+1$
+#220
+0$
+#230
+1+
+1$
+#240
+0$
+#250
+b1 )
+1$
+#260
+0$
+#270
+b10 )
+1$
+#280
+0$
+#290
+b11 )
+1$
+#300
+0$
+#310
+0"
+1!
+1#
+b0 )
+1$
+#320
+0$
+#330
+0!
+1$
+#340
+0$
+#350
+1$
+#360
+0$
+#370
+1$
+#380
+0$
+#390
+1$
+#400
+0$
+#405
+0'
+#410
+0*
+1$
+#420
+0$
+#430
+0+
+1$
+#440
+0$
+#450
+b1 )
+1$
+#460
+0$
+#470
+b10 )
+1$
+#480
+0$
+#490
+b11 )
+1$
+#500
+0$
+#510
+1"
+0#
+b0 )
+1$
+#520
+0$
+#530
+0"
+1$
+#540
+0$
+#550
+1$
+#560
+0$
+#570
+1$
+#580
+0$
+#590
+1$
+#600
+0$
+#605
+1'
+b0 &
+0(
+#610
+1*
+1$
+#612
+0'
+#615
+1'
+b1 &
+#620
+0$
+#622
+0'
+#625
+1'
+b10 &
+#630
+1+
+1$
+#632
+0'
+#635
+1'
+b11 &
+#640
+0$
+#642
+0'
+#645
+1'
+1(
+b100 &
+#650
+b1 )
+1$
+#660
+0$
+#670
+b10 )
+1$
+#680
+0$
+#690
+b11 )
+1$
+#700
+0$
+#710
+1!
+1#
+b0 )
+1$
+#720
+0$
+#730
+0!
+1$
+#740
+0$
+#750
+1$
+#760
+0$
+#770
+1$
+#780
+0$
+#790
+1$
+#800
+0$
+#810
+1$
+#820
+0$
+#830
+1$
+#840
+0$
+#850
+1$
+#860
+0$
+#870
+1$
+#880
+0$
+#890
+1$
+#900
+0$
+#910
+1$
+#920
+0$
+#930
+1$
+#940
+0$
+#950
+1$
+#960
+0$
+#970
+1$
+#980
+0$
+#990
+1$
+#1000
+0$
+#1010
+1$
+#1020
+0$
+#1030
+1$
+#1040
+0$
+#1045
diff --git a/midpoint.v b/midpoint.v
new file mode 100644
index 0000000..0bcc955
--- /dev/null
+++ b/midpoint.v
@@ -0,0 +1,34 @@
+`include "shiftregister.v"
+`include "inputconditioner.v"
+module midpoint_wrapper
+(
+   input clk,
+   input [3:0] sw,
+   input [3:0] btn,
+   output [3:0] led
+   );
+
+  wire par_load;
+   wire ser_in;
+   wire clk_edge;
+   wire [7:0] par_data_in;
+   wire [7:0] par_data_out;
+   reg [3:0]      ledmem;
+   
+   inputconditioner btn_cond(.clk(clk),.noisysignal(btn[0]),.negativeedge(par_load));
+   inputconditioner sw0_cond(.clk(clk),.noisysignal(sw[0]),.conditioned(ser_in));
+   inputconditioner sw1_cond(.clk(clk),.noisysignal(sw[1]),.positiveedge(clk_edge));
+
+   assign par_data_in = 8'hA5;
+
+   shiftregister shftreg(.clk(clk),.peripheralClkEdge(clk_edge),.parallelLoad(par_load),.parallelDataIn(par_data_in),.serialDataIn(ser_in),.parallelDataOut(par_data_out));
+
+   always @(posedge clk)begin
+      if(sw[3])
+	   ledmem = par_data_out[7:4];
+      else begin
+	   ledmem = par_data_out[3:0];
+      end
+   end
+   assign led=ledmem;
+endmodule
diff --git a/shift b/shift
new file mode 100755
index 0000000..cc2e75d
--- /dev/null
+++ b/shift
@@ -0,0 +1,280 @@
+#! /usr/local/bin/vvp
+:ivl_version "0.10.0 (devel)" "(s20150513)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "system";
+:vpi_module "vhdl_sys";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x18e7c60 .scope module, "testshiftregister" "testshiftregister" 2 6;
+ .timescale 0 0;
+v0x19301e0_0 .var "clk", 0 0;
+v0x19302a0_0 .var "dutpassed", 0 0;
+v0x1930340_0 .var "parallelDataIn", 7 0;
+v0x1930440_0 .net "parallelDataOut", 7 0, L_0x1930870;  1 drivers
+v0x1930510_0 .var "parallelLoad", 0 0;
+v0x1930600_0 .var "peripheralClkEdge", 0 0;
+v0x19306d0_0 .var "serialDataIn", 0 0;
+v0x19307a0_0 .net "serialDataOut", 0 0, L_0x1930930;  1 drivers
+S_0x190c880 .scope module, "dut" "shiftregister" 2 17, 3 9 0, S_0x18e7c60;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk"
+    .port_info 1 /INPUT 1 "peripheralClkEdge"
+    .port_info 2 /INPUT 1 "parallelLoad"
+    .port_info 3 /INPUT 8 "parallelDataIn"
+    .port_info 4 /INPUT 1 "serialDataIn"
+    .port_info 5 /OUTPUT 8 "parallelDataOut"
+    .port_info 6 /OUTPUT 1 "serialDataOut"
+P_0x190ca50 .param/l "width" 0 3 10, +C4<00000000000000000000000000001000>;
+L_0x1930870 .functor BUFZ 8, v0x192ffe0_0, C4<00000000>, C4<00000000>, C4<00000000>;
+v0x190caf0_0 .net "clk", 0 0, v0x19301e0_0;  1 drivers
+v0x192fac0_0 .net "parallelDataIn", 7 0, v0x1930340_0;  1 drivers
+v0x192fba0_0 .net "parallelDataOut", 7 0, L_0x1930870;  alias, 1 drivers
+v0x192fc90_0 .net "parallelLoad", 0 0, v0x1930510_0;  1 drivers
+v0x192fd50_0 .net "peripheralClkEdge", 0 0, v0x1930600_0;  1 drivers
+v0x192fe60_0 .net "serialDataIn", 0 0, v0x19306d0_0;  1 drivers
+v0x192ff20_0 .net "serialDataOut", 0 0, L_0x1930930;  alias, 1 drivers
+v0x192ffe0_0 .var "shiftregistermem", 7 0;
+E_0x190deb0 .event posedge, v0x190caf0_0;
+L_0x1930930 .part v0x192ffe0_0, 7, 1;
+    .scope S_0x190c880;
+T_0 ;
+    %wait E_0x190deb0;
+    %load/vec4 v0x192fc90_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_0.0, 8;
+    %load/vec4 v0x192fac0_0;
+    %assign/vec4 v0x192ffe0_0, 0;
+    %jmp T_0.1;
+T_0.0 ;
+    %load/vec4 v0x192fd50_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_0.2, 8;
+    %load/vec4 v0x192ffe0_0;
+    %parti/s 7, 0, 2;
+    %load/vec4 v0x192fe60_0;
+    %concat/vec4; draw_concat_vec4
+    %assign/vec4 v0x192ffe0_0, 0;
+T_0.2 ;
+T_0.1 ;
+    %jmp T_0;
+    .thread T_0;
+    .scope S_0x18e7c60;
+T_1 ;
+    %vpi_call 2 27 "$dumpfile", "shift.vcd" {0 0 0};
+    %vpi_call 2 28 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x18e7c60 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x19302a0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1930600_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 0, 0, 8;
+    %store/vec4 v0x1930340_0, 0, 8;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1930510_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %load/vec4 v0x1930440_0;
+    %cmpi/ne 0, 0, 8;
+    %flag_mov 8, 4;
+    %load/vec4 v0x1930440_0;
+    %xor/r;
+    %cmpi/e 1, 1, 1;
+    %flag_or 6, 8;
+    %jmp/0xz  T_1.0, 6;
+    %vpi_call 2 38 "$display", "initialization failed, parallel" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19302a0_0, 0, 1;
+T_1.0 ;
+    %load/vec4 v0x19307a0_0;
+    %pad/u 32;
+    %cmpi/ne 0, 0, 32;
+    %flag_mov 8, 4;
+    %load/vec4 v0x19307a0_0;
+    %cmpi/e 1, 1, 1;
+    %flag_or 6, 8;
+    %jmp/0xz  T_1.2, 6;
+    %vpi_call 2 42 "$display", "initialization failed, serial" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19302a0_0, 0, 1;
+T_1.2 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1930510_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x19306d0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x19306d0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19306d0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19306d0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x19306d0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19306d0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x19306d0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19306d0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %load/vec4 v0x1930440_0;
+    %cmpi/ne 202, 0, 8;
+    %flag_mov 8, 4;
+    %load/vec4 v0x1930440_0;
+    %xor/r;
+    %cmpi/e 1, 1, 1;
+    %flag_or 6, 8;
+    %jmp/0xz  T_1.4, 6;
+    %vpi_call 2 65 "$display", "Serial in failed, parallel" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19302a0_0, 0, 1;
+T_1.4 ;
+    %load/vec4 v0x19307a0_0;
+    %pad/u 32;
+    %cmpi/ne 1, 0, 32;
+    %flag_mov 8, 4;
+    %load/vec4 v0x19307a0_0;
+    %cmpi/e 1, 1, 1;
+    %flag_or 6, 8;
+    %jmp/0xz  T_1.6, 6;
+    %vpi_call 2 69 "$display", "Serial in failed, serial" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19302a0_0, 0, 1;
+T_1.6 ;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1930510_0, 0, 1;
+    %pushi/vec4 83, 0, 8;
+    %store/vec4 v0x1930340_0, 0, 8;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %load/vec4 v0x1930440_0;
+    %cmpi/ne 83, 0, 8;
+    %flag_mov 8, 4;
+    %load/vec4 v0x1930440_0;
+    %xor/r;
+    %cmpi/e 1, 1, 1;
+    %flag_or 6, 8;
+    %jmp/0xz  T_1.8, 6;
+    %vpi_call 2 78 "$display", "Parallel in failed, parallel" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19302a0_0, 0, 1;
+T_1.8 ;
+    %load/vec4 v0x19307a0_0;
+    %pad/u 32;
+    %cmpi/ne 0, 0, 32;
+    %flag_mov 8, 4;
+    %load/vec4 v0x19307a0_0;
+    %cmpi/e 1, 1, 1;
+    %flag_or 6, 8;
+    %jmp/0xz  T_1.10, 6;
+    %vpi_call 2 82 "$display", "Parallel in failed, serial" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19302a0_0, 0, 1;
+T_1.10 ;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1930510_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19306d0_0, 0, 1;
+    %pushi/vec4 255, 0, 8;
+    %store/vec4 v0x1930340_0, 0, 8;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19301e0_0, 0, 1;
+    %delay 5, 0;
+    %load/vec4 v0x1930440_0;
+    %cmpi/ne 255, 0, 8;
+    %flag_mov 8, 4;
+    %load/vec4 v0x1930440_0;
+    %xor/r;
+    %cmpi/e 1, 1, 1;
+    %flag_or 6, 8;
+    %jmp/0xz  T_1.12, 6;
+    %vpi_call 2 92 "$display", "Same time in failed, parallel" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19302a0_0, 0, 1;
+T_1.12 ;
+    %load/vec4 v0x19307a0_0;
+    %pad/u 32;
+    %cmpi/ne 1, 0, 32;
+    %flag_mov 8, 4;
+    %load/vec4 v0x19307a0_0;
+    %cmpi/e 1, 1, 1;
+    %flag_or 6, 8;
+    %jmp/0xz  T_1.14, 6;
+    %vpi_call 2 96 "$display", "Same time in failed, serial" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x19302a0_0, 0, 1;
+T_1.14 ;
+    %load/vec4 v0x19302a0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.16, 8;
+    %vpi_call 2 101 "$display", "DUT passed!" {0 0 0};
+T_1.16 ;
+    %vpi_call 2 103 "$finish" {0 0 0};
+    %end;
+    .thread T_1;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "shiftregister.t.v";
+    "./shiftregister.v";
diff --git a/shift.vcd b/shift.vcd
new file mode 100644
index 0000000..4149b41
--- /dev/null
+++ b/shift.vcd
@@ -0,0 +1,141 @@
+$date
+	Wed Oct 25 16:44:59 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module testshiftregister $end
+$var wire 1 ! serialDataOut $end
+$var wire 8 " parallelDataOut [7:0] $end
+$var reg 1 # clk $end
+$var reg 1 $ dutpassed $end
+$var reg 8 % parallelDataIn [7:0] $end
+$var reg 1 & parallelLoad $end
+$var reg 1 ' peripheralClkEdge $end
+$var reg 1 ( serialDataIn $end
+$scope module dut $end
+$var wire 1 # clk $end
+$var wire 8 ) parallelDataIn [7:0] $end
+$var wire 8 * parallelDataOut [7:0] $end
+$var wire 1 & parallelLoad $end
+$var wire 1 ' peripheralClkEdge $end
+$var wire 1 ( serialDataIn $end
+$var wire 1 ! serialDataOut $end
+$var reg 8 + shiftregistermem [7:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+bx +
+bx *
+bx )
+x(
+1'
+x&
+bx %
+1$
+0#
+bx "
+x!
+$end
+#5
+0!
+b0 "
+b0 *
+b0 +
+1#
+1&
+b0 %
+b0 )
+#10
+0#
+#15
+b1 "
+b1 *
+b1 +
+1#
+1(
+0&
+#20
+0#
+#25
+b11 "
+b11 *
+b11 +
+1#
+#30
+0#
+#35
+b110 "
+b110 *
+b110 +
+1#
+0(
+#40
+0#
+#45
+b1100 "
+b1100 *
+b1100 +
+1#
+#50
+0#
+#55
+b11001 "
+b11001 *
+b11001 +
+1#
+1(
+#60
+0#
+#65
+b110010 "
+b110010 *
+b110010 +
+1#
+0(
+#70
+0#
+#75
+b1100101 "
+b1100101 *
+b1100101 +
+1#
+1(
+#80
+0#
+#85
+1!
+b11001010 "
+b11001010 *
+b11001010 +
+1#
+0(
+#90
+0#
+#95
+0!
+b1010011 "
+b1010011 *
+b1010011 +
+1#
+b1010011 %
+b1010011 )
+1&
+#100
+0#
+#105
+1!
+b11111111 "
+b11111111 *
+b11111111 +
+1#
+b11111111 %
+b11111111 )
+#110
+0#
+#115
diff --git a/shiftregister.t.v b/shiftregister.t.v
index abe5b48..0fabc0c 100644
--- a/shiftregister.t.v
+++ b/shiftregister.t.v
@@ -1,3 +1,4 @@
+`include "shiftregister.v"
 //------------------------------------------------------------------------
 // Shift Register test bench
 //------------------------------------------------------------------------
@@ -10,20 +11,95 @@ module testshiftregister();
     wire[7:0]       parallelDataOut;
     wire            serialDataOut;
     reg[7:0]        parallelDataIn;
-    reg             serialDataIn; 
-    
+    reg             serialDataIn;
+
     // Instantiate with parameter width = 8
-    shiftregister #(8) dut(.clk(clk), 
+    shiftregister #(8) dut(.clk(clk),
     		           .peripheralClkEdge(peripheralClkEdge),
-    		           .parallelLoad(parallelLoad), 
-    		           .parallelDataIn(parallelDataIn), 
-    		           .serialDataIn(serialDataIn), 
-    		           .parallelDataOut(parallelDataOut), 
+    		           .parallelLoad(parallelLoad),
+    		           .parallelDataIn(parallelDataIn),
+    		           .serialDataIn(serialDataIn),
+    		           .parallelDataOut(parallelDataOut),
     		           .serialDataOut(serialDataOut));
-    
+    reg dutpassed;
+
     initial begin
-    	// Your Test Code
-    end
+      $dumpfile("shift.vcd");
+      $dumpvars(0, testshiftregister);
+      //initialize
+      dutpassed = 1;
+      peripheralClkEdge = 1;
+      clk = 0; #5;
+    	parallelDataIn = 8'd0;
+      parallelLoad   = 1;
+      clk = 1; #5;
+      clk = 0; #5;
+      if(parallelDataOut != 8'd0 || ^parallelDataOut === 1'bx) begin
+          $display("initialization failed, parallel");
+          dutpassed = 0;
+      end
+      if(serialDataOut != 0 || serialDataOut === 1'bx) begin
+          $display("initialization failed, serial");
+          dutpassed = 0;
+      end
 
-endmodule
+      //serialLoad some bits
+      parallelLoad = 0;
+      serialDataIn = 1;
+      clk = 1; #5; clk = 0; #5;
+      serialDataIn = 1;
+      clk = 1; #5; clk = 0; #5;
+      serialDataIn = 0;
+      clk = 1; #5; clk = 0; #5;
+      serialDataIn = 0;
+      clk = 1; #5; clk = 0; #5;
+      serialDataIn = 1;
+      clk = 1; #5; clk = 0; #5;
+      serialDataIn = 0;
+      clk = 1; #5; clk = 0; #5;
+      serialDataIn = 1;
+      clk = 1; #5; clk = 0; #5;
+      serialDataIn = 0;
+      clk = 1; #5; clk = 0; #5;
+      if(parallelDataOut != 8'b11001010 || ^parallelDataOut === 1'bx) begin
+          $display("Serial in failed, parallel");
+          dutpassed = 0;
+      end
+      if(serialDataOut != 1 || serialDataOut === 1'bx) begin
+          $display("Serial in failed, serial");
+          dutpassed = 0;
+      end
 
+      //parallelLoad some bits
+      parallelLoad = 1;
+      parallelDataIn = 8'b01010011;
+      clk = 1; #5; clk = 0; #5;
+      if(parallelDataOut != 8'b01010011 || ^parallelDataOut === 1'bx) begin
+          $display("Parallel in failed, parallel");
+          dutpassed = 0;
+      end
+      if(serialDataOut != 0 || serialDataOut === 1'bx) begin
+          $display("Parallel in failed, serial");
+          dutpassed = 0;
+      end
+
+      //parallel and serial at the same time
+      parallelLoad = 1;
+      serialDataIn = 0;
+      parallelDataIn = 8'b11111111;
+      clk = 1; #5; clk = 0; #5;
+      if(parallelDataOut != 8'b11111111 || ^parallelDataOut === 1'bx) begin
+          $display("Same time in failed, parallel");
+          dutpassed = 0;
+      end
+      if(serialDataOut != 1 || serialDataOut === 1'bx) begin
+          $display("Same time in failed, serial");
+          dutpassed = 0;
+      end
+
+      if(dutpassed) begin
+          $display("DUT passed!");
+      end
+      $finish();
+    end
+endmodule
diff --git a/shiftregister.v b/shiftregister.v
index b4ec057..e10129a 100644
--- a/shiftregister.v
+++ b/shiftregister.v
@@ -20,6 +20,14 @@ output              serialDataOut       // Positive edge synchronized
 
     reg [width-1:0]      shiftregistermem;
     always @(posedge clk) begin
-        // Your Code Here
+      if(parallelLoad) begin
+        shiftregistermem <= parallelDataIn;
+      end
+      else if(peripheralClkEdge) begin
+      	shiftregistermem <= {shiftregistermem[width-2:0],serialDataIn};
+      end
     end
+
+    assign parallelDataOut = shiftregistermem;
+    assign serialDataOut   = shiftregistermem[width-1];
 endmodule
diff --git a/spimem b/spimem
new file mode 100755
index 0000000..e0a4ea3
--- /dev/null
+++ b/spimem
@@ -0,0 +1,687 @@
+#! /usr/local/bin/vvp
+:ivl_version "0.10.0 (devel)" "(s20150513)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "system";
+:vpi_module "vhdl_sys";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x1b0ab00 .scope module, "testMemory" "testMemory" 2 6;
+ .timescale 0 0;
+v0x1b48860_0 .var "address", 6 0;
+v0x1b48960_0 .var "clk", 0 0;
+v0x1b48a20_0 .var "cs_pin", 0 0;
+v0x1b48b10_0 .var "data", 7 0;
+v0x1b48bb0_0 .var "dutpassed", 0 0;
+v0x1b48cc0_0 .var "i", 31 0;
+v0x1b48da0_0 .net "miso_pin", 0 0, v0x1b480a0_0;  1 drivers
+v0x1b48e40_0 .var "mosi_pin", 0 0;
+v0x1b48f30_0 .var "sclk_pin", 0 0;
+E_0x1b17e60 .event negedge, v0x1b48bb0_0;
+S_0x1b0ac80 .scope module, "dut" "spiMemory" 2 18, 3 12 0, S_0x1b0ab00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk"
+    .port_info 1 /INPUT 1 "sclk_pin"
+    .port_info 2 /INPUT 1 "cs_pin"
+    .port_info 3 /OUTPUT 1 "miso_pin"
+    .port_info 4 /INPUT 1 "mosi_pin"
+    .port_info 5 /OUTPUT 4 "leds"
+v0x1b478d0_0 .var "addressReg", 6 0;
+v0x1b479e0_0 .var "bitsTx", 4 0;
+v0x1b47aa0_0 .net "clk", 0 0, v0x1b48960_0;  1 drivers
+v0x1b47b70_0 .net "cs", 0 0, v0x1b44650_0;  1 drivers
+v0x1b47c40_0 .net "cs_pin", 0 0, v0x1b48a20_0;  1 drivers
+o0x7fac247edb28 .functor BUFZ 4, C4<zzzz>; HiZ drive
+v0x1b47d30_0 .net "leds", 3 0, o0x7fac247edb28;  0 drivers
+v0x1b47dd0_0 .var "load_mem", 0 0;
+v0x1b47ea0_0 .var "load_shift", 0 0;
+v0x1b47f40_0 .net "mem_out", 7 0, v0x1b45450_0;  1 drivers
+v0x1b480a0_0 .var "miso_pin", 0 0;
+v0x1b48140_0 .net "mosi", 0 0, v0x1b45c90_0;  1 drivers
+v0x1b48210_0 .net "mosi_pin", 0 0, v0x1b48e40_0;  1 drivers
+v0x1b482e0_0 .net "sclk_neg", 0 0, v0x1b46910_0;  1 drivers
+v0x1b483b0_0 .net "sclk_pin", 0 0, v0x1b48f30_0;  1 drivers
+v0x1b48480_0 .net "sclk_pos", 0 0, v0x1b46ae0_0;  1 drivers
+v0x1b48520_0 .net "shift_pOut", 7 0, L_0x1b49060;  1 drivers
+v0x1b48610_0 .net "shift_sOut", 0 0, L_0x1b490d0;  1 drivers
+v0x1b487c0_0 .var "state", 2 0;
+E_0x1b18920 .event posedge, v0x1b44650_0;
+E_0x1b18af0 .event posedge, v0x1b46910_0;
+E_0x1b18d60 .event posedge, v0x1b46ae0_0;
+S_0x1b06900 .scope module, "cscond" "inputconditioner" 3 35, 4 8 0, S_0x1b0ac80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk"
+    .port_info 1 /INPUT 1 "noisysignal"
+    .port_info 2 /OUTPUT 1 "conditioned"
+    .port_info 3 /OUTPUT 1 "positiveedge"
+    .port_info 4 /OUTPUT 1 "negativeedge"
+P_0x1b07790 .param/l "counterwidth" 0 4 17, +C4<00000000000000000000000000000011>;
+P_0x1b077d0 .param/l "waittime" 0 4 18, +C4<00000000000000000000000000000011>;
+v0x1afe470_0 .net "clk", 0 0, v0x1b48960_0;  alias, 1 drivers
+v0x1b44650_0 .var "conditioned", 0 0;
+v0x1b44710_0 .var "counter", 2 0;
+v0x1b44800_0 .var "negativeedge", 0 0;
+v0x1b448c0_0 .net "noisysignal", 0 0, v0x1b48a20_0;  alias, 1 drivers
+v0x1b449d0_0 .var "positiveedge", 0 0;
+v0x1b44a90_0 .var "synchronizer0", 0 0;
+v0x1b44b50_0 .var "synchronizer1", 0 0;
+E_0x1b182a0 .event posedge, v0x1afe470_0;
+S_0x1b44cb0 .scope module, "mem" "datamemory" 3 42, 5 8 0, S_0x1b0ac80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk"
+    .port_info 1 /OUTPUT 8 "dataOut"
+    .port_info 2 /INPUT 7 "address"
+    .port_info 3 /INPUT 1 "writeEnable"
+    .port_info 4 /INPUT 8 "dataIn"
+P_0x1b44ea0 .param/l "addresswidth" 0 5 10, +C4<00000000000000000000000000000111>;
+P_0x1b44ee0 .param/l "depth" 0 5 11, +C4<00000000000000000000000010000000>;
+P_0x1b44f20 .param/l "width" 0 5 12, +C4<00000000000000000000000000001000>;
+v0x1b45210_0 .net "address", 6 0, v0x1b478d0_0;  1 drivers
+v0x1b452b0_0 .net "clk", 0 0, v0x1b48960_0;  alias, 1 drivers
+v0x1b45380_0 .net "dataIn", 7 0, L_0x1b49060;  alias, 1 drivers
+v0x1b45450_0 .var "dataOut", 7 0;
+v0x1b45510 .array "memory", 0 127, 7 0;
+v0x1b45620_0 .net "writeEnable", 0 0, v0x1b47dd0_0;  1 drivers
+S_0x1b45780 .scope module, "mosicond" "inputconditioner" 3 34, 4 8 0, S_0x1b0ac80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk"
+    .port_info 1 /INPUT 1 "noisysignal"
+    .port_info 2 /OUTPUT 1 "conditioned"
+    .port_info 3 /OUTPUT 1 "positiveedge"
+    .port_info 4 /OUTPUT 1 "negativeedge"
+P_0x1b45950 .param/l "counterwidth" 0 4 17, +C4<00000000000000000000000000000011>;
+P_0x1b45990 .param/l "waittime" 0 4 18, +C4<00000000000000000000000000000011>;
+v0x1b45ba0_0 .net "clk", 0 0, v0x1b48960_0;  alias, 1 drivers
+v0x1b45c90_0 .var "conditioned", 0 0;
+v0x1b45d50_0 .var "counter", 2 0;
+v0x1b45e10_0 .var "negativeedge", 0 0;
+v0x1b45ed0_0 .net "noisysignal", 0 0, v0x1b48e40_0;  alias, 1 drivers
+v0x1b45fe0_0 .var "positiveedge", 0 0;
+v0x1b460a0_0 .var "synchronizer0", 0 0;
+v0x1b46160_0 .var "synchronizer1", 0 0;
+S_0x1b462c0 .scope module, "sclkcond" "inputconditioner" 3 36, 4 8 0, S_0x1b0ac80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk"
+    .port_info 1 /INPUT 1 "noisysignal"
+    .port_info 2 /OUTPUT 1 "conditioned"
+    .port_info 3 /OUTPUT 1 "positiveedge"
+    .port_info 4 /OUTPUT 1 "negativeedge"
+P_0x1b46490 .param/l "counterwidth" 0 4 17, +C4<00000000000000000000000000000011>;
+P_0x1b464d0 .param/l "waittime" 0 4 18, +C4<00000000000000000000000000000011>;
+v0x1b46700_0 .net "clk", 0 0, v0x1b48960_0;  alias, 1 drivers
+v0x1b467a0_0 .var "conditioned", 0 0;
+v0x1b46840_0 .var "counter", 2 0;
+v0x1b46910_0 .var "negativeedge", 0 0;
+v0x1b469d0_0 .net "noisysignal", 0 0, v0x1b48f30_0;  alias, 1 drivers
+v0x1b46ae0_0 .var "positiveedge", 0 0;
+v0x1b46ba0_0 .var "synchronizer0", 0 0;
+v0x1b46c60_0 .var "synchronizer1", 0 0;
+S_0x1b46dc0 .scope module, "shiftReg" "shiftregister" 3 39, 6 9 0, S_0x1b0ac80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk"
+    .port_info 1 /INPUT 1 "peripheralClkEdge"
+    .port_info 2 /INPUT 1 "parallelLoad"
+    .port_info 3 /INPUT 8 "parallelDataIn"
+    .port_info 4 /INPUT 1 "serialDataIn"
+    .port_info 5 /OUTPUT 8 "parallelDataOut"
+    .port_info 6 /OUTPUT 1 "serialDataOut"
+P_0x1b46fe0 .param/l "width" 0 6 10, +C4<00000000000000000000000000001000>;
+L_0x1b49060 .functor BUFZ 8, v0x1b476d0_0, C4<00000000>, C4<00000000>, C4<00000000>;
+v0x1b47130_0 .net "clk", 0 0, v0x1b48960_0;  alias, 1 drivers
+o0x7fac247ed8b8 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
+v0x1b47280_0 .net "parallelDataIn", 7 0, o0x7fac247ed8b8;  0 drivers
+v0x1b47360_0 .net "parallelDataOut", 7 0, L_0x1b49060;  alias, 1 drivers
+o0x7fac247ed8e8 .functor BUFZ 1, C4<z>; HiZ drive
+v0x1b47430_0 .net "parallelLoad", 0 0, o0x7fac247ed8e8;  0 drivers
+v0x1b474d0_0 .net "peripheralClkEdge", 0 0, v0x1b46ae0_0;  alias, 1 drivers
+o0x7fac247ed918 .functor BUFZ 1, C4<z>; HiZ drive
+v0x1b47570_0 .net "serialDataIn", 0 0, o0x7fac247ed918;  0 drivers
+v0x1b47610_0 .net "serialDataOut", 0 0, L_0x1b490d0;  alias, 1 drivers
+v0x1b476d0_0 .var "shiftregistermem", 7 0;
+L_0x1b490d0 .part v0x1b476d0_0, 7, 1;
+    .scope S_0x1b45780;
+T_0 ;
+    %pushi/vec4 0, 0, 3;
+    %store/vec4 v0x1b45d50_0, 0, 3;
+    %end;
+    .thread T_0;
+    .scope S_0x1b45780;
+T_1 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b460a0_0, 0, 1;
+    %end;
+    .thread T_1;
+    .scope S_0x1b45780;
+T_2 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b46160_0, 0, 1;
+    %end;
+    .thread T_2;
+    .scope S_0x1b45780;
+T_3 ;
+    %wait E_0x1b182a0;
+    %load/vec4 v0x1b45c90_0;
+    %load/vec4 v0x1b46160_0;
+    %cmp/e;
+    %jmp/0xz  T_3.0, 4;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0x1b45d50_0, 0;
+    %jmp T_3.1;
+T_3.0 ;
+    %load/vec4 v0x1b45d50_0;
+    %pad/u 32;
+    %cmpi/e 3, 0, 32;
+    %jmp/0xz  T_3.2, 4;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0x1b45d50_0, 0;
+    %load/vec4 v0x1b46160_0;
+    %assign/vec4 v0x1b45c90_0, 0;
+    %load/vec4 v0x1b45c90_0;
+    %inv;
+    %load/vec4 v0x1b46160_0;
+    %and;
+    %assign/vec4 v0x1b45fe0_0, 0;
+    %load/vec4 v0x1b46160_0;
+    %inv;
+    %load/vec4 v0x1b45c90_0;
+    %and;
+    %assign/vec4 v0x1b45e10_0, 0;
+    %jmp T_3.3;
+T_3.2 ;
+    %load/vec4 v0x1b45d50_0;
+    %addi 1, 0, 3;
+    %assign/vec4 v0x1b45d50_0, 0;
+T_3.3 ;
+T_3.1 ;
+    %load/vec4 v0x1b45fe0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_3.4, 8;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0x1b45fe0_0, 0;
+T_3.4 ;
+    %load/vec4 v0x1b45e10_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_3.6, 8;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0x1b45e10_0, 0;
+T_3.6 ;
+    %load/vec4 v0x1b45ed0_0;
+    %assign/vec4 v0x1b460a0_0, 0;
+    %load/vec4 v0x1b460a0_0;
+    %assign/vec4 v0x1b46160_0, 0;
+    %jmp T_3;
+    .thread T_3;
+    .scope S_0x1b06900;
+T_4 ;
+    %pushi/vec4 0, 0, 3;
+    %store/vec4 v0x1b44710_0, 0, 3;
+    %end;
+    .thread T_4;
+    .scope S_0x1b06900;
+T_5 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b44a90_0, 0, 1;
+    %end;
+    .thread T_5;
+    .scope S_0x1b06900;
+T_6 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b44b50_0, 0, 1;
+    %end;
+    .thread T_6;
+    .scope S_0x1b06900;
+T_7 ;
+    %wait E_0x1b182a0;
+    %load/vec4 v0x1b44650_0;
+    %load/vec4 v0x1b44b50_0;
+    %cmp/e;
+    %jmp/0xz  T_7.0, 4;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0x1b44710_0, 0;
+    %jmp T_7.1;
+T_7.0 ;
+    %load/vec4 v0x1b44710_0;
+    %pad/u 32;
+    %cmpi/e 3, 0, 32;
+    %jmp/0xz  T_7.2, 4;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0x1b44710_0, 0;
+    %load/vec4 v0x1b44b50_0;
+    %assign/vec4 v0x1b44650_0, 0;
+    %load/vec4 v0x1b44650_0;
+    %inv;
+    %load/vec4 v0x1b44b50_0;
+    %and;
+    %assign/vec4 v0x1b449d0_0, 0;
+    %load/vec4 v0x1b44b50_0;
+    %inv;
+    %load/vec4 v0x1b44650_0;
+    %and;
+    %assign/vec4 v0x1b44800_0, 0;
+    %jmp T_7.3;
+T_7.2 ;
+    %load/vec4 v0x1b44710_0;
+    %addi 1, 0, 3;
+    %assign/vec4 v0x1b44710_0, 0;
+T_7.3 ;
+T_7.1 ;
+    %load/vec4 v0x1b449d0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_7.4, 8;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0x1b449d0_0, 0;
+T_7.4 ;
+    %load/vec4 v0x1b44800_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_7.6, 8;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0x1b44800_0, 0;
+T_7.6 ;
+    %load/vec4 v0x1b448c0_0;
+    %assign/vec4 v0x1b44a90_0, 0;
+    %load/vec4 v0x1b44a90_0;
+    %assign/vec4 v0x1b44b50_0, 0;
+    %jmp T_7;
+    .thread T_7;
+    .scope S_0x1b462c0;
+T_8 ;
+    %pushi/vec4 0, 0, 3;
+    %store/vec4 v0x1b46840_0, 0, 3;
+    %end;
+    .thread T_8;
+    .scope S_0x1b462c0;
+T_9 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b46ba0_0, 0, 1;
+    %end;
+    .thread T_9;
+    .scope S_0x1b462c0;
+T_10 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b46c60_0, 0, 1;
+    %end;
+    .thread T_10;
+    .scope S_0x1b462c0;
+T_11 ;
+    %wait E_0x1b182a0;
+    %load/vec4 v0x1b467a0_0;
+    %load/vec4 v0x1b46c60_0;
+    %cmp/e;
+    %jmp/0xz  T_11.0, 4;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0x1b46840_0, 0;
+    %jmp T_11.1;
+T_11.0 ;
+    %load/vec4 v0x1b46840_0;
+    %pad/u 32;
+    %cmpi/e 3, 0, 32;
+    %jmp/0xz  T_11.2, 4;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0x1b46840_0, 0;
+    %load/vec4 v0x1b46c60_0;
+    %assign/vec4 v0x1b467a0_0, 0;
+    %load/vec4 v0x1b467a0_0;
+    %inv;
+    %load/vec4 v0x1b46c60_0;
+    %and;
+    %assign/vec4 v0x1b46ae0_0, 0;
+    %load/vec4 v0x1b46c60_0;
+    %inv;
+    %load/vec4 v0x1b467a0_0;
+    %and;
+    %assign/vec4 v0x1b46910_0, 0;
+    %jmp T_11.3;
+T_11.2 ;
+    %load/vec4 v0x1b46840_0;
+    %addi 1, 0, 3;
+    %assign/vec4 v0x1b46840_0, 0;
+T_11.3 ;
+T_11.1 ;
+    %load/vec4 v0x1b46ae0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_11.4, 8;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0x1b46ae0_0, 0;
+T_11.4 ;
+    %load/vec4 v0x1b46910_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_11.6, 8;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0x1b46910_0, 0;
+T_11.6 ;
+    %load/vec4 v0x1b469d0_0;
+    %assign/vec4 v0x1b46ba0_0, 0;
+    %load/vec4 v0x1b46ba0_0;
+    %assign/vec4 v0x1b46c60_0, 0;
+    %jmp T_11;
+    .thread T_11;
+    .scope S_0x1b46dc0;
+T_12 ;
+    %wait E_0x1b182a0;
+    %load/vec4 v0x1b47430_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_12.0, 8;
+    %load/vec4 v0x1b47280_0;
+    %assign/vec4 v0x1b476d0_0, 0;
+    %jmp T_12.1;
+T_12.0 ;
+    %load/vec4 v0x1b474d0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_12.2, 8;
+    %load/vec4 v0x1b476d0_0;
+    %parti/s 7, 0, 2;
+    %load/vec4 v0x1b47570_0;
+    %concat/vec4; draw_concat_vec4
+    %assign/vec4 v0x1b476d0_0, 0;
+T_12.2 ;
+T_12.1 ;
+    %jmp T_12;
+    .thread T_12;
+    .scope S_0x1b44cb0;
+T_13 ;
+    %wait E_0x1b182a0;
+    %load/vec4 v0x1b45620_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_13.0, 8;
+    %load/vec4 v0x1b45380_0;
+    %load/vec4 v0x1b45210_0;
+    %pad/u 9;
+    %ix/vec4 3;
+    %ix/load 4, 0, 0; Constant delay
+    %assign/vec4/a/d v0x1b45510, 0, 4;
+T_13.0 ;
+    %load/vec4 v0x1b45210_0;
+    %pad/u 9;
+    %ix/vec4 4;
+    %load/vec4a v0x1b45510, 4;
+    %assign/vec4 v0x1b45450_0, 0;
+    %jmp T_13;
+    .thread T_13;
+    .scope S_0x1b0ac80;
+T_14 ;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0x1b487c0_0, 0;
+    %pushi/vec4 0, 0, 7;
+    %assign/vec4 v0x1b478d0_0, 0;
+    %pushi/vec4 0, 0, 5;
+    %assign/vec4 v0x1b479e0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0x1b47ea0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0x1b47dd0_0, 0;
+    %pushi/vec4 0, 1, 1;
+    %assign/vec4 v0x1b480a0_0, 0;
+    %end;
+    .thread T_14;
+    .scope S_0x1b0ac80;
+T_15 ;
+    %wait E_0x1b18d60;
+    %load/vec4 v0x1b47b70_0;
+    %nor/r;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_15.0, 8;
+    %load/vec4 v0x1b487c0_0;
+    %cmpi/e 0, 0, 3;
+    %jmp/0xz  T_15.2, 4;
+    %load/vec4 v0x1b479e0_0;
+    %addi 1, 0, 5;
+    %store/vec4 v0x1b479e0_0, 0, 5;
+    %load/vec4 v0x1b479e0_0;
+    %pad/u 32;
+    %cmpi/e 7, 0, 32;
+    %jmp/0xz  T_15.4, 4;
+    %pushi/vec4 1, 0, 3;
+    %assign/vec4 v0x1b487c0_0, 0;
+    %load/vec4 v0x1b48520_0;
+    %parti/s 7, 0, 2;
+    %assign/vec4 v0x1b478d0_0, 0;
+T_15.4 ;
+T_15.2 ;
+    %load/vec4 v0x1b487c0_0;
+    %cmpi/e 3, 0, 3;
+    %jmp/0xz  T_15.6, 4;
+    %load/vec4 v0x1b479e0_0;
+    %addi 1, 0, 5;
+    %store/vec4 v0x1b479e0_0, 0, 5;
+    %load/vec4 v0x1b479e0_0;
+    %pad/u 32;
+    %cmpi/e 8, 0, 32;
+    %jmp/0xz  T_15.8, 4;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0x1b47dd0_0, 0;
+    %load/vec4 v0x1b478d0_0;
+    %addi 1, 0, 7;
+    %assign/vec4 v0x1b478d0_0, 0;
+T_15.8 ;
+T_15.6 ;
+    %load/vec4 v0x1b487c0_0;
+    %cmpi/e 1, 0, 3;
+    %jmp/0xz  T_15.10, 4;
+    %load/vec4 v0x1b48520_0;
+    %parti/s 1, 0, 2;
+    %pad/u 32;
+    %cmpi/e 1, 0, 32;
+    %jmp/0xz  T_15.12, 4;
+    %pushi/vec4 3, 0, 3;
+    %assign/vec4 v0x1b487c0_0, 0;
+T_15.12 ;
+    %load/vec4 v0x1b48520_0;
+    %parti/s 1, 0, 2;
+    %pad/u 32;
+    %cmpi/e 0, 0, 32;
+    %jmp/0xz  T_15.14, 4;
+    %pushi/vec4 2, 0, 3;
+    %assign/vec4 v0x1b487c0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0x1b47ea0_0, 0;
+T_15.14 ;
+    %pushi/vec4 0, 0, 5;
+    %assign/vec4 v0x1b479e0_0, 0;
+T_15.10 ;
+T_15.0 ;
+    %jmp T_15;
+    .thread T_15;
+    .scope S_0x1b0ac80;
+T_16 ;
+    %wait E_0x1b18af0;
+    %load/vec4 v0x1b47dd0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_16.0, 8;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0x1b47dd0_0, 0;
+T_16.0 ;
+    %load/vec4 v0x1b47ea0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_16.2, 8;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0x1b47ea0_0, 0;
+T_16.2 ;
+    %load/vec4 v0x1b47b70_0;
+    %nor/r;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_16.4, 8;
+    %load/vec4 v0x1b487c0_0;
+    %cmpi/e 2, 0, 3;
+    %jmp/0xz  T_16.6, 4;
+    %load/vec4 v0x1b48610_0;
+    %assign/vec4 v0x1b480a0_0, 0;
+    %load/vec4 v0x1b479e0_0;
+    %addi 1, 0, 5;
+    %store/vec4 v0x1b479e0_0, 0, 5;
+T_16.6 ;
+T_16.4 ;
+    %jmp T_16;
+    .thread T_16;
+    .scope S_0x1b0ac80;
+T_17 ;
+    %wait E_0x1b18920;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0x1b487c0_0, 0;
+    %pushi/vec4 0, 0, 5;
+    %assign/vec4 v0x1b479e0_0, 0;
+    %pushi/vec4 0, 1, 1;
+    %assign/vec4 v0x1b480a0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0x1b47dd0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0x1b47ea0_0, 0;
+    %jmp T_17;
+    .thread T_17;
+    .scope S_0x1b0ab00;
+T_18 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b48960_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b48f30_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b48a20_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b48e40_0, 0, 1;
+    %end;
+    .thread T_18;
+    .scope S_0x1b0ab00;
+T_19 ;
+    %vpi_call 2 33 "$dumpfile", "spimem.vcd" {0 0 0};
+    %vpi_call 2 34 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x1b0ab00 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1b48bb0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1b48a20_0, 0, 1;
+    %delay 100, 0;
+    %load/vec4 v0x1b48da0_0;
+    %cmpi/ne 0, 1, 1;
+    %jmp/0xz  T_19.0, 6;
+    %vpi_call 2 40 "$display", "chip not in Z state when CS is high" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b48bb0_0, 0, 1;
+T_19.0 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b48a20_0, 0, 1;
+    %delay 100, 0;
+    %pushi/vec4 85, 0, 7;
+    %store/vec4 v0x1b48860_0, 0, 7;
+    %pushi/vec4 240, 0, 8;
+    %store/vec4 v0x1b48b10_0, 0, 8;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x1b48cc0_0, 0, 32;
+T_19.2 ;
+    %load/vec4 v0x1b48cc0_0;
+    %cmpi/u 7, 0, 32;
+    %jmp/0xz T_19.3, 5;
+    %load/vec4 v0x1b48860_0;
+    %load/vec4 v0x1b48cc0_0;
+    %part/u 1;
+    %store/vec4 v0x1b48e40_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1b48f30_0, 0, 1;
+    %delay 100, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b48f30_0, 0, 1;
+    %load/vec4 v0x1b48cc0_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0x1b48cc0_0, 0, 32;
+    %jmp T_19.2;
+T_19.3 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b48e40_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1b48f30_0, 0, 1;
+    %delay 100, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b48f30_0, 0, 1;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x1b48cc0_0, 0, 32;
+T_19.4 ;
+    %load/vec4 v0x1b48cc0_0;
+    %cmpi/u 8, 0, 32;
+    %jmp/0xz T_19.5, 5;
+    %load/vec4 v0x1b48b10_0;
+    %load/vec4 v0x1b48cc0_0;
+    %part/u 1;
+    %store/vec4 v0x1b48e40_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1b48f30_0, 0, 1;
+    %delay 100, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b48f30_0, 0, 1;
+    %load/vec4 v0x1b48cc0_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0x1b48cc0_0, 0, 32;
+    %jmp T_19.4;
+T_19.5 ;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x1b48cc0_0, 0, 32;
+T_19.6 ;
+    %load/vec4 v0x1b48cc0_0;
+    %cmpi/u 7, 0, 32;
+    %jmp/0xz T_19.7, 5;
+    %load/vec4 v0x1b48860_0;
+    %load/vec4 v0x1b48cc0_0;
+    %part/u 1;
+    %store/vec4 v0x1b48e40_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1b48f30_0, 0, 1;
+    %delay 100, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b48f30_0, 0, 1;
+    %load/vec4 v0x1b48cc0_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0x1b48cc0_0, 0, 32;
+    %jmp T_19.6;
+T_19.7 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b48e40_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1b48f30_0, 0, 1;
+    %delay 100, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b48f30_0, 0, 1;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x1b48cc0_0, 0, 32;
+T_19.8 ;
+    %load/vec4 v0x1b48cc0_0;
+    %cmpi/u 8, 0, 32;
+    %jmp/0xz T_19.9, 5;
+    %load/vec4 v0x1b48da0_0;
+    %load/vec4 v0x1b48b10_0;
+    %load/vec4 v0x1b48cc0_0;
+    %part/u 1;
+    %cmp/ne;
+    %flag_mov 8, 6;
+    %load/vec4 v0x1b48da0_0;
+    %cmpi/e 1, 1, 1;
+    %flag_or 6, 8;
+    %jmp/0xz  T_19.10, 6;
+    %vpi_call 2 88 "$display", "read byte is different from written byte" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b48bb0_0, 0, 1;
+T_19.10 ;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1b48f30_0, 0, 1;
+    %delay 100, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1b48f30_0, 0, 1;
+    %load/vec4 v0x1b48cc0_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0x1b48cc0_0, 0, 32;
+    %jmp T_19.8;
+T_19.9 ;
+    %vpi_call 2 96 "$display", "DUT passed" {0 0 0};
+    %end;
+    .thread T_19;
+    .scope S_0x1b0ab00;
+T_20 ;
+    %wait E_0x1b17e60;
+    %vpi_call 2 101 "$display", "DUT failed" {0 0 0};
+    %vpi_call 2 102 "$finish" {0 0 0};
+    %jmp T_20;
+    .thread T_20;
+# The file index is used to find the file name in the following table.
+:file_names 7;
+    "N/A";
+    "<interactive>";
+    "spimemory.t.v";
+    "./spimemory.v";
+    "./inputconditioner.v";
+    "./datamemory.v";
+    "./shiftregister.v";
diff --git a/spimem.vcd b/spimem.vcd
new file mode 100644
index 0000000..682000e
--- /dev/null
+++ b/spimem.vcd
@@ -0,0 +1,231 @@
+$date
+	Wed Nov  1 21:09:35 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module testMemory $end
+$var wire 1 ! miso_pin $end
+$var reg 7 " address [6:0] $end
+$var reg 1 # clk $end
+$var reg 1 $ cs_pin $end
+$var reg 8 % data [7:0] $end
+$var reg 1 & dutpassed $end
+$var reg 32 ' i [31:0] $end
+$var reg 1 ( mosi_pin $end
+$var reg 1 ) sclk_pin $end
+$scope module dut $end
+$var wire 1 # clk $end
+$var wire 1 $ cs_pin $end
+$var wire 4 * leds [3:0] $end
+$var wire 1 ( mosi_pin $end
+$var wire 1 ) sclk_pin $end
+$var wire 1 + shift_sOut $end
+$var wire 8 , shift_pOut [7:0] $end
+$var wire 1 - sclk_pos $end
+$var wire 1 . sclk_neg $end
+$var wire 1 / mosi $end
+$var wire 8 0 mem_out [7:0] $end
+$var wire 1 1 cs $end
+$var reg 7 2 addressReg [6:0] $end
+$var reg 5 3 bitsTx [4:0] $end
+$var reg 1 4 load_mem $end
+$var reg 1 5 load_shift $end
+$var reg 1 ! miso_pin $end
+$var reg 3 6 state [2:0] $end
+$scope module cscond $end
+$var wire 1 # clk $end
+$var wire 1 $ noisysignal $end
+$var reg 1 1 conditioned $end
+$var reg 3 7 counter [2:0] $end
+$var reg 1 8 negativeedge $end
+$var reg 1 9 positiveedge $end
+$var reg 1 : synchronizer0 $end
+$var reg 1 ; synchronizer1 $end
+$upscope $end
+$scope module mem $end
+$var wire 7 < address [6:0] $end
+$var wire 1 # clk $end
+$var wire 1 4 writeEnable $end
+$var wire 8 = dataIn [7:0] $end
+$var reg 8 > dataOut [7:0] $end
+$upscope $end
+$scope module mosicond $end
+$var wire 1 # clk $end
+$var wire 1 ( noisysignal $end
+$var reg 1 / conditioned $end
+$var reg 3 ? counter [2:0] $end
+$var reg 1 @ negativeedge $end
+$var reg 1 A positiveedge $end
+$var reg 1 B synchronizer0 $end
+$var reg 1 C synchronizer1 $end
+$upscope $end
+$scope module sclkcond $end
+$var wire 1 # clk $end
+$var wire 1 ) noisysignal $end
+$var reg 1 D conditioned $end
+$var reg 3 E counter [2:0] $end
+$var reg 1 . negativeedge $end
+$var reg 1 - positiveedge $end
+$var reg 1 F synchronizer0 $end
+$var reg 1 G synchronizer1 $end
+$upscope $end
+$scope module shiftReg $end
+$var wire 1 # clk $end
+$var wire 8 H parallelDataIn [7:0] $end
+$var wire 8 I parallelDataOut [7:0] $end
+$var wire 1 J parallelLoad $end
+$var wire 1 - peripheralClkEdge $end
+$var wire 1 K serialDataIn $end
+$var wire 1 + serialDataOut $end
+$var reg 8 L shiftregistermem [7:0] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+bx L
+zK
+zJ
+bx I
+bz H
+0G
+0F
+b0 E
+xD
+0C
+0B
+xA
+x@
+b0 ?
+bx >
+bx =
+b0 <
+0;
+0:
+x9
+x8
+b0 7
+b0 6
+05
+04
+b0 3
+b0 2
+x1
+bx 0
+x/
+x.
+x-
+bx ,
+x+
+bz *
+0)
+0(
+bx '
+1&
+bx %
+1$
+0#
+bx "
+z!
+$end
+#100
+0$
+#200
+1)
+1(
+b0 '
+b11110000 %
+b1010101 "
+#300
+0(
+b1 '
+1)
+#400
+1(
+b10 '
+1)
+#500
+0(
+b11 '
+1)
+#600
+1(
+b100 '
+1)
+#700
+0(
+b101 '
+1)
+#800
+1(
+b110 '
+1)
+#900
+0(
+b111 '
+1)
+#1000
+b0 '
+1)
+#1100
+b1 '
+1)
+#1200
+b10 '
+1)
+#1300
+b11 '
+1)
+#1400
+1(
+b100 '
+1)
+#1500
+b101 '
+1)
+#1600
+b110 '
+1)
+#1700
+b111 '
+1)
+#1800
+b0 '
+1)
+#1900
+0(
+b1 '
+1)
+#2000
+1(
+b10 '
+1)
+#2100
+0(
+b11 '
+1)
+#2200
+1(
+b100 '
+1)
+#2300
+0(
+b101 '
+1)
+#2400
+1(
+b110 '
+1)
+#2500
+0(
+b111 '
+1)
+#2600
+0&
+b0 '
+1)
diff --git a/spimemory.t.v b/spimemory.t.v
new file mode 100644
index 0000000..e2b9f3c
--- /dev/null
+++ b/spimemory.t.v
@@ -0,0 +1,121 @@
+//----------------------------------------------------------------------
+// SPI Memory test bench
+//----------------------------------------------------------------------
+`include "spimemory.v"
+
+module testMemory();
+
+   reg clk;
+   reg sclk_pin;
+   reg cs_pin;
+   reg mosi_pin;
+   wire miso_pin;
+   reg [6:0] address;
+   reg [7:0] data;
+   reg 	dutpassed;
+   reg[31:0] i;
+
+   spiMemory dut(.clk(clk),
+		 .sclk_pin(sclk_pin),
+		 .cs_pin(cs_pin),
+		 .mosi_pin(mosi_pin),
+		 .miso_pin(miso_pin));
+
+   initial clk = 0;
+
+   always #10 clk = !clk;
+
+   initial begin
+      sclk_pin = 0;
+      cs_pin = 0;
+      mosi_pin = 0;
+   end
+   //always #10 clk != clk;
+
+   initial begin
+   $dumpfile("spimem.vcd");
+   $dumpvars(0, testMemory);
+      dutpassed = 1;
+
+      cs_pin = 1;
+      #1000;
+      if(miso_pin !== 'z) begin
+	 $display("chip not in Z state when CS is high");
+	 dutpassed = 0;
+      end
+      cs_pin = 0;
+      #1000
+
+      address = 7'b1010101;
+      data = 8'b11110000;
+
+      //write address
+      for(i=0; i < 7; i=i+1) begin
+	 mosi_pin = address[i];
+	 sclk_pin = 1;
+	 #1000;
+	 sclk_pin = 0;
+	 #1000;
+      end
+
+      //set write
+      mosi_pin = 0;
+      sclk_pin = 1;
+      #1000;
+      sclk_pin = 0;
+      #1000;
+
+
+      //write data
+      for(i=0; i < 8; i=i+1) begin
+	 mosi_pin = data[i];
+	 sclk_pin = 1;
+	 #1000;
+	 sclk_pin = 0;
+	 #1000;
+
+      end
+      //deassert and reassert CS
+      cs_pin = 1;
+      #1000;
+      cs_pin = 0;
+      #1000;
+
+      //write address
+      for(i=0; i < 7; i=i+1) begin
+	 mosi_pin = address[i];
+	 sclk_pin = 1;
+	 #1000;
+	 sclk_pin = 0;
+	 #1000;
+
+      end
+
+      //set read
+      mosi_pin = 1;
+      sclk_pin = 1;
+      #1000;
+      sclk_pin = 0;
+      #1000;
+
+      //read data
+      for(i=0; i < 8; i=i+1) begin
+	 if(miso_pin !== data[i] || miso_pin === 'x) begin
+	    $display("read byte is different from written byte");
+	    dutpassed = 0;
+	 end
+	 sclk_pin = 1;
+	 #1000;
+	 sclk_pin = 0;
+	 #1000;
+      end
+
+      $display("DUT passed");
+
+
+   end // initial begin
+   always @(negedge dutpassed) begin
+      $display("DUT failed");
+      $finish();
+   end
+endmodule
diff --git a/spimemory.v b/spimemory.v
index c6ed4f7..1c14109 100644
--- a/spimemory.v
+++ b/spimemory.v
@@ -1,17 +1,109 @@
 //------------------------------------------------------------------------
 // SPI Memory
 //------------------------------------------------------------------------
+`define READ_ADDRESS 2'd0
+`define READ_WR      2'd1
+`define WRITE_DATA   2'd2
+`define READ_DATA    2'd3
+`include "shiftregister.v"
+`include "inputconditioner.v"
+`include "datamemory.v"
 
 module spiMemory
 (
     input           clk,        // FPGA clock
     input           sclk_pin,   // SPI clock
     input           cs_pin,     // SPI chip select
-    output          miso_pin,   // SPI master in slave out
+    output reg      miso_pin,   // SPI master in slave out
     input           mosi_pin,   // SPI master out slave in
     output [3:0]    leds        // LEDs for debugging
-)
+);
+wire mosi;
+wire cs;
+wire sclk_neg;
+wire sclk_pos;
+wire[7:0] shift_pOut;
+wire      shift_sOut;
+wire[7:0] mem_out;
+reg[6:0] addressReg;
+reg[2:0] state;
+reg[4:0] bitsTx;
+reg load_shift;
+reg load_mem;
 
+inputconditioner mosicond(.clk(clk), .noisysignal(mosi_pin), .conditioned(mosi));
+inputconditioner cscond(  .clk(clk), .noisysignal(cs_pin),   .conditioned(cs));
+inputconditioner sclkcond(.clk(clk), .noisysignal(sclk_pin),
+                          .positiveedge(sclk_pos), .negativeedge(sclk_neg));
+
+shiftregister shiftReg(.clk(clk), .peripheralClkEdge(sclk_pos),
+                       .parallelDataOut(shift_pOut), .serialDataOut(shift_sOut),
+                       .serialDataIn(mosi), .parallelLoad(load_shift), .parallelDataIn(mem_out)
+                       );
+datamemory mem(.clk(clk),
+               .dataOut(mem_out),
+               .address(addressReg),
+               .writeEnable(load_mem),
+               .dataIn(shift_pOut));
+
+initial begin
+   state      <= `READ_ADDRESS;
+   addressReg <= 7'd0;
+   bitsTx     <= 4'd0;
+   load_shift <= 0;
+   load_mem   <= 0;
+   miso_pin <= 'z;
+end
+
+always @(negedge sclk_pos) begin
+  if(!cs) begin
+    if(state == `READ_ADDRESS) begin
+      bitsTx <= bitsTx + 1;
+      if(bitsTx == 7) begin
+        state   <= `READ_WR;
+        addressReg <= shift_pOut[6:0];
+      end
+    end
+    if(state == `READ_DATA) begin
+      bitsTx = bitsTx + 1;
+      if(bitsTx == 8) begin
+        load_mem <= 1;
+      end
+    end
+    if(state == `READ_WR) begin
+      if(shift_pOut[0] == 0) begin
+        state <= `READ_DATA;
+      end
+      if(shift_pOut[0] == 1) begin
+        state <= `WRITE_DATA;
+        load_shift <= 1;
+      end
+      bitsTx <= 4'd0;
+    end
+  end
+end
+
+always @ (posedge sclk_neg) begin
+  if(load_mem) begin
+    load_mem <= 0;
+  end
+  if(load_shift) begin
+    load_shift <= 0;
+  end
+  if(!cs) begin
+    if(state == `WRITE_DATA) begin
+      miso_pin <= shift_sOut;
+      bitsTx <= bitsTx + 1;
+    end
+  end
+end
+
+always @(posedge cs) begin
+  state    <= `READ_ADDRESS;
+  bitsTx   <= 4'd0;
+  miso_pin <= 'z;
+  load_mem <= 0;
+  load_shift <= 0;
+end
 
 endmodule
-   
diff --git a/work_plan.txt b/work_plan.txt
new file mode 100644
index 0000000..98de84b
--- /dev/null
+++ b/work_plan.txt
@@ -0,0 +1,6 @@
+Input Conditioner (10/23) (1.5 hrs)
+Shift Register (10/24) (2 hrs)
+FPGA (10/24) (3 hrs)
+Midpoint Checkin (10/25)
+SPI Memory Integration (10/31) (5 hrs)
+Writeup (11/1) (4 - 5 hrs)