diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..e39d5e7
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,18 @@
+test: build
+	echo "Running ALU test bench"
+	./alu
+	echo -e "\n\nRunning memory test bench"
+	./memory
+	echo -e "\n\nRunning register file test bench"
+	./registerFile
+	echo -e "\n\nRunning CPU test bench"
+	./cpu
+
+build: alu.t.v alu.v cpu.t.v cpu.v memory.t.v memory.v registerFile.t.v registerFile.v
+	iverilog alu.t.v -o alu
+	iverilog cpu.t.v -o cpu
+	iverilog memory.t.v -o memory
+	iverilog registerFile.t.v -o registerFile
+
+clean:
+	rm alu cpu memory registerFile
diff --git a/Writeup.pdf b/Writeup.pdf
new file mode 100644
index 0000000..28f02da
Binary files /dev/null and b/Writeup.pdf differ
diff --git a/alu.t.v b/alu.t.v
new file mode 100644
index 0000000..aedb1ed
--- /dev/null
+++ b/alu.t.v
@@ -0,0 +1,137 @@
+`include "alu.v"
+
+module aluTestBench();
+  reg signed [31:0] A;
+  reg signed [31:0] B;
+  reg        [1:0]  op;
+  wire signed[31:0] out;
+  wire eq;
+  reg dutPassed;
+  alu dut(out, eq, op, A, B);
+  initial begin
+    dutPassed = 1;
+    A = 32'd10;
+    B = 32'd14;
+    op = `addOp;
+    #1;
+    if(out != 24 || ^out === 1'bx) begin
+      $display("Add test failed");
+      dutPassed = 0;
+    end
+
+    A = 32'd10;
+    B = 32'd14;
+    op = `subOp;
+    #1;
+    if(out != -4 || ^out === 1'bx) begin
+      $display("Sub test failed");
+      dutPassed = 0;
+    end
+
+    A = 32'b00001111000011110000111100001111;
+    B = 32'b10101010101010101010101010101010;
+    op = `xorOp;
+    #1;
+    if(out != 32'b10100101101001011010010110100101 || ^out === 1'bx) begin
+      $display("Xor test failed");
+      dutPassed = 0;
+    end
+
+    A = 14;
+    B = 32;
+    op = `sltOp;
+    #1;
+    if(out != 1 || ^out === 1'bx) begin
+      $display("Slt test failed");
+      $display("14 >= 32");
+      dutPassed = 0;
+    end
+
+    A = 32;
+    B = 14;
+    op = `sltOp;
+    #1;
+    if(out != 0 || ^out === 1'bx) begin
+      $display("Slt test failed");
+      $display("32 < 14");
+      dutPassed = 0;
+    end
+
+    A = -14;
+    B = -32;
+    op = `sltOp;
+    #1;
+    if(out != 0 || ^out === 1'bx) begin
+      $display("Slt test failed");
+      $display("-14 < -32");
+      dutPassed = 0;
+    end
+
+    A = -32;
+    B = -14;
+    op = `sltOp;
+    #1;
+    if(out != 1 || ^out === 1'bx) begin
+      $display("Slt test failed");
+      $display("-32 >= -14");
+      dutPassed = 0;
+    end
+
+    A = 14;
+    B = -32;
+    op = `sltOp;
+    #1;
+    if(out != 0 || ^out === 1'bx) begin
+      $display("Slt test failed");
+      $display("14 < -32");
+      dutPassed = 0;
+    end
+
+    A = -32;
+    B = 14;
+    op = `sltOp;
+    #1;
+    if(out != 1 || ^out === 1'bx) begin
+      $display("Slt test failed");
+      $display("-32 >= 14");
+      dutPassed = 0;
+    end
+
+    A = 14;
+    B = 14;
+    op = `sltOp;
+    #1;
+    if(out != 0 || ^out === 1'bx) begin
+      $display("Slt test failed");
+      $display("14 < 14");
+      dutPassed = 0;
+    end
+
+    A = -14;
+    B = -14;
+    op = `sltOp;
+    #1;
+    if(out != 0 || ^out === 1'bx) begin
+      $display("Slt test failed");
+      $display("-14 < -14");
+      dutPassed = 0;
+    end
+
+    if(!eq || eq === 1'bx) begin
+      $display("eq tes failed");
+      $display("-14 != -14");
+    end
+    A = -14;
+    B = 14;
+    #1;
+    if(eq || eq === 1'bx) begin
+      $display("eq tes failed");
+      $display("-14 == 14");
+    end
+
+    if(dutPassed) begin
+      $display("DUT passed!");
+    end
+  end
+
+endmodule
diff --git a/alu.v b/alu.v
new file mode 100644
index 0000000..ac189c1
--- /dev/null
+++ b/alu.v
@@ -0,0 +1,28 @@
+//ops: XOR, ADD, SUB, SLT
+`define xorOp 2'b00
+`define addOp 2'b01
+`define subOp 2'b10
+`define sltOp 2'b11
+
+module alu
+  #(
+  parameter width = 32
+  )
+  (output signed [width-1:0] out,
+   output eq,
+   input[1:0] op,
+   input signed [width-1:0] A,
+   input signed [width-1:0] B);
+
+  wire[width-1:0] outputs[4];
+
+  assign outputs[`xorOp] = A^B;
+  assign outputs[`addOp] = A+B;
+  assign outputs[`subOp] = A-B;
+  assign outputs[`sltOp][0] = A<B;
+  assign outputs[`sltOp][width-1:1] = {width{1'b0}};
+  assign eq = (A==B);
+  assign out[width-1:0] = outputs[op][width-1:0];
+
+
+endmodule
diff --git a/asmtest/ackermann.asm b/asmtest/ackermann.asm
new file mode 100644
index 0000000..27e2b93
--- /dev/null
+++ b/asmtest/ackermann.asm
@@ -0,0 +1,68 @@
+#ackermann function: calculates A($t0, $t1)
+#https://en.wikipedia.org/wiki/Ackermann_function
+#will stackoverflow if m or n is greater than 4
+
+addi $t0, $zero, 3 #m = t0
+addi $t1, $zero, 3 #n = t1
+sw   $t0, 4($sp)         #push m
+sw   $t1  8($sp)         #push n
+addi $sp, $sp, 8
+jal ackermann             #ackermann(m, n);
+lw   $t2,   ($sp)         #pop the return value
+addi $sp, $sp, -4
+end:
+j end
+
+ackermann:
+lw   $t0, -4($sp)         # m = arg1
+lw   $t1,  0($sp)         # n = arg2
+addi $sp, $sp, -8              # pop two words
+
+bne  $t0, $zero, continue1# if m != 0 goto continue1
+addi $t2, $t1, 1          # t2 = n + 1
+sw   $t2, 4($sp)          # push return value
+addi $sp, $sp, 4          #push one word
+jr   $ra                  #return t2
+
+continue1:
+bne $t1, $zero, continue2
+#push locals
+sw   $ra,  4($sp)         #push our return address
+addi $t0, $t0, -1         # m = m -1;
+addi $t1, $zero, 1        # n = 1;
+sw   $t0, 8($sp)         #push m
+sw   $t1  12($sp)         #push n
+addi $sp, $sp, 12
+jal ackermann             #ackermann(m, n);
+lw   $t2,   ($sp)         #pop the return value
+lw   $ra, -4($sp)         #pop the return address
+addi $sp, $sp, -8         #pop 2 words
+sw   $t2, 4($sp)          #push return value
+addi $sp, $sp, 4          #push one word
+jr   $ra                  #return 
+continue2:
+#push locals
+sw   $t0,  4($sp)
+sw   $ra,  8($sp)         #push our return address
+addi $t1, $t1, -1         # n = n -1;
+sw   $t0, 12($sp)         #push m
+sw   $t1  16($sp)         #push n
+addi $sp, $sp, 16
+jal ackermann             #ackermann(m, n);
+lw   $t1,   ($sp)         #pop the return value
+lw   $ra, -4($sp)         #pop the return address
+lw   $t0, -8($sp)         #pop m
+addi $sp, $sp, -12        #pop 2 words
+addi $t0, $t0, -1         # n = n -1
+sw   $ra,  4($sp)         #push our return address
+sw   $t0, 8($sp)         #push m
+sw   $t1  12($sp)         #push n
+addi $sp, $sp, 12
+jal ackermann             #ackermann(m, n);
+lw   $t2,   ($sp)         #pop the return value
+lw   $ra, -4($sp)         #pop the return address
+addi $sp, $sp, -8         #pop 2 words
+sw   $t2, 4($sp)          #push return value
+addi $sp, $sp, 4          #push one word
+jr   $ra                  #return 
+
diff --git a/cpu.t.v b/cpu.t.v
new file mode 100644
index 0000000..215a548
--- /dev/null
+++ b/cpu.t.v
@@ -0,0 +1,66 @@
+`include "cpu.v"
+
+module cpuTestBench();
+  reg clk;
+  reg[4:0] regAddr;
+  reg[13:0] memAddr;
+  wire[31:0] regTest;
+  wire[31:0] memTest;
+  wire interrupt;
+  reg[31:0] currentTest;
+  reg[31:0] expectedVals[12];
+  reg[31:0] i;
+  reg dutPassed = 1;
+
+  cpu dut(clk, regAddr, regTest,
+               memAddr, memTest,
+               interrupt);
+  initial begin
+     currentTest = 0;
+     //list of expected test values
+     //For the "source" of the program this test runs on the cpu
+     //see fullTest.asm
+     expectedVals[0] = 15;
+     expectedVals[1] = 20;
+     expectedVals[2] = 25;
+     expectedVals[3] = 30;
+     expectedVals[4] = 35;
+     expectedVals[5] = 40;
+     expectedVals[6] = 45;
+     expectedVals[7] = 9;
+     expectedVals[8] = 27;
+     expectedVals[9] = 3;
+     expectedVals[10] = 1;
+     expectedVals[11] = 0;
+     clk = 0;
+     memAddr = 100;
+     regAddr = 25; //t9
+     i = 0;
+     #5;
+     for(i = 0; i<10000; i = i + 1) begin
+     clk = 1; #5;
+     clk = 0; #5;
+     end
+     #25;
+     if(currentTest != 12) begin
+       $display("Didn't run enough tests!");
+       dutPassed = 0;
+     end
+     if(dutPassed) begin
+       $display("DUT passed!");
+     end
+     $finish();
+  end
+
+  //cpu interrupts every time it is ready to be tested
+  //we use syscall to fire interrupts
+  always @(posedge interrupt) begin
+    if(regTest != expectedVals[currentTest]) begin
+      $display("Failed test %d", currentTest);
+      $display("%d != %d", regTest, expectedVals[currentTest]);
+      dutPassed = 0;
+    end
+    currentTest = currentTest + 1;
+  end
+
+endmodule
diff --git a/cpu.v b/cpu.v
new file mode 100644
index 0000000..44f56c3
--- /dev/null
+++ b/cpu.v
@@ -0,0 +1,260 @@
+`include "alu.v"
+`include "memory.v"
+`include "registerFile.v"
+`define  opLW    6'b100011
+`define  opSW    6'b101011
+`define  opJ     6'b000010
+`define  opRTYPE 6'b000000
+`define  opJAL   6'b000011
+`define  opBNE   6'b000101
+`define  opXORI  6'b001110
+`define  opADDI  6'b001000
+
+`define  fnADD   6'b100000
+`define  fnSUB   6'b100010
+`define  fnJR    6'b001000
+`define  fnSLT   6'b101010
+`define  fnSYS   6'b001100
+
+module cpu
+#(parameter width = 32, addressWidth = 14, regAddressWidth = 5)
+(input clk,
+  input[regAddressWidth-1:0] regTestAddr, output reg[width-1:0] regTest,
+  input[addressWidth-1:0] memTestAddr, output reg[width-1:0] memTest,
+  output reg interrupt);
+
+//used to output debug information at syscall
+reg test;
+
+//initialize registers
+initial begin
+  test <= 0;
+  interrupt <= 0;
+end
+
+//all the wires get defined ahead of time
+//control signals are registers
+wire[width-1:0]         inst_read;
+wire[addressWidth-1:0]  inst_addr;
+
+wire[width-1:0]         mem_read;
+wire[width-1:0]         mem_write;
+reg                     mem_wen;
+wire[addressWidth-1:0]  mem_addr;
+
+wire[width-1:0]        alu_a;
+wire[width-1:0]        alu_b;
+reg[1:0]               alu_op;
+wire                   alu_eq;
+wire[width-1:0]        alu_out;
+
+wire[width-1:0]           reg_portA;
+wire[width-1:0]           reg_portB;
+wire[width-1:0]           reg_write;
+wire[regAddressWidth-1:0] reg_addrA;
+wire[regAddressWidth-1:0] reg_addrB;
+wire[regAddressWidth-1:0] reg_addrW;
+reg                       reg_wen;
+
+reg[addressWidth-1:0]     pc;
+wire[regAddressWidth-1:0] RS;
+wire[regAddressWidth-1:0] RT;
+wire[regAddressWidth-1:0] RD;
+wire[5:0]                 FUNCT;
+wire[15:0]                IMM;
+wire[25:0]                ADDR;
+wire[5:0]                 OP;
+
+//sign extend the immediate
+wire[width-1:0] imm;
+assign imm = {{(width-15){IMM[15]}}, IMM[14:0]};
+
+//A WHOLE LOT OF MULTIPLEXORS
+
+//possible next values of the program counter for a BNE
+wire[addressWidth-1:0] BNE_RESULT_OPTIONS[2];
+assign BNE_RESULT_OPTIONS[0] = pc+(imm<<2)+4;
+assign BNE_RESULT_OPTIONS[1] = pc+4;
+wire[addressWidth-1:0] bneResult;
+assign bneResult = BNE_RESULT_OPTIONS[alu_eq];
+
+//possible next values of the program counter
+wire[addressWidth-1:0] PC_NEXT_OPTIONS[4];
+assign PC_NEXT_OPTIONS[0] = pc+4;                            //Normal execution
+assign PC_NEXT_OPTIONS[1] = bneResult;                       //BNE
+assign PC_NEXT_OPTIONS[2] = (ADDR<<2);    //J, JAL
+assign PC_NEXT_OPTIONS[3] = reg_portA[addressWidth-1:0];     //JR
+reg[1:0] pcNextOption;
+wire[addressWidth-1:0] pcNext;
+assign pcNext = PC_NEXT_OPTIONS[pcNextOption];
+
+
+//we only address memory based on alue output
+wire[addressWidth-1:0] MEM_ADDR_OPTIONS[2];
+assign MEM_ADDR_OPTIONS[0] = alu_out;
+assign MEM_ADDR_OPTIONS[1] = memTestAddr;
+assign mem_addr  = MEM_ADDR_OPTIONS[test]; //LW, SW
+assign mem_write = reg_portB;
+
+wire[width-1:0] REG_WRITE_OPTIONS[3];
+assign REG_WRITE_OPTIONS[0] = alu_out;  //XORI?, ADDI?, SLT,
+assign REG_WRITE_OPTIONS[1] = mem_read; //LW
+assign REG_WRITE_OPTIONS[2] = pc+4;     //JAL
+reg[1:0] regWriteOption;
+assign reg_write = REG_WRITE_OPTIONS[regWriteOption];
+
+wire[regAddressWidth-1:0] REG_WRITE_ADDR_OPTIONS[3];
+assign REG_WRITE_ADDR_OPTIONS[0] = RD; //XOR, ADD, SLT
+assign REG_WRITE_ADDR_OPTIONS[1] = RT; //LW, XORI, ADDI
+assign REG_WRITE_ADDR_OPTIONS[2] = 31; //JAL
+reg[1:0] regWriteAddrOption;
+assign reg_addrW = REG_WRITE_ADDR_OPTIONS[regWriteAddrOption];
+
+wire[regAddressWidth-1:0] REG_ADDR_A_OPTS[2];
+assign REG_ADDR_A_OPTS[0] = RS;
+assign REG_ADDR_A_OPTS[1] = regTestAddr;
+
+assign reg_addrA = REG_ADDR_A_OPTS[test];
+assign reg_addrB = RT;
+
+assign alu_a = reg_portA;
+wire[width-1:0] ALU_B_OPTIONS[2];
+assign ALU_B_OPTIONS[0] = reg_portB; //XOR, ADD, SLT
+assign ALU_B_OPTIONS[1] = imm;       //XORI, ADDI, LW, SW
+reg aluBOption;
+assign alu_b = ALU_B_OPTIONS[aluBOption];
+
+assign inst_addr = pc;
+assign OP = inst_read[31:26];
+assign RS = inst_read[25:21];
+assign RT = inst_read[20:16];
+assign RD = inst_read[15:11];
+assign FUNCT = inst_read[5:0];
+assign IMM = inst_read[15:0];
+assign ADDR = inst_read[25:0];
+
+//Giant lookup table of control signals
+always @ (OP or FUNCT) begin
+  case(OP)
+    `opLW: begin
+      alu_op             <= `addOp;
+      mem_wen            <= 0;
+      reg_wen            <= 1; //write to reg
+      regWriteOption     <= 1; //write mem_read to reg
+      regWriteAddrOption <= 1; //write to reg[rt]
+      aluBOption         <= 1; //use imm
+      pcNextOption       <= 0; //normal execution
+    end
+    `opSW: begin
+      alu_op             <= `addOp;
+      mem_wen            <= 1; //write to mem
+      reg_wen            <= 0;
+      aluBOption         <= 1; //use imm
+      pcNextOption       <= 0; //normal execution
+    end
+    `opJ: begin
+      mem_wen            <= 0; //write to nothing
+      reg_wen            <= 0;
+      pcNextOption       <= 2; //jump
+    end
+    `opJAL: begin
+      mem_wen            <= 0;
+      reg_wen            <= 1; //write to reg
+      regWriteOption     <= 2; //write pc+4 to reg
+      regWriteAddrOption <= 2; //write to reg[31]
+      pcNextOption       <= 2; //jump
+    end
+    `opBNE: begin
+      mem_wen            <= 0;
+      reg_wen            <= 0; //write to nothing
+      aluBOption         <= 0; //use rt
+      pcNextOption       <= 1; //branch execution
+    end
+    `opXORI: begin
+      alu_op             <= `xorOp;
+      mem_wen            <= 0;
+      reg_wen            <= 1; //write to reg
+      regWriteOption     <= 0; //write alu_out to reg
+      regWriteAddrOption <= 1; //write to reg[rt]
+      aluBOption         <= 1; //use imm
+      pcNextOption       <= 0; //normal execution
+    end
+    `opADDI: begin
+      alu_op             <= `addOp;
+      mem_wen            <= 0;
+      reg_wen            <= 1; //write to reg
+      regWriteOption     <= 0; //write alu_out to reg
+      regWriteAddrOption <= 1; //write to reg[rt]
+      aluBOption         <= 1; //use imm
+      pcNextOption       <= 0; //normal execution
+    end
+    `opRTYPE: begin
+      case(FUNCT)
+        `fnADD: begin
+          alu_op             <= `addOp;
+          mem_wen            <= 0;
+          reg_wen            <= 1; //write to reg
+          regWriteOption     <= 0; //write alu_out to reg
+          regWriteAddrOption <= 0; //write to reg[rb]
+          aluBOption         <= 0; //use rb
+          pcNextOption       <= 0; //normal execution
+        end
+        `fnSUB: begin
+          alu_op             <= `subOp;
+          mem_wen            <= 0;
+          reg_wen            <= 1; //write to reg
+          regWriteOption     <= 0; //write alu_out to reg
+          regWriteAddrOption <= 0; //write to reg[rb]
+          aluBOption         <= 0; //use rb
+          pcNextOption       <= 0; //normal execution
+        end
+        `fnJR: begin
+          mem_wen            <=0;
+          reg_wen            <=0; //write to nothing
+          pcNextOption       <=3; //jump to reg[rs]
+        end
+        `fnSLT: begin
+          alu_op             <= `sltOp;
+          mem_wen            <= 0;
+          reg_wen            <= 1; //write to reg
+          regWriteOption     <= 0; //write alu_out to reg
+          regWriteAddrOption <= 0; //write to reg[rb]
+          aluBOption         <= 0; //use rb
+          pcNextOption       <= 0; //normal execution
+        end
+        `fnSYS: begin
+          mem_wen <= 0;
+          reg_wen <= 0;
+          pcNextOption <= 0;
+          test <= 1;
+          #1;
+          regTest <= reg_portA;
+          memTest <= mem_read;
+          #1;
+          interrupt <= 1;
+          #1;
+          test <= 0;
+          interrupt <= 0;
+        end
+      endcase
+    end
+  endcase
+end
+
+//the meat and potatos
+memory mem(clk, mem_read, mem_addr, mem_wen, mem_write);
+memory inst(clk, inst_read, inst_addr, 1'b0, 32'b0);
+alu    ex(alu_out, alu_eq, alu_op, alu_a, alu_b);
+registerFile regs(reg_portA, reg_portB, reg_write, reg_addrA, reg_addrB, reg_addrW, reg_wen, clk);
+
+//advance pc
+always @(posedge clk) begin
+  pc <= pcNext;
+end
+
+//initialize pc
+initial begin
+  pc = 0;
+end
+
+endmodule
diff --git a/fullTest.asm b/fullTest.asm
new file mode 100644
index 0000000..570dc31
--- /dev/null
+++ b/fullTest.asm
@@ -0,0 +1,67 @@
+#addi 0
+addi $t0, $zero, 10
+addi $t9, $t0, 5
+syscall #15 0
+#sw,lw 1
+addi $t1, $zero, 20
+sw   $t1, 0($sp)
+lw   $t9, 0($sp)
+syscall #20 1
+#j 2
+addi $t9, $zero, 25
+j jumpOver
+addi $t9, $zero, 50
+jumpOver:
+syscall #25 2
+#jal 4
+jal jumpAndLink
+add $t9, $zero, 35
+syscall #35 4
+j jumpPast
+jumpAndLink:
+#jr 3
+add $t9, $zero, 30
+syscall #30 3
+jr $ra
+jumpPast:
+#bne 5 6
+addi $t0, $zero, 10
+addi $t1, $zero, 11
+addi $t9, $zero, 40
+bne $t0, $t1, takenBranch
+addi $t9, $zero, 50
+addi $t8, $zero, 10
+takenBranch:
+syscall #40 5
+addi $t0, $zero, 10
+addi $t1, $zero, 10
+addi $t9, $zero, 50
+bne $t0, $t1, untakenBranch
+addi $t9, $zero, 45
+untakenBranch:
+syscall #45 6
+#xori 7
+addi $t0, $zero, 0xC
+xori $t9, $t0,   0x05
+syscall #9 7
+#add 8
+addi $t0, $zero, 12
+addi $t1, $zero, 15
+add $t9, $t0, $t1
+syscall #27 8
+#sub 9
+addi $t0, $zero, 15
+addi $t1, $zero, 12
+sub $t9, $t0, $t1
+syscall #3 9
+#slt 10 11
+addi $t0, $zero, 12
+addi $t1, $zero, 15
+slt $t9, $t0, $t1
+syscall #1 10
+addi $t0, $zero, 15
+addi $t1, $zero, 12
+slt $t9, $t0, $t1
+syscall #0 11
+end:
+j end
diff --git a/memory.t.v b/memory.t.v
new file mode 100644
index 0000000..6201265
--- /dev/null
+++ b/memory.t.v
@@ -0,0 +1,71 @@
+`include "memory.v"
+module programMemoryTestBench
+  ();
+   wire [31:0]dataOut;
+   reg [31:0] dataIn;
+   reg 	      writeEnable;
+   reg [13:0] address;
+   reg 	     Clk;
+   reg 	     dutpassed;
+
+   always #10 Clk = !Clk;
+
+   defparam dut.data = "testmemory.dat";
+   
+   memory dut
+   (
+	      .clk(Clk),
+	      .dataOut(dataOut),
+	      .dataIn(dataIn),
+	      .writeEnable(writeEnable),
+	      .address(address));
+
+   initial begin
+      //setup initial values
+      Clk = 0;
+      dutpassed = 1;
+
+      //Test Case 0: Read First Instruction
+      address = 0;
+      #20;//wait for clock
+      if(dataOut != 32'hDEADBEEF) begin
+        $display("Test Case 0 Failed: first instruction not 0xDEADBEEF, %h",dataOut);
+        dutpassed = 0;
+      end
+
+      //Test Case 1: Read Second Instruction
+      address = 4;
+      #20;//wait for clock
+      if(dataOut != 32'h00c0ffee) begin
+        $display("Test Case 1 Failed: second instruction not 0x00c0ffee");
+        dutpassed = 0;
+      end
+
+      //Test Case 2: Read Third Instruction
+      address = 8;
+      #20;//wait for clock
+      if(dataOut != 32'h00bada55) begin
+        $display("Test Case 2 Failed: third instruction not 0x00bada55");
+        dutpassed = 0;
+      end
+
+      //Test Case 3: Write and Read
+      //Write 0x1337FADE to address 16 and check that value is written
+      address = 16;
+      writeEnable = 1;
+      dataIn = 32'h1337FADE;
+      #20;//wait for clock
+      if(dataOut != 32'h1337FADE) begin
+        $display("Test Case 3 Failed: 0x1337FADE not read from address 16");
+        dutpassed = 0;
+      end
+
+      $display("DUT Passed");
+      $finish();
+   end
+   always @(negedge dutpassed) begin
+      $display("DUT Failed");
+      $finish();
+
+   end
+endmodule
diff --git a/memory.v b/memory.v
new file mode 100644
index 0000000..aad55b4
--- /dev/null
+++ b/memory.v
@@ -0,0 +1,32 @@
+module memory
+  #(
+    parameter width = 8,
+    parameter wordlength = 4,
+    parameter addresswidth = 14,
+    parameter depth = 2**addresswidth,
+    parameter data = "testmem.dat"
+    )
+   (
+    input 		     clk,
+    output [width*wordlength-1:0]   dataOut,
+    input [addresswidth-1:0] address,
+    input 		     writeEnable,
+    input [width*wordlength-1:0] 	     dataIn
+    );
+
+   reg [width-1:0] 	     memory [depth-1:0];
+
+   initial $readmemh(data, memory);
+   //generate code to read and write one word of data and from memory 
+   genvar 		     i;
+   generate
+      for (i = 0; i < wordlength; i = i+1) begin
+        always @(posedge clk) begin
+          if(writeEnable) begin
+             memory[address+wordlength-1-i] <= dataIn[i*width+:width];
+          end
+        end // always @ (posedge clk)
+      assign dataOut[(wordlength-i-1)*width+:width] = memory[address+i];
+      end
+   endgenerate
+   endmodule
diff --git a/registerFile.t.v b/registerFile.t.v
new file mode 100644
index 0000000..81b3de3
--- /dev/null
+++ b/registerFile.t.v
@@ -0,0 +1,84 @@
+`include "registerFile.v"
+
+module registerFileTestBench
+  ();
+
+  wire [31:0] ReadData1;
+  wire [31:0] ReadData2;
+   reg [31:0] WriteData;
+   reg [4:0]  ReadReg1;
+   reg [4:0] ReadReg2;
+   reg [4:0] WriteReg;
+   reg 	     RegWrite;
+   reg 	     Clk;
+   reg 	     dutpassed;
+
+   always #10 Clk = !Clk;
+
+
+   registerFile dut(
+		    .ReadRegister1(ReadReg1),
+		    .ReadRegister2(ReadReg2),
+		    .WriteData(WriteData),
+		    .ReadData1(ReadData1),
+		    .ReadData2(ReadData2),
+		    .WriteRegister(WriteReg),
+		    .RegWrite(RegWrite),
+		    .Clk(Clk));
+
+   initial begin
+      //setup initial values
+      Clk = 0;
+      dutpassed = 1;
+
+      //Test Case 0: Zero Register
+      //Try writing non-zero value to zero register and check that value is still zero
+      WriteReg = 0;
+      RegWrite = 1;
+      WriteData = 50;
+      #20;//wait for clock
+      ReadReg1 = 0;
+      #20;//wait for clock
+      if(ReadData1 != 0) begin
+	 $display("Test Case 0 Failed: Zero register gave non-zero value");
+	 dutpassed = 0;
+      end
+
+      //Test Case 1: Write and Read
+      //Write 0xDEADBEEF to register 17 and check that value is written
+      WriteReg = 17;
+      WriteData = 32'hDEADBEEF;
+      #20;//wait for clock
+      ReadReg2 = 17;
+      #20;//wait for clock
+      if(ReadData2 != 32'hDEADBEEF) begin
+	 $display("Test Case 1 Failed: 0xDEADBEEF not read from register 17");
+	 dutpassed = 0;
+      end
+
+      //Test Case 2: Check Write Enable
+      //Attempt to Write 0x00BADA55 to register 23 and check that value is not written
+      RegWrite = 0;
+      WriteReg = 23;
+      WriteData = 32'h00BADA55;
+      #20;
+      ReadReg1 = 23;
+      #20;
+      if(ReadData1 == 32'h00BADA55) begin
+	 $display("Test Case 2 Failed: 0x00BADA55 read from register 23");
+	 dutpassed = 0;
+      end
+
+
+      $display("DUT Passed");
+      $finish();
+
+   end // initial begin
+
+   always @(negedge dutpassed) begin
+      $display("DUT Failed");
+      $finish();
+
+   end
+
+endmodule
diff --git a/registerFile.v b/registerFile.v
new file mode 100644
index 0000000..db07a80
--- /dev/null
+++ b/registerFile.v
@@ -0,0 +1,32 @@
+module registerFile
+ #(
+    parameter width = 32,
+    parameter addresswidth = 5,
+    parameter depth = 2**addresswidth
+    )
+  (
+   output [width-1:0]   ReadData1,
+   output [width-1:0]   ReadData2,
+   input [width-1:0] 	    WriteData,
+   input [addresswidth-1:0] ReadRegister1,
+   input [addresswidth-1:0] ReadRegister2,
+   input [addresswidth-1:0] WriteRegister,
+   input 		    RegWrite,
+   input 		    Clk
+   );
+   //setup registers
+   reg [width-1:0] registers [depth-1:0];
+   initial begin
+      registers[0][width-1:0]   <= 0;
+      registers[29][width-1:0]  <= 32'h3ffc;
+   end
+
+   //do register operations on clock edges
+   always @(posedge Clk) begin
+      if(RegWrite && WriteRegister != 0) begin
+	       registers[WriteRegister] <= WriteData;
+      end
+   end // always @ (posedge Clk)
+   assign ReadData1 = registers[ReadRegister1];
+   assign ReadData2 = registers[ReadRegister2];
+endmodule
diff --git a/split.py b/split.py
new file mode 100644
index 0000000..fb106d0
--- /dev/null
+++ b/split.py
@@ -0,0 +1,10 @@
+f = open("test.txt", "r")
+o = open("testmem.dat", "w")
+lines = f.readlines()
+for s in lines:
+    for i in range(4):
+        o.write(s[i*2:i*2+2])
+        o.write("\n")
+
+f.close()
+o.close
diff --git a/test.txt b/test.txt
new file mode 100644
index 0000000..ed61fde
--- /dev/null
+++ b/test.txt
@@ -0,0 +1,51 @@
+2008000a
+21190005
+0000000c
+20090014
+afa90000
+8fb90000
+0000000c
+20190019
+0800000a
+20190032
+0000000c
+0c00000f
+20190023
+0000000c
+08000012
+2019001e
+0000000c
+03e00008
+2008000a
+2009000b
+20190028
+15090002
+20190032
+2018000a
+0000000c
+2008000a
+2009000a
+20190032
+15090001
+2019002d
+0000000c
+2008000c
+39190005
+0000000c
+2008000c
+2009000f
+0109c820
+0000000c
+2008000f
+2009000c
+0109c822
+0000000c
+2008000c
+2009000f
+0109c82a
+0000000c
+2008000f
+2009000c
+0109c82a
+0000000c
+08000032
diff --git a/testmem.dat b/testmem.dat
new file mode 100644
index 0000000..327305f
--- /dev/null
+++ b/testmem.dat
@@ -0,0 +1,204 @@
+20
+08
+00
+0a
+21
+19
+00
+05
+00
+00
+00
+0c
+20
+09
+00
+14
+af
+a9
+00
+00
+8f
+b9
+00
+00
+00
+00
+00
+0c
+20
+19
+00
+19
+08
+00
+00
+0a
+20
+19
+00
+32
+00
+00
+00
+0c
+0c
+00
+00
+0f
+20
+19
+00
+23
+00
+00
+00
+0c
+08
+00
+00
+12
+20
+19
+00
+1e
+00
+00
+00
+0c
+03
+e0
+00
+08
+20
+08
+00
+0a
+20
+09
+00
+0b
+20
+19
+00
+28
+15
+09
+00
+02
+20
+19
+00
+32
+20
+18
+00
+0a
+00
+00
+00
+0c
+20
+08
+00
+0a
+20
+09
+00
+0a
+20
+19
+00
+32
+15
+09
+00
+01
+20
+19
+00
+2d
+00
+00
+00
+0c
+20
+08
+00
+0c
+39
+19
+00
+05
+00
+00
+00
+0c
+20
+08
+00
+0c
+20
+09
+00
+0f
+01
+09
+c8
+20
+00
+00
+00
+0c
+20
+08
+00
+0f
+20
+09
+00
+0c
+01
+09
+c8
+22
+00
+00
+00
+0c
+20
+08
+00
+0c
+20
+09
+00
+0f
+01
+09
+c8
+2a
+00
+00
+00
+0c
+20
+08
+00
+0f
+20
+09
+00
+0c
+01
+09
+c8
+2a
+00
+00
+00
+0c
+08
+00
+00
+32
diff --git a/work_plan.txt b/work_plan.txt
new file mode 100644
index 0000000..94340e4
--- /dev/null
+++ b/work_plan.txt
@@ -0,0 +1,19 @@
+Tobias Shapinsky
+Henry Rachootin
+Single Cycle CPU
+
+-Throughout the week of 11/06-
+ALU (2hrs) - Henry 
+Register File (2hrs) - Toby
+Data Memory (1hr) - Henry
+Program Memory (2hrs) - Toby
+
+-Throughout the week of 11/13-
+Decoder (2hrs) - Henry
+Synthesis (5hrs) - Both
+
+-On Monday-
+Test Programs (1hr) - Both
+
+-On Thursday-
+Write Report (4hrs) - Both