diff --git a/Lab 3 Report.pdf b/Lab 3 Report.pdf new file mode 100644 index 0000000..2ab6031 Binary files /dev/null and b/Lab 3 Report.pdf differ diff --git a/cpu.v b/cpu.v index 0ca0cc5..5cecf9a 100644 --- a/cpu.v +++ b/cpu.v @@ -4,6 +4,7 @@ `include "programCounter.v" `include "regfile.v" `include "alu.v" +`include "signExtended.v" module cpu ( @@ -11,7 +12,7 @@ module cpu ); //PCSel mux -reg[1:0] PCSel; +wire[1:0] PCSel; //Program counter wire[31:0] PCInput; @@ -19,17 +20,17 @@ wire[31:0] PCOutput; wire[3:0] PCLastFour; //AdderMux -wire[31:0] adderMux1Out; -wire[31:0] adderMux2Out; -reg AdderValControl; +wire[31:0] adderMuxOut; //Adder +wire[31:0] adderOut1; wire[31:0] adderOut; //instruction memory wire[31:0] instrMemOut; wire[25:0] jumpAddress; wire[15:0] instrMemImm; +wire[31:0] extendedInstrMemImm; wire[5:0] opCode; wire[4:0] rs; wire[4:0] rt; @@ -46,20 +47,20 @@ assign functionCode = instrMemOut[5:0]; //registerMux wire[31:0] registerMux1Out; wire[4:0] registerMux2Out; -reg[1:0] RegDataWrSel; -reg[1:0] RegAddrWrSel; +wire[1:0] RegDataWrSel; +wire[1:0] RegAddrWrSel; //register wire[31:0] regOut1; wire[31:0] regOut2; -reg RegWrEn; +wire RegWrEn; //branchControlMux wire branchControlOut; -reg BranchControl; +wire BranchControl; //alu Mux -reg ALUImm; +wire ALUImm; wire[31:0] aluMuxOut; //alu @@ -67,145 +68,30 @@ wire[31:0] aluOut; wire carryout; wire zero; wire overflow; -reg[2:0] command; +wire[2:0] command; //Data Memory wire[31:0] dataMemOut; -reg MemWrEn; +wire MemWrEn; -mux4input PCSelMux(PCInput, PCSel, {PCLastFour, jumpAddress, 2'b00}, regOut1, adderOut, adderOut); +mux4input CSelMux(PCInput, PCSel, {PCLastFour, jumpAddress, 2'b00}, regOut1, adderOut, adderOut); programCounter PC(PCOutput, PCLastFour, PCInput, 1, clk); -mux2input adderMux1(adderMux1Out, branchControlOut, instrMemImm, PCOutput); -mux2input adderMux2(adderMux2Out, AdderValControl, 32'd4, 32'd8); -ALU adder(.result(adderOut), .operandA(adderMux1Out), .operandB(adderMux2Out), .command(3'd0)); -instrMemory instrMem(.clk(clk), .Addr(PCOutput), .DataOut(instrMemOut), .regWE(0)); +signExtended extend(extendedInstrMemImm, instrMemImm); +mux2input adderMux(adderMuxOut, branchControlOut, extendedInstrMemImm[29:0]<<2, 0); +ALU pcAdder1(.result(adderOut1), .operandA(PCOutput), .operandB(32'd4), .command(3'd0)); +ALU pcAdder2(.result(adderOut), .operandA(adderMuxOut), .operandB(adderOut1), .command(3'd0)); +instrMemory instrMem(.clk(clk), .Addr(PCOutput[9:0]), .DataOut(instrMemOut), + .regWE(0), .RegWrEn(RegWrEn), .MemWrEn(MemWrEn), .PCSel(PCSel), .RegDataWrSel(RegDataWrSel), + .RegAddrWrSel(RegAddrWrSel), .BranchControl(BranchControl), .ALUImm(ALUImm), .command(command)); mux4input registerMux1(.out(registerMux1Out), .address(RegDataWrSel), .in0(aluOut), .in1(dataMemOut), .in3(adderOut)); -mux4input registerMux2(.out(registerMux2Out), .address(RegAddrWrSel), .in0(rd), .in1(rt), .in3(5'd31)); -regfile register(.ReadData1(regOut1), .ReadData2(regOut2), .WriteData(registerMux1Out), .ReadRegister1(rs), .ReadRegister2(rt), .WriteRegister(registerMux2Out), .RegWrite(RegWrEn), .Clk(clk)); -mux2input aluMux(aluMuxOut, ALUImm, regOut2, instrMemImm); - -always @(posedge clk) begin - //Decoding op code to alu operation command - if (opCode == 6'h23) begin //lw - RegWrEn <= 1'b1; - MemWrEn <= 1'b0; - PCSel <= 2'b10; - AdderValControl <= 1'b0; - RegDataWrSel <= 2'b01; - RegAddrWrSel <= 2'b01; - BranchControl <= 1'b1; - ALUImm <= 1'b1; - end - if (opCode == 6'h2b) begin //sw - RegWrEn <= 1'b0; - MemWrEn <= 1'b1; - PCSel <= 2'b10; - AdderValControl <= 1'b0; - RegDataWrSel <= 2'b01; - RegAddrWrSel <= 2'b01; - BranchControl <= 1'b1; - ALUImm <= 1'b1; - end - if (opCode == 6'h2) begin //j - RegWrEn <= 1'b0; - MemWrEn <= 1'b0; - PCSel <= 2'b00; - AdderValControl <= 1'b0; - RegDataWrSel <= 2'b01; - RegAddrWrSel <= 2'b01; - BranchControl <= 1'b1; - ALUImm <= 1'b1; - end - if (opCode == 6'h0 && functionCode == 6'h08) begin //jr - RegWrEn <= 1'b0; - MemWrEn <= 1'b0; - PCSel <= 2'b01; - AdderValControl <= 1'b0; - RegDataWrSel <= 2'b01; - RegAddrWrSel <= 2'b01; - BranchControl <= 1'b1; - ALUImm <= 1'b1; - end - if (opCode == 6'h3) begin //jal - RegWrEn <= 1'b1; - MemWrEn <= 1'b0; - PCSel <= 2'b00; - AdderValControl <= 1'b1; - RegDataWrSel <= 2'b11; - RegAddrWrSel <= 2'b11; - BranchControl <= 1'b1; - ALUImm <= 1'b1; - end - if (opCode == 6'd5) begin //bne - RegWrEn <= 1'b0; - MemWrEn <= 1'b0; - PCSel <= 2'b10; - AdderValControl <= 1'b0; - RegDataWrSel <= 2'b01; - RegAddrWrSel <= 2'b01; - BranchControl <= 1'b0; - ALUImm <= 1'b1; - command <= 3'd1; - end - if (opCode == 6'd14) begin //xori - command <= 3'd2; - RegWrEn <= 1'b1; - MemWrEn <= 1'b0; - PCSel <= 2'b10; - AdderValControl <= 1'b0; - RegDataWrSel <= 2'b00; - RegAddrWrSel <= 2'b01; - BranchControl <= 1'b1; - ALUImm <= 1'b1; - end - if (opCode == 6'd8) begin //addi - command <= 3'd0; - RegWrEn <= 1'b1; - MemWrEn <= 1'b0; - PCSel <= 2'b10; - AdderValControl <= 1'b0; - RegDataWrSel <= 2'b00; - RegAddrWrSel <= 2'b01; - BranchControl <= 1'b1; - ALUImm <= 1'b1; - end - if (opCode == 6'd0 && functionCode == 6'h20) begin //add - command <= 3'd0; - RegWrEn <= 1'b1; - MemWrEn <= 1'b0; - PCSel <= 2'b10; - AdderValControl <= 1'b0; - RegDataWrSel <= 2'b00; - RegAddrWrSel <= 2'b00; - BranchControl <= 1'b1; - ALUImm <= 1'b0; - end - if (opCode == 6'd0 && functionCode == 6'h22) begin //sub - command <= 3'd1; - RegWrEn <= 1'b1; - MemWrEn <= 1'b0; - PCSel <= 2'b10; - AdderValControl <= 1'b0; - RegDataWrSel <= 2'b00; - RegAddrWrSel <= 2'b00; - BranchControl <= 1'b1; - ALUImm <= 1'b0; - end - if (opCode == 6'd0 && functionCode == 6'h2a) begin //slt - command <= 3'd3; - RegWrEn <= 1'b1; - MemWrEn <= 1'b0; - PCSel <= 2'b10; - AdderValControl <= 1'b0; - RegDataWrSel <= 2'b00; - RegAddrWrSel <= 2'b00; - BranchControl <= 1'b1; - ALUImm <= 1'b0; - end -end - -ALU alu(.result(aluOut), .carryout(carryout), .zero(zero), .overflow(overflow), .operandA(regOut1), .operandB(aluMuxOut), .command(command)); -mux2input branchControlMux(branchControlOut, BranchControl, zero, 1'b0); -dataMemory dataMem(.clk(clk), .regWE(MemWrEn), .Addr(aluOut), .DataIn(regOut2), .DataOut(dataMemOut)); +mux4input #(5) registerMux2(.out(registerMux2Out), .address(RegAddrWrSel), .in0(rd), .in1(rt), .in3(5'd31)); +regfile register(.ReadData1(regOut1), .ReadData2(regOut2), .WriteData(registerMux1Out), .ReadRegister1(rs), .ReadRegister2(rt), + .WriteRegister(registerMux2Out), .RegWrite(RegWrEn), .Clk(clk)); +mux2input aluMux(aluMuxOut, ALUImm, regOut2, extendedInstrMemImm); + +ALU alu(.result(aluOut), .carryout(carryout), .zero(zero), .overflow(overflow), + .operandA(regOut1), .operandB(aluMuxOut), .command(command)); +mux2input #(1) branchControlMux(branchControlOut, BranchControl, zero, 1'b1); +dataMemory dataMem(.clk(clk), .regWE(MemWrEn), .Addr(aluOut[9:0]), .DataIn(regOut2), .DataOut(dataMemOut)); endmodule diff --git a/dataMemory.v b/dataMemory.v index 0f547f6..5b6e21c 100644 --- a/dataMemory.v +++ b/dataMemory.v @@ -14,7 +14,7 @@ module dataMemory end end - initial $readmemh("dataMemory.dat", mem); + //initial $readmemh("dataMemory.dat", mem); assign DataOut = mem[Addr]; endmodule diff --git a/instrMemory.v b/instrMemory.v index e1778b2..bf350c3 100644 --- a/instrMemory.v +++ b/instrMemory.v @@ -1,10 +1,19 @@ //Instruction memory module instrMemory ( - input clk, regWE, + input clk, regWE, // clock, register Write Enable input[9:0] Addr, input[31:0] DataIn, - output[31:0] DataOut + output[31:0] DataOut, + // control signal + output reg RegWrEn, + output reg MemWrEn, + output reg[1:0] PCSel, + output reg[1:0] RegDataWrSel, + output reg[1:0] RegAddrWrSel, + output reg BranchControl, + output reg ALUImm, + output reg[2:0] command ); reg [31:0] mem[1023:0]; @@ -15,7 +24,121 @@ module instrMemory end end - initial $readmemh("instrMemory.dat", mem); - - assign DataOut = mem[Addr]; + initial $readmemh("subTest.dat", mem); + + initial begin + BranchControl = 1'b1; + PCSel = 2'b10; + end + + assign DataOut = mem[Addr>>2]; + + always @(negedge clk) begin + //Decoding op code to alu operation command + if (DataOut[31:26] == 6'h23) begin //lw + RegWrEn <= 1'b1; + MemWrEn <= 1'b0; + PCSel <= 2'b10; + RegDataWrSel <= 2'b01; + RegAddrWrSel <= 2'b01; + BranchControl <= 1'b1; + ALUImm <= 1'b1; + end + if (DataOut[31:26] == 6'h2b) begin //sw + RegWrEn <= 1'b0; + MemWrEn <= 1'b1; + PCSel <= 2'b10; + RegDataWrSel <= 2'b01; + RegAddrWrSel <= 2'b01; + BranchControl <= 1'b1; + ALUImm <= 1'b1; + end + if (DataOut[31:26] == 6'h2) begin //j + RegWrEn <= 1'b0; + MemWrEn <= 1'b0; + PCSel <= 2'b00; + RegDataWrSel <= 2'b01; + RegAddrWrSel <= 2'b01; + BranchControl <= 1'b1; + ALUImm <= 1'b1; + end + if (DataOut[31:26] == 6'h0 && DataOut[5:0] == 6'h08) begin //jr + RegWrEn <= 1'b0; + MemWrEn <= 1'b0; + PCSel <= 2'b01; + RegDataWrSel <= 2'b01; + RegAddrWrSel <= 2'b01; + BranchControl <= 1'b1; + ALUImm <= 1'b1; + end + if (DataOut[31:26] == 6'h3) begin //jal + RegWrEn <= 1'b1; + MemWrEn <= 1'b0; + PCSel <= 2'b00; + RegDataWrSel <= 2'b11; + RegAddrWrSel <= 2'b11; + BranchControl <= 1'b1; + ALUImm <= 1'b1; + end + if (DataOut[31:26] == 6'd5) begin //bne + command <= 3'd1; + RegWrEn <= 1'b0; + MemWrEn <= 1'b0; + PCSel <= 2'b10; + RegDataWrSel <= 2'b01; + RegAddrWrSel <= 2'b01; + BranchControl <= 1'b0; + ALUImm <= 1'b0; + end + if (DataOut[31:26] == 6'd14) begin //xori + command <= 3'd2; + RegWrEn <= 1'b1; + MemWrEn <= 1'b0; + PCSel <= 2'b10; + RegDataWrSel <= 2'b00; + RegAddrWrSel <= 2'b01; + BranchControl <= 1'b1; + ALUImm <= 1'b1; + end + if (DataOut[31:26] == 6'd8) begin //addi + command <= 3'd0; + RegWrEn <= 1'b1; + MemWrEn <= 1'b0; + PCSel <= 2'b10; + RegDataWrSel <= 2'b00; + RegAddrWrSel <= 2'b01; + BranchControl <= 1'b1; + ALUImm <= 1'b1; + end + if (DataOut[31:26] == 6'd0 && DataOut[5:0] == 6'h20) begin //add + command <= 3'd0; + RegWrEn <= 1'b1; + MemWrEn <= 1'b0; + PCSel <= 2'b10; + RegDataWrSel <= 2'b00; + RegAddrWrSel <= 2'b00; + BranchControl <= 1'b1; + ALUImm <= 1'b0; + end + if (DataOut[31:26] == 6'd0 && DataOut[5:0] == 6'h22) begin //sub + command <= 3'd1; + RegWrEn <= 1'b1; + MemWrEn <= 1'b0; + PCSel <= 2'b10; + RegDataWrSel <= 2'b00; + RegAddrWrSel <= 2'b00; + BranchControl <= 1'b1; + ALUImm <= 1'b0; + end + if (DataOut[31:26] == 6'd0 && DataOut[5:0] == 6'h2a) begin //slt + command <= 3'd3; + RegWrEn <= 1'b1; + MemWrEn <= 1'b0; + PCSel <= 2'b10; + RegDataWrSel <= 2'b00; + RegAddrWrSel <= 2'b00; + BranchControl <= 1'b1; + ALUImm <= 1'b0; + end + end endmodule diff --git a/programCounter.v b/programCounter.v index 7128cd8..1347913 100644 --- a/programCounter.v +++ b/programCounter.v @@ -7,6 +7,9 @@ input[31:0] newCount, input wrenable, input clk ); + initial begin + currentCount = -4; + end always @(posedge clk) begin if(wrenable) begin diff --git a/regfile.v b/regfile.v index d03dbc0..95c9089 100644 --- a/regfile.v +++ b/regfile.v @@ -38,12 +38,22 @@ input Clk // Clock (Positive Edge Triggered) generate genvar i; for (i=1; i<32; i=i+1) begin: generate_register - register register32bit( - .q(regout[i]), - .d(WriteData), - .wrenable(wrenable[i]), - .clk(Clk) - ); + if (i == 29) begin //initialize $sp(stack point) value to 0x00003ffc + register #(32, 16380) register32bit( + .q(regout[i]), + .d(WriteData), + .wrenable(wrenable[i]), + .clk(Clk) + ); + end + else begin + register register32bit( + .q(regout[i]), + .d(WriteData), + .wrenable(wrenable[i]), + .clk(Clk) + ); + end end endgenerate @@ -61,5 +71,4 @@ input Clk // Clock (Positive Edge Triggered) regout[30], regout[31] ); - endmodule diff --git a/register.v b/register.v index 8141432..17f14e1 100644 --- a/register.v +++ b/register.v @@ -2,7 +2,8 @@ module register #( - parameter width = 32 + parameter width = 32, + parameter initialValue = 32'h00000000 ) ( output reg[width-1:0] q, // data output @@ -10,9 +11,13 @@ module register input wrenable, // write enable input clk // clock ); + initial begin + q <= initialValue; + end + always @(posedge clk) begin if(wrenable) begin - q = d; + q <= d; end end endmodule @@ -28,8 +33,6 @@ module registerZero input clk // clock ); always @(posedge clk) begin - if(wrenable) begin - q = 0; - end + q <= 0; end endmodule \ No newline at end of file diff --git a/signExtended.t b/signExtended.t new file mode 100755 index 0000000..d4e33b3 --- /dev/null +++ b/signExtended.t @@ -0,0 +1,235 @@ +#! /usr/bin/vvp +:ivl_version "0.9.7 " "(v0_9_7)"; +:vpi_time_precision - 12; +:vpi_module "system"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x1f52730 .scope module, "testSignExtended" "testSignExtended" 2 4; + .timescale -9 -12; +v0x1f9b290_0 .var "in", 15 0; +v0x1f9b360_0 .net "out", 31 0, v0x1f9b1f0_0; 1 drivers +S_0x1f52820 .scope module, "se" "signExtended" 2 8, 3 1, S_0x1f52730; + .timescale -9 -12; +v0x1f8a560_0 .net "in", 15 0, v0x1f9b290_0; 1 drivers +v0x1f9b1f0_0 .var "out", 31 0; +E_0x1f66380 .event edge, v0x1f8a560_0; + .scope S_0x1f52820; +T_0 ; + %wait E_0x1f66380; + %load/v 8, v0x1f8a560_0, 16; + %ix/load 0, 16, 0; + %ix/load 1, 0, 0; + %assign/v0/x1 v0x1f9b1f0_0, 0, 8; + %ix/load 1, 15, 0; + %mov 4, 0, 1; + %jmp/1 T_0.0, 4; + %load/x1p 8, v0x1f8a560_0, 1; + %jmp T_0.1; +T_0.0 ; + %mov 8, 2, 1; +T_0.1 ; +; Save base=8 wid=1 in lookaside. + %ix/load 0, 1, 0; + %ix/load 1, 16, 0; + %assign/v0/x1 v0x1f9b1f0_0, 0, 8; + %ix/load 1, 15, 0; + %mov 4, 0, 1; + %jmp/1 T_0.2, 4; + %load/x1p 8, v0x1f8a560_0, 1; + %jmp T_0.3; +T_0.2 ; + %mov 8, 2, 1; +T_0.3 ; +; Save base=8 wid=1 in lookaside. + %ix/load 0, 1, 0; + %ix/load 1, 17, 0; + %assign/v0/x1 v0x1f9b1f0_0, 0, 8; + %ix/load 1, 15, 0; + %mov 4, 0, 1; + %jmp/1 T_0.4, 4; + %load/x1p 8, v0x1f8a560_0, 1; + %jmp T_0.5; +T_0.4 ; + %mov 8, 2, 1; +T_0.5 ; +; Save base=8 wid=1 in lookaside. + %ix/load 0, 1, 0; + %ix/load 1, 18, 0; + %assign/v0/x1 v0x1f9b1f0_0, 0, 8; + %ix/load 1, 15, 0; + %mov 4, 0, 1; + %jmp/1 T_0.6, 4; + %load/x1p 8, v0x1f8a560_0, 1; + %jmp T_0.7; +T_0.6 ; + %mov 8, 2, 1; +T_0.7 ; +; Save base=8 wid=1 in lookaside. + %ix/load 0, 1, 0; + %ix/load 1, 19, 0; + %assign/v0/x1 v0x1f9b1f0_0, 0, 8; + %ix/load 1, 15, 0; + %mov 4, 0, 1; + %jmp/1 T_0.8, 4; + %load/x1p 8, v0x1f8a560_0, 1; + %jmp T_0.9; +T_0.8 ; + %mov 8, 2, 1; +T_0.9 ; +; Save base=8 wid=1 in lookaside. + %ix/load 0, 1, 0; + %ix/load 1, 20, 0; + %assign/v0/x1 v0x1f9b1f0_0, 0, 8; + %ix/load 1, 15, 0; + %mov 4, 0, 1; + %jmp/1 T_0.10, 4; + %load/x1p 8, v0x1f8a560_0, 1; + %jmp T_0.11; +T_0.10 ; + %mov 8, 2, 1; +T_0.11 ; +; Save base=8 wid=1 in lookaside. + %ix/load 0, 1, 0; + %ix/load 1, 21, 0; + %assign/v0/x1 v0x1f9b1f0_0, 0, 8; + %ix/load 1, 15, 0; + %mov 4, 0, 1; + %jmp/1 T_0.12, 4; + %load/x1p 8, v0x1f8a560_0, 1; + %jmp T_0.13; +T_0.12 ; + %mov 8, 2, 1; +T_0.13 ; +; Save base=8 wid=1 in lookaside. + %ix/load 0, 1, 0; + %ix/load 1, 22, 0; + %assign/v0/x1 v0x1f9b1f0_0, 0, 8; + %ix/load 1, 15, 0; + %mov 4, 0, 1; + %jmp/1 T_0.14, 4; + %load/x1p 8, v0x1f8a560_0, 1; + %jmp T_0.15; +T_0.14 ; + %mov 8, 2, 1; +T_0.15 ; +; Save base=8 wid=1 in lookaside. + %ix/load 0, 1, 0; + %ix/load 1, 23, 0; + %assign/v0/x1 v0x1f9b1f0_0, 0, 8; + %ix/load 1, 15, 0; + %mov 4, 0, 1; + %jmp/1 T_0.16, 4; + %load/x1p 8, v0x1f8a560_0, 1; + %jmp T_0.17; +T_0.16 ; + %mov 8, 2, 1; +T_0.17 ; +; Save base=8 wid=1 in lookaside. + %ix/load 0, 1, 0; + %ix/load 1, 24, 0; + %assign/v0/x1 v0x1f9b1f0_0, 0, 8; + %ix/load 1, 15, 0; + %mov 4, 0, 1; + %jmp/1 T_0.18, 4; + %load/x1p 8, v0x1f8a560_0, 1; + %jmp T_0.19; +T_0.18 ; + %mov 8, 2, 1; +T_0.19 ; +; Save base=8 wid=1 in lookaside. + %ix/load 0, 1, 0; + %ix/load 1, 25, 0; + %assign/v0/x1 v0x1f9b1f0_0, 0, 8; + %ix/load 1, 15, 0; + %mov 4, 0, 1; + %jmp/1 T_0.20, 4; + %load/x1p 8, v0x1f8a560_0, 1; + %jmp T_0.21; +T_0.20 ; + %mov 8, 2, 1; +T_0.21 ; +; Save base=8 wid=1 in lookaside. + %ix/load 0, 1, 0; + %ix/load 1, 26, 0; + %assign/v0/x1 v0x1f9b1f0_0, 0, 8; + %ix/load 1, 15, 0; + %mov 4, 0, 1; + %jmp/1 T_0.22, 4; + %load/x1p 8, v0x1f8a560_0, 1; + %jmp T_0.23; +T_0.22 ; + %mov 8, 2, 1; +T_0.23 ; +; Save base=8 wid=1 in lookaside. + %ix/load 0, 1, 0; + %ix/load 1, 27, 0; + %assign/v0/x1 v0x1f9b1f0_0, 0, 8; + %ix/load 1, 15, 0; + %mov 4, 0, 1; + %jmp/1 T_0.24, 4; + %load/x1p 8, v0x1f8a560_0, 1; + %jmp T_0.25; +T_0.24 ; + %mov 8, 2, 1; +T_0.25 ; +; Save base=8 wid=1 in lookaside. + %ix/load 0, 1, 0; + %ix/load 1, 28, 0; + %assign/v0/x1 v0x1f9b1f0_0, 0, 8; + %ix/load 1, 15, 0; + %mov 4, 0, 1; + %jmp/1 T_0.26, 4; + %load/x1p 8, v0x1f8a560_0, 1; + %jmp T_0.27; +T_0.26 ; + %mov 8, 2, 1; +T_0.27 ; +; Save base=8 wid=1 in lookaside. + %ix/load 0, 1, 0; + %ix/load 1, 29, 0; + %assign/v0/x1 v0x1f9b1f0_0, 0, 8; + %ix/load 1, 15, 0; + %mov 4, 0, 1; + %jmp/1 T_0.28, 4; + %load/x1p 8, v0x1f8a560_0, 1; + %jmp T_0.29; +T_0.28 ; + %mov 8, 2, 1; +T_0.29 ; +; Save base=8 wid=1 in lookaside. + %ix/load 0, 1, 0; + %ix/load 1, 30, 0; + %assign/v0/x1 v0x1f9b1f0_0, 0, 8; + %ix/load 1, 15, 0; + %mov 4, 0, 1; + %jmp/1 T_0.30, 4; + %load/x1p 8, v0x1f8a560_0, 1; + %jmp T_0.31; +T_0.30 ; + %mov 8, 2, 1; +T_0.31 ; +; Save base=8 wid=1 in lookaside. + %ix/load 0, 1, 0; + %ix/load 1, 31, 0; + %assign/v0/x1 v0x1f9b1f0_0, 0, 8; + %jmp T_0; + .thread T_0, $push; + .scope S_0x1f52730; +T_1 ; + %vpi_call 2 11 "$display", "inputs | Output"; + %movi 8, 255, 16; + %set/v v0x1f9b290_0, 8, 16; + %delay 10000, 0; + %vpi_call 2 13 "$display", "%b | %b", v0x1f9b290_0, v0x1f9b360_0; + %movi 8, 64175, 16; + %set/v v0x1f9b290_0, 8, 16; + %delay 10000, 0; + %vpi_call 2 15 "$display", "%b | %b", v0x1f9b290_0, v0x1f9b360_0; + %end; + .thread T_1; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "signExtended.t.v"; + "./signExtended.v"; diff --git a/signExtended.t.v b/signExtended.t.v new file mode 100644 index 0000000..9b93380 --- /dev/null +++ b/signExtended.t.v @@ -0,0 +1,18 @@ +`timescale 1 ns / 1 ps +`include "signExtended.v" + +module testSignExtended(); + + wire[31:0] out; + reg[15:0] in; + signExtended se(out, in); + + initial begin + $display("inputs | Output"); + in = 16'h00FF; #10 + $display("%b | %b", in, out); + in = 16'hFAAF; #10 + $display("%b | %b", in, out); + end + +endmodule \ No newline at end of file