From 2b18a9559197117e37670675a247627cf36ed341 Mon Sep 17 00:00:00 2001
From: Alexander Hoppe <alexanderehoppe@gmail.com>
Date: Sun, 5 Nov 2017 16:42:27 -0500
Subject: [PATCH] Add work plan

---
 work_plan.txt | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 work_plan.txt

diff --git a/work_plan.txt b/work_plan.txt
new file mode 100644
index 0000000..38cf1d0
--- /dev/null
+++ b/work_plan.txt
@@ -0,0 +1,20 @@
+Work Plan
+William Derksen, Alexander Hoppe, Samuel Meyers, Taylor Sheneman
+
+Week 1
+
+- RTL for all required instructions in the set (30 mins)
+- Block Diagram of Single Cycle CPU (2 Hr) (by Wednesday night office hours)
+- Begin Verilog Implementation (4 Hr)
+
+Friday
+~~~~~~~~~~~~~~~~~~
+Saturday
+- Finish Verilog Implementation
+
+- Testing in parts (3 Hr)
+- Developing Assembly Code (3 Hr)
++ (stretch goal) Draw pipelined design block diagram (2 Hr)
++ Implement Pipeline (2 Hr)
++ Test pipelined design (should just be modifying exising ones)
+- Report writing (2 Hr)