diff --git a/CPU.t.v b/CPU.t.v new file mode 100644 index 0000000..1616884 --- /dev/null +++ b/CPU.t.v @@ -0,0 +1,85 @@ +`include "CPU.v" + +//------------------------------------------------------------------------ +// Simple fake CPU testbench sequence +//------------------------------------------------------------------------ + +module cpu_test (); + + reg clk; + reg reset; + + // Clock generation + initial clk=0; + always #10 clk = !clk; + + // Instantiate fake CPU + CPU cpu(.clk(clk), .reset(reset)); + + // Filenames for memory images and VCD dump file + reg [1023:0] mem_text_fn; + reg [1023:0] mem_data_fn; + reg [1023:0] dump_fn; + reg init_data = 1; // Initializing .data segment is optional + + // Test sequence + initial begin + $display("Starting CPU tests."); + + // Get command line arguments for memory image(s) and VCD dump file + // http://iverilog.wikia.com/wiki/Simulation + // http://www.project-veripage.com/plusarg.php + if (! $value$plusargs("mem_text_fn=%s", mem_text_fn)) begin + $display("ERROR: provide +mem_text_fn=[path to .text memory image] argument"); + $finish(); + end + if (! $value$plusargs("mem_data_fn=%s", mem_data_fn)) begin + $display("INFO: +mem_data_fn=[path to .data memory image] argument not provided; data memory segment uninitialized"); + init_data = 0; + end + + if (! $value$plusargs("dump_fn=%s", dump_fn)) begin + $display("ERROR: provide +dump_fn=[path for VCD dump] argument"); + $finish(); + end + + + // Load CPU memory from (assembly) dump files + // Assumes compact memory map, _word_ addressed memory implementation + // -> .text segment starts at word address 0 + // -> .data segment starts at word address 2048 (byte address 0x2000) + $readmemh(mem_text_fn, cpu.memory.memory, 0); + if (init_data) begin + $readmemh(mem_data_fn, cpu.memory.memory, 2048); + end + + // Dump waveforms to file + // Note: arrays (e.g. memory) are not dumped by default + $dumpfile(dump_fn); + $dumpvars(); + + // Assert reset pulse + reset = 0; #10; + reset = 1; #10; + reset = 0; #10; + + // Display a few cycles just for quick checking + // Note: I'm just dumping instruction bits, but you can do some + // self-checking test cases based on your CPU and program and + // automatically report the results. + // $display("Time | PC | Instruction"); + // repeat(3) begin + // $display("%4t | %h | %h", $time, cpu.programCounter, cpu.instruction); #20 ; + // end + // $display("... more execution (see waveform)"); + + // End execution after some time delay - adjust to match your program + // or use a smarter approach like looking for an exit syscall or the + // PC to be the value of the last instruction in your program. + #50000 + if(cpu.register.mux1.input2==32'h3a) + $display("Fib Test Successful"); + $finish(); + end + +endmodule diff --git a/CPU.v b/CPU.v new file mode 100644 index 0000000..6ae7f0b --- /dev/null +++ b/CPU.v @@ -0,0 +1,219 @@ +`include "regfile.v" +`include "mux.v" +`include "memReg.v" +`include "alu.v" +`include "adder.v" +`include "regWrLUT.v" +`include "signExtender.v" + +module CPU ( + input clk, + input reset +); +//wire declaration +wire[31:0] pcAfterAdd, pcPlusFour, Da, immediate; +wire opcode0Inv, opcode1Inv, opcode2Inv, opcode3Inv, opcode4Inv, opcode5Inv; + +wire isBranch, isBneOrBeq, zero, wEnable; + +//Program Counter Logic +reg[31:0] programCounter; +wire [31:0] instruction, nextProgramCounter; + +//advances the program to the next step +always @(posedge clk) begin + if (reset) programCounter <= 32'b0; + else programCounter <= nextProgramCounter; +end + +wire[25:0] jump; +wire[31:0] finalJumpValue; +assign jump = instruction[25:0]; +assign finalJumpValue = {pcPlusFour[31:26], jump}; + +wire isJumpSel; +not(opcode5Inv, opcode[5]); +and(isJumpSel, opcode5Inv, opcode4Inv, opcode3Inv, opcode2Inv, opcode[1]); +wire[31:0] jumpNextPC; +mux isJumpMux( + .input0(pcAfterAdd), + .input1(finalJumpValue), + .out(jumpNextPC), + .sel(isJumpSel) +); + +wire jrOr, jrNor; +or(jrOr, opcode[0], opcode[1], opcode[2], opcode[3], opcode[4], opcode[5], funct[5]); // if all of these are zero then its JR +not(jrNor, jrOr); +mux isNotJRMux( + .input1(Da), //R[rs] + .input0(jumpNextPC), + .out(nextProgramCounter), + .sel(jrNor) +); + +wire[31:0] fourOrBranch; +Adder programCounterAdder( + .operandA(programCounter), + .operandB(fourOrBranch), + .result(pcAfterAdd), + .carryout(), + .overflow() +); + +wire isBranchOrAddSel; +mux isBranchOrAddMux( + .input1(immediate + 1'b1), // has already been extended + .input0(32'd1), + .out(fourOrBranch), + .sel(isBranchOrAddSel) +); + +and(isBranchOrAddSel, isBranch, isBneOrBeq); + +and(isBranch, opcode1Inv, opcode[2]); //is true if BNE or BEQ +wire zeroInv; +not(zeroInv, zero); +defparam isBneOrBeqMux.data_width = 1; +mux isBneOrBeqMux( + .input0(zero), + .input1(zeroInv), + .out(isBneOrBeq), + .sel(opcode[0]) +); + +wire[5:0] opcode; +assign opcode = instruction[31:26]; +wire[5:0] funct; +assign funct = instruction[5:0]; + +//Register File Logic +wire[4:0] Rs, Rt, Rd; +wire[4:0] regWrite; +assign Rs = instruction[25:21]; +assign Rt = instruction[20:16]; +assign Rd = instruction[15:11]; +wire[31:0] Db, Dw; + +regfile register( + .ReadData1(Da), + .ReadData2(Db), + .WriteData(Dw), + .ReadRegister1(Rs), + .ReadRegister2(Rt), + .WriteRegister(regWrite), + .wEnable(wEnable), + .Clk(clk) +); + +regWrLUT isRegWrite( + .opcode(opcode), + .funct(funct), + .regwr(wEnable) +); + +wire rTypeOr; +wire[4:0] regWriteRdOrRt; +or(rTypeOr, opcode[0], opcode[1], opcode[2], opcode[3], opcode[4], opcode[5]); +//determines if you are writing to Rd or Rt +mux #(5) writeRegisterMuxRtOrRd( + .input0(Rd), + .input1(Rt), + .out(regWriteRdOrRt), + .sel(rTypeOr) +); + +wire isJumpandLink; +not(opcode0Inv, opcode[0]); +not(opcode1Inv, opcode[1]); +not(opcode2Inv, opcode[2]); +not(opcode3Inv, opcode[3]); +not(opcode4Inv, opcode[4]); +and(isJumpandLink, opcode[0], opcode[1], opcode2Inv, opcode3Inv, opcode4Inv, opcode5Inv); +//determines if write address is set my Rt or Rd or is "31" because of the opcode +mux #(5) writeRegister31Mux( + .input0(regWriteRdOrRt), + .input1(5'd31), + .out(regWrite), + .sel(isJumpandLink) +); + +//ALU Logic + +wire[31:0] DbOrImmediate; +wire DbOrImmediateSel; +or(DbOrImmediateSel, opcode[1], opcode[3]); + +mux isDbOrImmediateMux( + .input0(Db), + .input1(immediate), + .out(DbOrImmediate), + .sel(DbOrImmediateSel) +); + +wire[15:0] preExtendedImm; +assign preExtendedImm = instruction[15:0]; + +signExtend sExtend( + .extend(preExtendedImm), + .extended(immediate) +); + +wire[31:0] aluResult; +wire overflow, carryout; + +ALU alu( + .operandA(Da), + .operandB(DbOrImmediate), + .opcode(opcode), + .funct(funct), + .zero(zero), + .res(aluResult), + .overflow(overflow), + .carryout(carryout) +); + +//Memory Logic + +wire[31:0] dataOut; +wire dataWrite; +and(dataWrite, opcode[5], opcode[3]); +memoryReg memory( + .clk(clk), + .dataOutRW(dataOut), + .dataOutRead(instruction), + .addressRW(aluResult[31:2]), + .addressRead(programCounter), + .addressWrite(9'b0), //Don't actually need the second write port + .writeEnableRW(dataWrite), + .writeEnableWrite(1'b0), + .dataInRW(Db), + .dataInWrite(32'b0) +); + +wire isAluOrDout; +wire[31:0] aluOrDout; +and(isAluOrDout, opcode[5], opcode3Inv); + +mux isAluOrDoutMux( + .input1(dataOut), + .input0(aluResult), + .out(aluOrDout), + .sel(isAluOrDout) +); + +mux isJalAluOrDoutMux( + .input0(aluOrDout), + .input1(pcPlusFour), + .out(Dw), + .sel(isJumpandLink) +); + +Adder pcPlusFourAdder( + .operandA(programCounter), + .operandB(32'd1), + .result(pcPlusFour), + .carryout(), + .overflow() +); +endmodule \ No newline at end of file diff --git a/Lab 3 Writeup.pdf b/Lab 3 Writeup.pdf new file mode 100644 index 0000000..e4ab79d Binary files /dev/null and b/Lab 3 Writeup.pdf differ diff --git a/adder.t.v b/adder.t.v new file mode 100644 index 0000000..de65004 --- /dev/null +++ b/adder.t.v @@ -0,0 +1,52 @@ +`include "adder.v" + +module testAdder(); + reg[31:0] operandA; + reg[31:0] operandB; + wire[31:0] result; + wire overflow; + wire carryout; + + initial begin + $display(); + + $display("Starting Adder Tests."); + $display("TESTING ADD"); + operandA=32'd7000;operandB=32'd14000; #4000 + if(result != 32'd21000) $display("p + p = p TEST FAILED - result: %d", result); + if(overflow != 0) $display("p + p = p OVERFLOW FAILED"); + if(carryout != 0) $display("p + p = p CARRYOUT FAILED"); + operandA=32'd2147483647;operandB=32'd14000; #4000 + if(result != 32'd2147497647) $display("p + p = n TEST FAILED - result: %d", result); + if(overflow != 1) $display("p + p = n OVERFLOW FAILED"); + if(carryout != 0) $display("p + p = n CARRYOUT FAILED"); + operandA=32'd0;operandB=32'd87000; #4000 + if(result != 32'd87000) $display("0 + p = p TEST FAILED - result: %d", result); + if(overflow != 0) $display("0 + p = p OVERFLOW FAILED"); + if(carryout != 0) $display("0 + p = p CARRYOUT FAILED"); + operandA=32'd3657483652;operandB=32'd2997483652; #4000 + if(result != 32'd2360000008) $display("n + n = n TEST FAILED - result: %d", result); + if(overflow != 0) $display("n + n = n OVERFLOW FAILED"); + if(carryout != 1) $display("n + n = n CARRYOUT FAILED"); + operandA=32'd2147483652;operandB=32'd2147483652; #4000 + if(result != 32'd8) $display("n + n = p TEST FAILED - result: %d", result); + if(overflow != 1) $display("n + n = p OVERFLOW FAILED"); + if(carryout != 1) $display("n + n = p CARRYOUT FAILED"); + operandA=32'd3657483652;operandB=32'd637483644; #4000 + if(result != 32'd0) $display("n + p = 0 TEST FAILED - result: %d", result); + if(overflow != 0) $display("n + p = 0 OVERFLOW FAILED"); + if(carryout != 1) $display("n + p = 0 CARRYOUT FAILED"); + operandA=32'd3657483652;operandB=32'd637483645; #4000 + if(result != 32'd1) $display("n + p = p TEST FAILED - result: %d", result); + if(overflow != 0) $display("n + p = p OVERFLOW FAILED"); + if(carryout != 1) $display("n + p = p CARRYOUT FAILED"); + operandA=32'd3657483652;operandB=32'd637483643; #4000 + if(result != 32'd4294967295) $display("n + p = n TEST FAILED - result: %d", result); + if(overflow != 0) $display("n + p = n OVERFLOW FAILED"); + if(carryout != 0) $display("n + p = n CARRYOUT FAILED"); + + $display("Finished Adder Testing"); + $display(); + end + +endmodule // testAdder \ No newline at end of file diff --git a/adder.v b/adder.v new file mode 100644 index 0000000..67324c5 --- /dev/null +++ b/adder.v @@ -0,0 +1,82 @@ +module FullAdder1 +( + output res, + output carryout, + input a, + input b, + input carryin +); + wire xAorB; + wire AandB; + wire xAorBandCin; + xor xorgate(xAorB, a, b); // OR gate produces AorB from A and B + xor xorgate(res, xAorB, carryin); + and andgate(AandB, a, b); + and andgate(xAorBandCin, xAorB, carryin); + or orgate(carryout, AandB, xAorBandCin); +endmodule + +module didOverflow1 +( + output overflow, + input a, + input b, + input s +); +//this module determines if a signal overflows +// it requires the most significant bit of the two things being added together as well as the most significant bit of the sum +// this is only relevant when you are doing signed addition + wire notA; + wire notB; + wire notS; + wire aAndB; + wire notaAndNotb; + wire negToPos; + wire posToNeg; + + not aNot(notA, a); + not bNot(notB, b); + not sNot(notS, s); + + and andab(aAndB, a, b); + and andabNot(notaAndNotb, notA, notB); + + and andSwitch1(negToPos, aAndB, notS); //if the most significant bit of a and b were both 0 and the most significant big of the sum was 1, the inputs were both positive and the outpus was negative + and andSwitch2(posToNeg, notaAndNotb, s); // this is the same as the above line but from positive to negative + + or orGate(overflow, negToPos, posToNeg); + +endmodule + +module Adder +( + output[31:0] result, + output carryout, + output overflow, + input[31:0] operandA, + input[31:0] operandB +); + wire[32:0] carryOut; // one larger to accomodate for the initial carry in + assign carryOut[0] = 0; + + generate + genvar i; + for (i=0; i<32; i=i+1) + begin + FullAdder1 FullAdder ( + .carryout (carryOut[i+1]), + .a (operandA[i]), + .b (operandB[i]), + .carryin (carryOut[i]), + .res (result[i]) + ); + end + endgenerate + + didOverflow1 overflowCalc( // looks at most significant bit and checks if it will overflow + .overflow (overflow), + .a (operandA[31]), + .b (operandB[31]), + .s (result[31]) + ); +endmodule \ No newline at end of file diff --git a/alu.t.v b/alu.t.v new file mode 100644 index 0000000..3d14ebf --- /dev/null +++ b/alu.t.v @@ -0,0 +1,166 @@ +`include "alu.v" +`timescale 1 ns / 1 ps + +module testALU(); + reg[31:0] operandA; + reg[31:0] operandB; + reg[5:0] opcode; + reg[5:0] funct; + + wire[31:0] res; + wire overflow; + wire carryout; + wire zero; + + + ALU alu (operandA, operandB, opcode, funct, zero, res, overflow, carryout); + + initial begin + // $dumpfile("ALU.vcd"); + // $dumpvars(); + $display("Starting ALU tests."); + + $display("TESTING BASIC GATES"); + + // XOR Test + opcode = `XORI_OP; + funct = `JR_FUNCT; + if(res != 32'b0110) $display("XOR Test Failed - res: %b%b%b%b", res[3], res[2], res[1], res[0]); + + $display("TESTING ADD"); + opcode = `ADDI_OP; + funct = `JR_FUNCT; + operandA=32'd7000;operandB=32'd14000; #4000 + if(res != 32'd21000) $display("p + p = p TEST FAILED - res: %d", res); + if(overflow != 0) $display("p + p = p OVERFLOW FAILED"); + if(carryout != 0) $display("p + p = p CARRYOUT FAILED"); + operandA=32'd2147483647;operandB=32'd14000; #4000 + if(res != 32'd2147497647) $display("p + p = n TEST FAILED - res: %d", res); + if(overflow != 1) $display("p + p = n OVERFLOW FAILED"); + if(carryout != 0) $display("p + p = n CARRYOUT FAILED"); + if(zero != 0) $display("ZERO FAILED - was not 0 part 1"); + operandA=32'd0;operandB=32'd87000; #4000 + if(res != 32'd87000) $display("0 + p = p TEST FAILED - res: %d", res); + if(overflow != 0) $display("0 + p = p OVERFLOW FAILED"); + if(carryout != 0) $display("0 + p = p CARRYOUT FAILED"); + if(zero != 0) $display("ZERO FAILED - was not 0 part 2"); + operandA=32'd3657483652;operandB=32'd2997483652; #4000 + if(res != 32'd2360000008) $display("n + n = n TEST FAILED - res: %d", res); + if(overflow != 0) $display("n + n = n OVERFLOW FAILED"); + if(carryout != 1) $display("n + n = n CARRYOUT FAILED"); + if(zero != 0) $display("ZERO FAILED - was not 0 part 3"); + + opcode = `RTYPE_OP; + funct = `ADD_FUNCT; + operandA=32'd2147483652;operandB=32'd2147483652; #4000 + if(res != 32'd8) $display("n + n = p TEST FAILED - res: %d", res); + if(overflow != 1) $display("n + n = p OVERFLOW FAILED"); + if(carryout != 1) $display("n + n = p CARRYOUT FAILED"); + if(zero != 0) $display("ZERO FAILED - was not 0 part 4"); + operandA=32'd3657483652;operandB=32'd637483644; #4000 + if(res != 32'd0) $display("n + p = 0 TEST FAILED - res: %d", res); + if(overflow != 0) $display("n + p = 0 OVERFLOW FAILED"); + if(carryout != 1) $display("n + p = 0 CARRYOUT FAILED"); + if(zero != 1) $display("ZERO FAILED - was 0"); + operandA=32'd3657483652;operandB=32'd637483645; #4000 + if(res != 32'd1) $display("n + p = p TEST FAILED - res: %d", res); + if(overflow != 0) $display("n + p = p OVERFLOW FAILED"); + if(carryout != 1) $display("n + p = p CARRYOUT FAILED"); + if(zero != 0) $display("ZERO FAILED - was not 0 part 5"); + operandA=32'd3657483652;operandB=32'd637483643; #4000 + if(res != 32'd4294967295) $display("n + p = n TEST FAILED - res: %d", res); + if(overflow != 0) $display("n + p = n OVERFLOW FAILED"); + if(carryout != 0) $display("n + p = n CARRYOUT FAILED"); + + + $display("TESTING SUBTRACT"); + opcode = `RTYPE_OP; + funct = `SUB_FUNCT; + operandA=32'd0;operandB=32'd637483644; #4000 + if(res != 32'd3657483652) $display("0 - p = n TEST FAILED - res: %d", res); //the res is equivalent to -637483644 + if(overflow != 0) $display("0 - p = n OVERFLOW FAILED"); + if(carryout != 0) $display("0 - p = n CARRYOUT FAILED"); + operandA=32'd0;operandB=32'd3657483652; #4000 // b is equivalent to -637483644 + if(res != 32'd637483644) $display("0 - n = p TEST FAILED - res: %d", res); + if(overflow != 0) $display("0 - n = p OVERFLOW FAILED"); + if(carryout != 0) $display("0 - n = p CARRYOUT FAILED"); + operandA=32'd3657483652;operandB=32'd3657483652; #4000 // a and b is equivalent to -637483644 + if(res != 32'd0) $display("n - n = 0 TEST FAILED - res: %d", res); + if(overflow != 0) $display("n - n = 0 OVERFLOW FAILED"); + if(carryout != 1) $display("n - n = 0 CARRYOUT FAILED"); + if(zero != 1) $display("ZERO FAILED - was 0 part 1"); + + opcode = `BEQ_OP; + funct = `JR_FUNCT; + operandA=32'd637483644;operandB=32'd637483644; #4000 + if(res != 32'd0) $display("p - p = 0 TEST FAILED - res: %d", res); + if(overflow != 0) $display("p - p = 0 OVERFLOW FAILED"); + if(carryout != 1) $display("p - p = 0 CARRYOUT FAILED"); + if(zero != 1) $display("ZERO FAILED - was 0 part 2"); + operandA=32'd436258181;operandB=32'd236258181; #4000 + if(res != 32'd200000000) $display("p - p = p TEST FAILED - res: %d", res); + if(overflow != 0) $display("p - p = p OVERFLOW FAILED"); + if(carryout != 1) $display("p - p = p CARRYOUT FAILED"); + if(zero != 0) $display("ZERO FAILED - was not 0"); + operandA=32'd436258181;operandB=32'd2013265920; #4000 + if(res != 32'd2717959557) $display("p - p = n TEST FAILED - res: %d", res); //res is equivalent to -1845443195 + if(overflow != 0) $display("p - p = n OVERFLOW FAILED"); + if(carryout != 0) $display("p - p = n CARRYOUT FAILED"); + operandA=32'd3657483652;operandB=32'd3657483653; #4000 //a and b both correspond to negative numbers + if(res != 32'd4294967295) $display("n - n = n TEST FAILED - res: %d", res); //the res is also a negative twos complement number + if(overflow != 0) $display("n - n = n OVERFLOW FAILED"); + if(carryout != 0) $display("n - n = n CARRYOUT FAILED"); + + opcode = `BNE_OP; + funct = `JR_FUNCT; + operandA=32'd3657483652;operandB=32'd3657483651; #4000 + if(res != 32'd1) $display("n - n = p TEST FAILED - res: %d", res); + if(overflow != 0) $display("n - n = p OVERFLOW FAILED"); + if(carryout != 1) $display("n - n = p CARRYOUT FAILED"); + operandA=32'd7000;operandB=32'd4294953296 ; #4000 //b is the equivalent of -14000 + if(res != 32'd21000) $display("p - n = p TEST FAILED - res: %d", res); + if(overflow != 0) $display("p - n = p OVERFLOW FAILED"); + if(carryout != 0) $display("p - n = p CARRYOUT FAILED"); + operandA=32'd2147483647;operandB=32'd4294953296; #4000 + if(res != 32'd2147497647) $display("p - n = n TEST FAILED - res: %d", res); + if(overflow != 1) $display("p - n = n OVERFLOW FAILED"); + if(carryout != 0) $display("p - n = n CARRYOUT FAILED"); + operandA=32'd3657483652;operandB=32'd1297483644; #4000 + if(res != 32'd2360000008) $display("n - p = n TEST FAILED - res: %d", res); + if(overflow != 0) $display("n - p = n OVERFLOW FAILED"); + if(carryout != 1) $display("n - p = n CARRYOUT FAILED"); + operandA=32'd2147483652;operandB=32'd2147483644; #4000 + if(res != 32'd8) $display("n - p = p TEST FAILED - res: %d", res); + if(overflow != 1) $display("n - p = p OVERFLOW FAILED"); + if(carryout != 1) $display("n - p = p CARRYOUT FAILED"); + + $display("TESTING SLT"); + opcode = `RTYPE_OP; + funct = `SLT_FUNCT; + operandA=32'd0;operandB=32'd1000; #4000 + if (res != 32'd1) $display("0 < p TEST FAILED - res: %b", res); + operandA=32'd1;operandB=32'd0; #4000 + if (res != 32'd0) $display("p not < 0 TEST FAILED - res: %b", res); + operandA=32'd0;operandB=32'd3657483652; #4000 + if (res != 32'd0) $display("0 not < n TEST FAILED - res: %b", res); + operandA=32'd3657483652;operandB=32'd0; #4000 + if (res != 32'd1) $display("n < 0 TEST FAILED - res: %b %b", res, overflow); + operandA=32'd1000;operandB=32'd2000; #4000 + if (res != 32'd1) $display("p < p TEST FAILED"); + operandA=32'd2000;operandB=32'd1000; #4000 + if (res != 32'd0) $display("p not < p TEST FAILED"); + operandA=32'd2360000008;operandB=32'd3657483652; #4000 + if (res != 32'd1) $display("n < n TEST FAILED"); + operandA=32'd3657483652;operandB=32'd2360000008; #4000 + if (res != 32'd0) $display("n not < n TEST FAILED %b", res); + operandA=32'd3657483652;operandB=32'd1000; #10000 + if (res != 32'd1) $display("n < p TEST FAILED - res: %b, %b", res, overflow); + if(zero != 0) $display("ZERO FAILED - was not 1"); + operandA=32'd1000;operandB=32'd3657483652; #4000 + if (res != 32'd0) $display("p not < n TEST FAILED"); + if(zero != 32'd1) $display("ZERO FAILED - was 0 %b %b ", zero, res); + + $display("ALU Testing Finished"); + $display(); + end +endmodule // testALU diff --git a/alu.v b/alu.v new file mode 100644 index 0000000..115744f --- /dev/null +++ b/alu.v @@ -0,0 +1,256 @@ +`define LW_OP 6'b100011 +`define SW_OP 6'b101011 +`define J_OP 6'b000010 +`define JAL_OP 6'b000011 +`define BEQ_OP 6'b000100 +`define BNE_OP 6'b000101 +`define XORI_OP 6'b001110 +`define ADDI_OP 6'b001000 +`define RTYPE_OP 6'b000000 + +`define JR_FUNCT 6'b001000 +`define ADD_FUNCT 6'b100000 +`define SUB_FUNCT 6'b100010 +`define SLT_FUNCT 6'b101010 + +`timescale 1 ns / 1 ps + +module ALUBitSlice( + input a, + input b, + input[5:0] opcode, + input[5:0] funct, + input carryIn, + output res, + output carryOut, + output reg isSubtract +); +wire addRes; +wire finalAdd; +wire xorRes; +wire finalXor; +wire finalA; +reg isA; +reg isAdd; +reg isXor; + + AdderAndSubtractor adder ( + .res (addRes), + .carryout (carryOut), + .a (a), + .b (b), + .isSubtract (isSubtract), + .carryin (carryIn) + ); + + xor xorRes(xorRes, a, b); + + + always @(opcode or funct) begin + case (opcode) + `LW_OP: begin isA=0; isAdd=1; isXor=0; isSubtract=0; end + `SW_OP: begin isA=0; isAdd=1; isXor=0; isSubtract=0; end //SW + `J_OP: begin isA=1; isAdd=0; isXor=0; isSubtract=0; end //J + `JAL_OP: begin isA=1; isAdd=0; isXor=0; isSubtract=0; end //JAL + `BEQ_OP: begin isA=0; isAdd=1; isXor=0; isSubtract=1; end //BEQ + `BNE_OP: begin isA=0; isAdd=1; isXor=0; isSubtract=1; end//BNE + `XORI_OP: begin isA=0; isAdd=0; isXor=1; isSubtract=0; end //XORI + `ADDI_OP: begin isA=0; isAdd=1; isXor=0; isSubtract=0; end //ADDI + + `RTYPE_OP: begin + case (funct) + `JR_FUNCT: begin isA=1; isAdd=0; isXor=0; isSubtract=0; end //JR + `ADD_FUNCT: begin isA=0; isAdd=1; isXor=0; isSubtract=0; end //ADD + `SUB_FUNCT: begin isA=0; isAdd=1; isXor=0; isSubtract=1; end //SUB //actually is subtract + `SLT_FUNCT: begin isA=0; isAdd=1; isXor=0; isSubtract=1; end//SLT //actually is subtract + default: $display("Error in ALUBitSlice: Invalid funct"); + endcase + end + default: $display("Error in ALU: Invalid opcode. OPCODE: %b", opcode); + endcase + end + + and andAdd(finalAdd, addRes, isAdd); + and andXor(finalXor, xorRes, isXor); + and andA(finalA, a, isA); + + or orRes(res, finalAdd, finalXor, finalA); + +endmodule + +module AdderAndSubtractor +( + output res, + output carryout, + input a, + input b, + input isSubtract, + input carryin +); + wire BxorSub; + wire xAorB; + wire AandB; + wire xAorBandCin; + xor xorgate(BxorSub, b, isSubtract); + xor xorgate(xAorB, a, BxorSub); // OR gate produces AorB from A and B + xor xorgate(res, xAorB, carryin); + and andgate(AandB, a, BxorSub); + and andgate(xAorBandCin, xAorB, carryin); + or orgate(carryout, AandB, xAorBandCin); +endmodule + +module isZero ( + input[31:0] zeroBit, + output out +); +wire outInv; +//nor all bits, if all are zero a one will be returned if any are not a 0 will be returned. + +or zeroNOR(outInv, zeroBit[0], zeroBit[1], zeroBit[2], zeroBit[3], zeroBit[4], zeroBit[5], zeroBit[6], zeroBit[7], zeroBit[8], zeroBit[9], zeroBit[10], zeroBit[11], zeroBit[12], zeroBit[13], zeroBit[14], + zeroBit[15], zeroBit[16], zeroBit[17], zeroBit[18], zeroBit[19], zeroBit[20], zeroBit[21], zeroBit[22], zeroBit[23], zeroBit[24], zeroBit[25], zeroBit[26], zeroBit[27], zeroBit[28], zeroBit[29], zeroBit[30], zeroBit[31]); +not notOut(out, outInv); + +endmodule // isZero + +module didOverflow // calculates overflow of 2 bits +( + output overflow, + input a, + input b, + input s, // most sig bit + input sub +); + wire BxorSub; + wire notA; + wire notB; + wire notS; + wire aAndB; + wire notaAndNotb; + wire negToPos; + wire posToNeg; + xor xorgate(BxorSub, b, sub); + not aNot(notA, a); + not bNot(notB, BxorSub); + not sNot(notS, s); + and andab(aAndB, a, BxorSub); + and andabNot(notaAndNotb, notA, notB); + and andSwitch1(negToPos, aAndB, notS); + and andSwitch2(posToNeg, notaAndNotb, s); + or orGate(overflow, negToPos, posToNeg); +endmodule + +module ALU( + input[31:0] operandA, + input[31:0] operandB, + input[5:0] opcode, + input[5:0] funct, + output zero, + output[31:0] res, + output overflow, + output carryout +); + wire[31:0] initialResult; + wire[31:0] initialFinal; + reg isInitial; + wire[31:0] sltResult; + wire[31:0] sltFinal; + reg isSLT; + wire isSubtract; + wire[32:0] carryOut; + + or carryOr(carryOut[0], isSubtract, isSubtract); + + generate + genvar i; + for (i=0; i<32; i=i+1) + //makes mini ALU for each bit + begin + ALUBitSlice aluBitSlice ( + .carryOut (carryOut[i+1]), + .res (initialResult[i]), + .a (operandA[i]), + .b (operandB[i]), + .carryIn (carryOut[i]), + .isSubtract (isSubtract), + .opcode (opcode), + .funct (funct) + ); + end + endgenerate + + always @(opcode or funct) begin + case (opcode) + `LW_OP: begin isInitial=1; isSLT=0; end //LW + `SW_OP: begin isInitial=1; isSLT=0; end //SW + `J_OP: begin isInitial=1; isSLT=0; end //J + `JAL_OP: begin isInitial=1; isSLT=0; end //JAL + `BEQ_OP: begin isInitial=1; isSLT=0; end //BEQ + `BNE_OP: begin isInitial=1; isSLT=0; end //BNE + `XORI_OP: begin isInitial=1; isSLT=0; end //XORI + `ADDI_OP: begin isInitial=1; isSLT=0; end //ADDI + + `RTYPE_OP: begin + case (funct) + `JR_FUNCT: begin isInitial=1; isSLT=0; end //JR + `ADD_FUNCT: begin isInitial=1; isSLT=0; end //ADD + `SUB_FUNCT: begin isInitial=1; isSLT=0; end //SUB + `SLT_FUNCT: begin isInitial=0; isSLT=1; end //SLT + default: $display("Error in ALU: Invalid funct. OPCODE: %b", opcode); + endcase + end + + default: $display("Error in ALU: Invalid opcode"); + endcase + end + + //SLT Module for . Uses outputs of subtractor + wire overflowInv; + wire isSLTinv; + wire SLTval; + + wire bInv; + not(bInv, operandB[31]); + + wire aCheck; + wire bCheck; + wire abCheck; + + and(aCheck, operandA[31], initialResult[31], isSLT); + and(bCheck, bInv, initialResult[31], isSLT); + and(abCheck, operandA[31], bInv, isSLT); + + or(SLTval, aCheck, bCheck, abCheck); + + // not(overflowInv, overflow); + not(isSLTinv, isSLT); + // and(SLTval, initialResult[31], overflowInv, isSLT); + + generate + genvar j; + for (j=1; j<32; j=j+1) + begin + and(res[j], initialResult[j], isSLTinv); + end + endgenerate + + wire sltCheck; + and(sltCheck, initialResult[0], isSLTinv); + or(res[0], sltCheck, SLTval); + + didOverflow overflowCalc ( + .overflow (overflow), + .a (operandA[31]), + .b (operandB[31]), + .s (initialResult[31]), + .sub (isSubtract) + ); + + isZero zeroCalc( + .zeroBit (res), + .out (zero) + ); + + or orCarryout(carryout, carryOut[32], carryOut[32]); + +endmodule + diff --git a/aluTest b/aluTest new file mode 100755 index 0000000..658b7cf --- /dev/null +++ b/aluTest @@ -0,0 +1,9233 @@ +#! /usr/local/bin/vvp +:ivl_version "10.1 (stable)" "(v10_1-107-gab6ae79)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x189e4c0 .scope module, "testALU" "testALU" 2 4; + .timescale -9 -12; +v0x1a03a80_0 .net "carryout", 0 0, L_0x1a25510; 1 drivers +v0x1a03b70_0 .var "funct", 5 0; +v0x1a03c10_0 .var "opcode", 5 0; +v0x1a03ce0_0 .var "operandA", 31 0; +v0x1a03dd0_0 .var "operandB", 31 0; +v0x1a03e70_0 .net "overflow", 0 0, L_0x1a22c90; 1 drivers +RS_0x7fa24fdd4a38 .resolv tri, L_0x1a1f2e0, L_0x1a21e70; +v0x1a03f60_0 .net8 "res", 31 0, RS_0x7fa24fdd4a38; 2 drivers +v0x1a04050_0 .net "zero", 0 0, L_0x1a24190; 1 drivers +S_0x18c67f0 .scope module, "alu" "ALU" 2 15, 3 142 0, S_0x189e4c0; + .timescale -9 -12; + .port_info 0 /INPUT 32 "operandA" + .port_info 1 /INPUT 32 "operandB" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /OUTPUT 1 "zero" + .port_info 5 /OUTPUT 32 "res" + .port_info 6 /OUTPUT 1 "overflow" + .port_info 7 /OUTPUT 1 "carryout" +RS_0x7fa24fdc8138 .resolv tri, v0x19b9c70_0, v0x19bbb50_0, v0x19bda10_0, v0x19bf8b0_0, v0x19c1850_0, v0x19c36a0_0, v0x19c5500_0, v0x19c7360_0, v0x19c9420_0, v0x19cb290_0, v0x19cd0f0_0, v0x19cef50_0, v0x19d0db0_0, v0x19d2c10_0, v0x19d4a70_0, v0x19d68d0_0, v0x19d8b30_0, v0x19daa40_0, v0x19dc8a0_0, v0x19de6f0_0, v0x19e0570_0, v0x19e23d0_0, v0x19e4230_0, v0x19e6090_0, v0x19e7ef0_0, v0x19e9d50_0, v0x19ebbb0_0, v0x19eda10_0, v0x19ef870_0, v0x19f16d0_0, v0x19f3530_0, v0x19f5390_0; +L_0x1a21110 .functor OR 1, RS_0x7fa24fdc8138, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a211d0 .functor NOT 1, L_0x1a22c90, C4<0>, C4<0>, C4<0>; +L_0x1a21240 .functor NOT 1, v0x1a03060_0, C4<0>, C4<0>, C4<0>; +L_0x1a212b0 .functor AND 1, L_0x1a22290, L_0x1a211d0, v0x1a03060_0, C4<1>; +L_0x1a21fa0 .functor OR 1, L_0x1a22060, L_0x1a212b0, C4<0>, C4<0>; +L_0x1a25510 .functor OR 1, L_0x1a257c0, L_0x1a22f70, C4<0>, C4<0>; +v0x1a00560_0 .net "SLTval", 0 0, L_0x1a212b0; 1 drivers +v0x1a00620_0 .net *"_s225", 0 0, L_0x1a1db60; 1 drivers +v0x1a00700_0 .net *"_s228", 0 0, L_0x1a1d260; 1 drivers +v0x1a007f0_0 .net *"_s231", 0 0, L_0x1a1d410; 1 drivers +v0x1a008d0_0 .net *"_s234", 0 0, L_0x1a1dd10; 1 drivers +v0x1a00a00_0 .net *"_s237", 0 0, L_0x1a1deb0; 1 drivers +v0x1a00ae0_0 .net *"_s240", 0 0, L_0x1a1dfc0; 1 drivers +v0x1a00bc0_0 .net *"_s243", 0 0, L_0x1a1e4f0; 1 drivers +v0x1a00ca0_0 .net *"_s246", 0 0, L_0x1a1e030; 1 drivers +v0x1a00e10_0 .net *"_s249", 0 0, L_0x1a1e2a0; 1 drivers +v0x1a00ef0_0 .net *"_s252", 0 0, L_0x1a1dd80; 1 drivers +v0x1a00fd0_0 .net *"_s255", 0 0, L_0x1a1ebb0; 1 drivers +v0x1a010b0_0 .net *"_s258", 0 0, L_0x1a1e760; 1 drivers +v0x1a01190_0 .net *"_s261", 0 0, L_0x1a1e8c0; 1 drivers +v0x1a01270_0 .net *"_s264", 0 0, L_0x1a1ea20; 1 drivers +v0x1a01350_0 .net *"_s267", 0 0, L_0x1a1f180; 1 drivers +v0x1a01430_0 .net *"_s270", 0 0, L_0x1a1e650; 1 drivers +v0x1a015e0_0 .net *"_s273", 0 0, L_0x1a1e0f0; 1 drivers +v0x1a01680_0 .net *"_s276", 0 0, L_0x1a1efc0; 1 drivers +v0x1a01760_0 .net *"_s279", 0 0, L_0x1a1f930; 1 drivers +v0x1a01840_0 .net *"_s282", 0 0, L_0x1a1f4f0; 1 drivers +v0x1a01920_0 .net *"_s285", 0 0, L_0x1a1f650; 1 drivers +v0x1a01a00_0 .net *"_s288", 0 0, L_0x1a1f7b0; 1 drivers +v0x1a01ae0_0 .net *"_s291", 0 0, L_0x1a1fef0; 1 drivers +v0x1a01bc0_0 .net *"_s294", 0 0, L_0x1a1fa90; 1 drivers +v0x1a01ca0_0 .net *"_s297", 0 0, L_0x1a1fbf0; 1 drivers +v0x1a01d80_0 .net *"_s300", 0 0, L_0x1a1fd50; 1 drivers +v0x1a01e60_0 .net *"_s303", 0 0, L_0x1a204d0; 1 drivers +v0x1a01f40_0 .net *"_s306", 0 0, L_0x1a20050; 1 drivers +v0x1a02020_0 .net *"_s309", 0 0, L_0x1a201b0; 1 drivers +v0x1a02100_0 .net *"_s312", 0 0, L_0x1a20310; 1 drivers +v0x1a021e0_0 .net *"_s315", 0 0, L_0x1a20a80; 1 drivers +v0x1a022c0_0 .net *"_s318", 0 0, L_0x1a219a0; 1 drivers +v0x1a01510_0 .net *"_s322", 0 0, L_0x1a21110; 1 drivers +v0x1a02590_0 .net *"_s329", 0 0, L_0x1a22290; 1 drivers +v0x1a02670_0 .net *"_s331", 0 0, L_0x1a21fa0; 1 drivers +v0x1a02750_0 .net *"_s334", 0 0, L_0x1a22060; 1 drivers +v0x1a02830_0 .net *"_s342", 0 0, L_0x1a257c0; 1 drivers +v0x1a02910_0 .net *"_s344", 0 0, L_0x1a22f70; 1 drivers +v0x1a029f0_0 .net "carryOut", 32 0, L_0x1a1ee00; 1 drivers +v0x1a02ad0_0 .net "carryout", 0 0, L_0x1a25510; alias, 1 drivers +v0x1a02b90_0 .net "funct", 5 0, v0x1a03b70_0; 1 drivers +v0x19d8880_0 .net "initialResult", 31 0, L_0x1a108f0; 1 drivers +v0x19d8960_0 .var "isInitial", 0 0; +v0x1a03060_0 .var "isSLT", 0 0; +v0x1a03100_0 .net "isSLTinv", 0 0, L_0x1a21240; 1 drivers +v0x1a031a0_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; 32 drivers +v0x1a03240_0 .net "opcode", 5 0, v0x1a03c10_0; 1 drivers +v0x19d8d10_0 .net "operandA", 31 0, v0x1a03ce0_0; 1 drivers +v0x19d8df0_0 .net "operandB", 31 0, v0x1a03dd0_0; 1 drivers +v0x1a036f0_0 .net "overflow", 0 0, L_0x1a22c90; alias, 1 drivers +v0x1a03790_0 .net "overflowInv", 0 0, L_0x1a211d0; 1 drivers +v0x1a03830_0 .net8 "res", 31 0, RS_0x7fa24fdd4a38; alias, 2 drivers +v0x1a038d0_0 .net "zero", 0 0, L_0x1a24190; alias, 1 drivers +L_0x1a04b40 .part v0x1a03ce0_0, 0, 1; +L_0x1a04c30 .part v0x1a03dd0_0, 0, 1; +L_0x1a04d60 .part L_0x1a1ee00, 0, 1; +L_0x1a057a0 .part v0x1a03ce0_0, 1, 1; +L_0x1a05840 .part v0x1a03dd0_0, 1, 1; +L_0x1a05970 .part L_0x1a1ee00, 1, 1; +L_0x1a063f0 .part v0x1a03ce0_0, 2, 1; +L_0x1a06520 .part v0x1a03dd0_0, 2, 1; +L_0x1a066e0 .part L_0x1a1ee00, 2, 1; +L_0x1a07040 .part v0x1a03ce0_0, 3, 1; +L_0x1a07140 .part v0x1a03dd0_0, 3, 1; +L_0x1a07270 .part L_0x1a1ee00, 3, 1; +L_0x1a07cf0 .part v0x1a03ce0_0, 4, 1; +L_0x1a07d90 .part v0x1a03dd0_0, 4, 1; +L_0x1a07f40 .part L_0x1a1ee00, 4, 1; +L_0x1a088f0 .part v0x1a03ce0_0, 5, 1; +L_0x1a08a20 .part v0x1a03dd0_0, 5, 1; +L_0x1a08b50 .part L_0x1a1ee00, 5, 1; +L_0x1a095a0 .part v0x1a03ce0_0, 6, 1; +L_0x1a09750 .part v0x1a03dd0_0, 6, 1; +L_0x1a08c80 .part L_0x1a1ee00, 6, 1; +L_0x1a0a2a0 .part v0x1a03ce0_0, 7, 1; +L_0x1a09900 .part v0x1a03dd0_0, 7, 1; +L_0x1a0a490 .part L_0x1a1ee00, 7, 1; +L_0x1a0af30 .part v0x1a03ce0_0, 8, 1; +L_0x1a0afd0 .part v0x1a03dd0_0, 8, 1; +L_0x1a0a6d0 .part L_0x1a1ee00, 8, 1; +L_0x1a0bb30 .part v0x1a03ce0_0, 9, 1; +L_0x1a0b100 .part v0x1a03dd0_0, 9, 1; +L_0x1a0bd50 .part L_0x1a1ee00, 9, 1; +L_0x1a0c720 .part v0x1a03ce0_0, 10, 1; +L_0x1a0c7c0 .part v0x1a03dd0_0, 10, 1; +L_0x1a0be80 .part L_0x1a1ee00, 10, 1; +L_0x1a0d330 .part v0x1a03ce0_0, 11, 1; +L_0x1a0c8f0 .part v0x1a03dd0_0, 11, 1; +L_0x1a0d580 .part L_0x1a1ee00, 11, 1; +L_0x1a0df50 .part v0x1a03ce0_0, 12, 1; +L_0x1a0dff0 .part v0x1a03dd0_0, 12, 1; +L_0x1a0d6b0 .part L_0x1a1ee00, 12, 1; +L_0x1a0eb50 .part v0x1a03ce0_0, 13, 1; +L_0x1a0e120 .part v0x1a03dd0_0, 13, 1; +L_0x1a0ed40 .part L_0x1a1ee00, 13, 1; +L_0x1a0f790 .part v0x1a03ce0_0, 14, 1; +L_0x1a09640 .part v0x1a03dd0_0, 14, 1; +L_0x1a097f0 .part L_0x1a1ee00, 14, 1; +L_0x1a105a0 .part v0x1a03ce0_0, 15, 1; +L_0x1a0fce0 .part v0x1a03dd0_0, 15, 1; +L_0x1a107c0 .part L_0x1a1ee00, 15, 1; +L_0x1a112d0 .part v0x1a03ce0_0, 16, 1; +L_0x1a11370 .part v0x1a03dd0_0, 16, 1; +L_0x1a10b00 .part L_0x1a1ee00, 16, 1; +L_0x1a11eb0 .part v0x1a03ce0_0, 17, 1; +L_0x1a114a0 .part v0x1a03dd0_0, 17, 1; +L_0x1a12100 .part L_0x1a1ee00, 17, 1; +L_0x1a12ac0 .part v0x1a03ce0_0, 18, 1; +L_0x1a12b60 .part v0x1a03dd0_0, 18, 1; +L_0x1a12230 .part L_0x1a1ee00, 18, 1; +L_0x1a136a0 .part v0x1a03ce0_0, 19, 1; +L_0x1a12c90 .part v0x1a03dd0_0, 19, 1; +L_0x1a12dc0 .part L_0x1a1ee00, 19, 1; +L_0x1a142b0 .part v0x1a03ce0_0, 20, 1; +L_0x1a14350 .part v0x1a03dd0_0, 20, 1; +L_0x1a139b0 .part L_0x1a1ee00, 20, 1; +L_0x1a14eb0 .part v0x1a03ce0_0, 21, 1; +L_0x1a14480 .part v0x1a03dd0_0, 21, 1; +L_0x1a145b0 .part L_0x1a1ee00, 21, 1; +L_0x1a15ae0 .part v0x1a03ce0_0, 22, 1; +L_0x1a15b80 .part v0x1a03dd0_0, 22, 1; +L_0x1a151f0 .part L_0x1a1ee00, 22, 1; +L_0x1a166f0 .part v0x1a03ce0_0, 23, 1; +L_0x1a15cb0 .part v0x1a03dd0_0, 23, 1; +L_0x1a15de0 .part L_0x1a1ee00, 23, 1; +L_0x1a17310 .part v0x1a03ce0_0, 24, 1; +L_0x1a173b0 .part v0x1a03dd0_0, 24, 1; +L_0x1a16a60 .part L_0x1a1ee00, 24, 1; +L_0x1a17f60 .part v0x1a03ce0_0, 25, 1; +L_0x1a174e0 .part v0x1a03dd0_0, 25, 1; +L_0x1a17610 .part L_0x1a1ee00, 25, 1; +L_0x1a18b70 .part v0x1a03ce0_0, 26, 1; +L_0x1a18c10 .part v0x1a03dd0_0, 26, 1; +L_0x1a18000 .part L_0x1a1ee00, 26, 1; +L_0x1a19790 .part v0x1a03ce0_0, 27, 1; +L_0x1a18d40 .part v0x1a03dd0_0, 27, 1; +L_0x1a18e70 .part L_0x1a1ee00, 27, 1; +L_0x1a1a3a0 .part v0x1a03ce0_0, 28, 1; +L_0x1a1a440 .part v0x1a03dd0_0, 28, 1; +L_0x1a19830 .part L_0x1a1ee00, 28, 1; +L_0x1a1afa0 .part v0x1a03ce0_0, 29, 1; +L_0x1a1a570 .part v0x1a03dd0_0, 29, 1; +L_0x1a1a6a0 .part L_0x1a1ee00, 29, 1; +L_0x1a1bbc0 .part v0x1a03ce0_0, 30, 1; +L_0x1a0f830 .part v0x1a03dd0_0, 30, 1; +L_0x1a0f960 .part L_0x1a1ee00, 30, 1; +L_0x1a1cab0 .part v0x1a03ce0_0, 31, 1; +L_0x1a1c480 .part v0x1a03dd0_0, 31, 1; +L_0x1a1c5b0 .part L_0x1a1ee00, 31, 1; +LS_0x1a108f0_0_0 .concat8 [ 1 1 1 1], L_0x1a04980, L_0x1a05640, L_0x1a06290, L_0x1a06ee0; +LS_0x1a108f0_0_4 .concat8 [ 1 1 1 1], L_0x1a07b60, L_0x1a08760, L_0x1a09410, L_0x1a0a110; +LS_0x1a108f0_0_8 .concat8 [ 1 1 1 1], L_0x1a0add0, L_0x1a0b9d0, L_0x1a0c5c0, L_0x1a0d1a0; +LS_0x1a108f0_0_12 .concat8 [ 1 1 1 1], L_0x1a0ddc0, L_0x1a0e9c0, L_0x1a0f600, L_0x1a10410; +LS_0x1a108f0_0_16 .concat8 [ 1 1 1 1], L_0x1a11170, L_0x1a11d50, L_0x1a12960, L_0x1a13510; +LS_0x1a108f0_0_20 .concat8 [ 1 1 1 1], L_0x1a14120, L_0x1a14d20, L_0x1a15980, L_0x1a16560; +LS_0x1a108f0_0_24 .concat8 [ 1 1 1 1], L_0x1a17180, L_0x1a17dd0, L_0x1a189e0, L_0x1a19600; +LS_0x1a108f0_0_28 .concat8 [ 1 1 1 1], L_0x1a1a240, L_0x1a1ae10, L_0x1a1ba30, L_0x1a1c950; +LS_0x1a108f0_1_0 .concat8 [ 4 4 4 4], LS_0x1a108f0_0_0, LS_0x1a108f0_0_4, LS_0x1a108f0_0_8, LS_0x1a108f0_0_12; +LS_0x1a108f0_1_4 .concat8 [ 4 4 4 4], LS_0x1a108f0_0_16, LS_0x1a108f0_0_20, LS_0x1a108f0_0_24, LS_0x1a108f0_0_28; +L_0x1a108f0 .concat8 [ 16 16 0 0], LS_0x1a108f0_1_0, LS_0x1a108f0_1_4; +L_0x1a1dbd0 .part L_0x1a108f0, 0, 1; +L_0x1a1d320 .part L_0x1a108f0, 1, 1; +L_0x1a1d480 .part L_0x1a108f0, 2, 1; +L_0x1a1de10 .part L_0x1a108f0, 3, 1; +L_0x1a1df20 .part L_0x1a108f0, 4, 1; +L_0x1a1e400 .part L_0x1a108f0, 5, 1; +L_0x1a1e560 .part L_0x1a108f0, 6, 1; +L_0x1a1e1b0 .part L_0x1a108f0, 7, 1; +L_0x1a1e310 .part L_0x1a108f0, 8, 1; +L_0x1a1eac0 .part L_0x1a108f0, 9, 1; +L_0x1a1ec20 .part L_0x1a108f0, 10, 1; +L_0x1a1e7d0 .part L_0x1a108f0, 11, 1; +L_0x1a1e930 .part L_0x1a108f0, 12, 1; +L_0x1a1f090 .part L_0x1a108f0, 13, 1; +L_0x1a1f1f0 .part L_0x1a108f0, 14, 1; +L_0x1a1e6c0 .part L_0x1a108f0, 15, 1; +L_0x1a1ef20 .part L_0x1a108f0, 16, 1; +L_0x1a1f890 .part L_0x1a108f0, 17, 1; +L_0x1a1f9a0 .part L_0x1a108f0, 18, 1; +L_0x1a1f560 .part L_0x1a108f0, 19, 1; +L_0x1a1f6c0 .part L_0x1a108f0, 20, 1; +L_0x1a1fe50 .part L_0x1a108f0, 21, 1; +L_0x1a1ff60 .part L_0x1a108f0, 22, 1; +L_0x1a1fb00 .part L_0x1a108f0, 23, 1; +L_0x1a1fc60 .part L_0x1a108f0, 24, 1; +L_0x1a20430 .part L_0x1a108f0, 25, 1; +L_0x1a20540 .part L_0x1a108f0, 26, 1; +L_0x1a200c0 .part L_0x1a108f0, 27, 1; +L_0x1a20220 .part L_0x1a108f0, 28, 1; +L_0x1a20380 .part L_0x1a108f0, 29, 1; +L_0x1a20af0 .part L_0x1a108f0, 30, 1; +LS_0x1a1f2e0_0_0 .concat8 [ 1 1 1 1], L_0x1a1db60, L_0x1a1d260, L_0x1a1d410, L_0x1a1dd10; +LS_0x1a1f2e0_0_4 .concat8 [ 1 1 1 1], L_0x1a1deb0, L_0x1a1dfc0, L_0x1a1e4f0, L_0x1a1e030; +LS_0x1a1f2e0_0_8 .concat8 [ 1 1 1 1], L_0x1a1e2a0, L_0x1a1dd80, L_0x1a1ebb0, L_0x1a1e760; +LS_0x1a1f2e0_0_12 .concat8 [ 1 1 1 1], L_0x1a1e8c0, L_0x1a1ea20, L_0x1a1f180, L_0x1a1e650; +LS_0x1a1f2e0_0_16 .concat8 [ 1 1 1 1], L_0x1a1e0f0, L_0x1a1efc0, L_0x1a1f930, L_0x1a1f4f0; +LS_0x1a1f2e0_0_20 .concat8 [ 1 1 1 1], L_0x1a1f650, L_0x1a1f7b0, L_0x1a1fef0, L_0x1a1fa90; +LS_0x1a1f2e0_0_24 .concat8 [ 1 1 1 1], L_0x1a1fbf0, L_0x1a1fd50, L_0x1a204d0, L_0x1a20050; +LS_0x1a1f2e0_0_28 .concat8 [ 1 1 1 1], L_0x1a201b0, L_0x1a20310, L_0x1a20a80, L_0x1a219a0; +LS_0x1a1f2e0_1_0 .concat8 [ 4 4 4 4], LS_0x1a1f2e0_0_0, LS_0x1a1f2e0_0_4, LS_0x1a1f2e0_0_8, LS_0x1a1f2e0_0_12; +LS_0x1a1f2e0_1_4 .concat8 [ 4 4 4 4], LS_0x1a1f2e0_0_16, LS_0x1a1f2e0_0_20, LS_0x1a1f2e0_0_24, LS_0x1a1f2e0_0_28; +L_0x1a1f2e0 .concat8 [ 16 16 0 0], LS_0x1a1f2e0_1_0, LS_0x1a1f2e0_1_4; +L_0x1a1ed10 .part L_0x1a108f0, 31, 1; +LS_0x1a1ee00_0_0 .concat8 [ 1 1 1 1], L_0x1a21110, L_0x1a045b0, L_0x1a05250, L_0x1a05ea0; +LS_0x1a1ee00_0_4 .concat8 [ 1 1 1 1], L_0x1a06b30, L_0x1a07770, L_0x1a08370, L_0x1a09020; +LS_0x1a1ee00_0_8 .concat8 [ 1 1 1 1], L_0x1a09d20, L_0x1a0a9e0, L_0x1a0b5e0, L_0x1a0c210; +LS_0x1a1ee00_0_12 .concat8 [ 1 1 1 1], L_0x1a0cdb0, L_0x1a0d9d0, L_0x1a0e5d0, L_0x1a0f210; +LS_0x1a1ee00_0_16 .concat8 [ 1 1 1 1], L_0x1a10020, L_0x1a10dc0, L_0x1a11960, L_0x1a12570; +LS_0x1a1ee00_0_20 .concat8 [ 1 1 1 1], L_0x1a13160, L_0x1a13d70, L_0x1a14930, L_0x1a15590; +LS_0x1a1ee00_0_24 .concat8 [ 1 1 1 1], L_0x1a16170, L_0x1a16d90, L_0x1a17a20, L_0x1a185f0; +LS_0x1a1ee00_0_28 .concat8 [ 1 1 1 1], L_0x1a19210, L_0x1a19e50, L_0x1a1aa20, L_0x1a1b640; +LS_0x1a1ee00_0_32 .concat8 [ 1 0 0 0], L_0x1a1b120; +LS_0x1a1ee00_1_0 .concat8 [ 4 4 4 4], LS_0x1a1ee00_0_0, LS_0x1a1ee00_0_4, LS_0x1a1ee00_0_8, LS_0x1a1ee00_0_12; +LS_0x1a1ee00_1_4 .concat8 [ 4 4 4 4], LS_0x1a1ee00_0_16, LS_0x1a1ee00_0_20, LS_0x1a1ee00_0_24, LS_0x1a1ee00_0_28; +LS_0x1a1ee00_1_8 .concat8 [ 1 0 0 0], LS_0x1a1ee00_0_32; +L_0x1a1ee00 .concat8 [ 16 16 1 0], LS_0x1a1ee00_1_0, LS_0x1a1ee00_1_4, LS_0x1a1ee00_1_8; +L_0x1a22290 .part L_0x1a108f0, 31, 1; +L_0x1a21e70 .part/pv L_0x1a21fa0, 0, 1, 32; +L_0x1a22060 .part L_0x1a108f0, 0, 1; +L_0x1a22de0 .part v0x1a03ce0_0, 31, 1; +L_0x1a22e80 .part v0x1a03dd0_0, 31, 1; +L_0x1a22330 .part L_0x1a108f0, 31, 1; +L_0x1a257c0 .part L_0x1a1ee00, 32, 1; +L_0x1a22f70 .part L_0x1a1ee00, 32, 1; +S_0x18bfca0 .scope generate, "genblk1[0]" "genblk1[0]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x1833a40 .param/l "i" 0 3 165, +C4<00>; +S_0x18b9160 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x18bfca0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a04710 .functor XOR 1, L_0x1a04b40, L_0x1a04c30, C4<0>, C4<0>; +L_0x1a04810 .functor AND 1, L_0x1a04350, v0x19b9bb0_0, C4<1>, C4<1>; +L_0x1a048a0 .functor AND 1, L_0x1a04710, v0x19b9d40_0, C4<1>, C4<1>; +L_0x1a04910 .functor AND 1, L_0x1a04b40, v0x19b9b10_0, C4<1>, C4<1>; +L_0x1a04980 .functor OR 1, L_0x1a04810, L_0x1a048a0, L_0x1a04910, C4<0>; +v0x19b9400_0 .net "a", 0 0, L_0x1a04b40; 1 drivers +v0x19b94c0_0 .net "addRes", 0 0, L_0x1a04350; 1 drivers +v0x19b9590_0 .net "b", 0 0, L_0x1a04c30; 1 drivers +v0x19b9690_0 .net "carryIn", 0 0, L_0x1a04d60; 1 drivers +v0x19b9760_0 .net "carryOut", 0 0, L_0x1a045b0; 1 drivers +v0x19b9800_0 .net "finalA", 0 0, L_0x1a04910; 1 drivers +v0x19b98a0_0 .net "finalAdd", 0 0, L_0x1a04810; 1 drivers +v0x19b9940_0 .net "finalXor", 0 0, L_0x1a048a0; 1 drivers +v0x19b99e0_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19b9b10_0 .var "isA", 0 0; +v0x19b9bb0_0 .var "isAdd", 0 0; +v0x19b9c70_0 .var "isSubtract", 0 0; +v0x19b9d40_0 .var "isXor", 0 0; +v0x19b9de0_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19b9ec0_0 .net "res", 0 0, L_0x1a04980; 1 drivers +v0x19b9f80_0 .net "xorRes", 0 0, L_0x1a04710; 1 drivers +E_0x18beec0 .event edge, v0x19b99e0_0, v0x19b9de0_0; +S_0x18a5030 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x18b9160; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a04140 .functor XOR 1, L_0x1a04c30, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a04220 .functor XOR 1, L_0x1a04b40, L_0x1a04140, C4<0>, C4<0>; +L_0x1a04350 .functor XOR 1, L_0x1a04220, L_0x1a04d60, C4<0>, C4<0>; +L_0x1a044b0 .functor AND 1, L_0x1a04b40, L_0x1a04140, C4<1>, C4<1>; +L_0x1a04540 .functor AND 1, L_0x1a04220, L_0x1a04d60, C4<1>, C4<1>; +L_0x1a045b0 .functor OR 1, L_0x1a044b0, L_0x1a04540, C4<0>, C4<0>; +v0x18a4e10_0 .net "AandB", 0 0, L_0x1a044b0; 1 drivers +v0x19b8b50_0 .net "BxorSub", 0 0, L_0x1a04140; 1 drivers +v0x19b8c10_0 .net "a", 0 0, L_0x1a04b40; alias, 1 drivers +v0x19b8ce0_0 .net "b", 0 0, L_0x1a04c30; alias, 1 drivers +v0x19b8da0_0 .net "carryin", 0 0, L_0x1a04d60; alias, 1 drivers +v0x19b8eb0_0 .net "carryout", 0 0, L_0x1a045b0; alias, 1 drivers +v0x19b8f70_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19b9030_0 .net "res", 0 0, L_0x1a04350; alias, 1 drivers +v0x19b90f0_0 .net "xAorB", 0 0, L_0x1a04220; 1 drivers +v0x19b9240_0 .net "xAorBandCin", 0 0, L_0x1a04540; 1 drivers +S_0x19ba140 .scope generate, "genblk1[1]" "genblk1[1]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19ba300 .param/l "i" 0 3 165, +C4<01>; +S_0x19ba3c0 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19ba140; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a053f0 .functor XOR 1, L_0x1a057a0, L_0x1a05840, C4<0>, C4<0>; +L_0x1a054f0 .functor AND 1, L_0x1a05010, v0x19bbab0_0, C4<1>, C4<1>; +L_0x1a05560 .functor AND 1, L_0x1a053f0, v0x19bbbf0_0, C4<1>, C4<1>; +L_0x1a055d0 .functor AND 1, L_0x1a057a0, v0x19bba10_0, C4<1>, C4<1>; +L_0x1a05640 .functor OR 1, L_0x1a054f0, L_0x1a05560, L_0x1a055d0, C4<0>; +v0x19bb300_0 .net "a", 0 0, L_0x1a057a0; 1 drivers +v0x19bb3c0_0 .net "addRes", 0 0, L_0x1a05010; 1 drivers +v0x19bb460_0 .net "b", 0 0, L_0x1a05840; 1 drivers +v0x19bb560_0 .net "carryIn", 0 0, L_0x1a05970; 1 drivers +v0x19bb630_0 .net "carryOut", 0 0, L_0x1a05250; 1 drivers +v0x19bb6d0_0 .net "finalA", 0 0, L_0x1a055d0; 1 drivers +v0x19bb770_0 .net "finalAdd", 0 0, L_0x1a054f0; 1 drivers +v0x19bb810_0 .net "finalXor", 0 0, L_0x1a05560; 1 drivers +v0x19bb8b0_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19bba10_0 .var "isA", 0 0; +v0x19bbab0_0 .var "isAdd", 0 0; +v0x19bbb50_0 .var "isSubtract", 0 0; +v0x19bbbf0_0 .var "isXor", 0 0; +v0x19bbc90_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19bbd80_0 .net "res", 0 0, L_0x1a05640; 1 drivers +v0x19bbe20_0 .net "xorRes", 0 0, L_0x1a053f0; 1 drivers +S_0x19ba6b0 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19ba3c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a04e90 .functor XOR 1, L_0x1a05840, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a04f00 .functor XOR 1, L_0x1a057a0, L_0x1a04e90, C4<0>, C4<0>; +L_0x1a05010 .functor XOR 1, L_0x1a04f00, L_0x1a05970, C4<0>, C4<0>; +L_0x1a05170 .functor AND 1, L_0x1a057a0, L_0x1a04e90, C4<1>, C4<1>; +L_0x1a051e0 .functor AND 1, L_0x1a04f00, L_0x1a05970, C4<1>, C4<1>; +L_0x1a05250 .functor OR 1, L_0x1a05170, L_0x1a051e0, C4<0>, C4<0>; +v0x19ba940_0 .net "AandB", 0 0, L_0x1a05170; 1 drivers +v0x19baa20_0 .net "BxorSub", 0 0, L_0x1a04e90; 1 drivers +v0x19baae0_0 .net "a", 0 0, L_0x1a057a0; alias, 1 drivers +v0x19babb0_0 .net "b", 0 0, L_0x1a05840; alias, 1 drivers +v0x19bac70_0 .net "carryin", 0 0, L_0x1a05970; alias, 1 drivers +v0x19bad80_0 .net "carryout", 0 0, L_0x1a05250; alias, 1 drivers +v0x19bae40_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19baf30_0 .net "res", 0 0, L_0x1a05010; alias, 1 drivers +v0x19baff0_0 .net "xAorB", 0 0, L_0x1a04f00; 1 drivers +v0x19bb140_0 .net "xAorBandCin", 0 0, L_0x1a051e0; 1 drivers +S_0x19bbfe0 .scope generate, "genblk1[2]" "genblk1[2]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19bc1d0 .param/l "i" 0 3 165, +C4<010>; +S_0x19bc270 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19bbfe0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a06040 .functor XOR 1, L_0x1a063f0, L_0x1a06520, C4<0>, C4<0>; +L_0x1a06140 .functor AND 1, L_0x1a05c60, v0x19bd970_0, C4<1>, C4<1>; +L_0x1a061b0 .functor AND 1, L_0x1a06040, v0x19bdab0_0, C4<1>, C4<1>; +L_0x1a06220 .functor AND 1, L_0x1a063f0, v0x19bd8d0_0, C4<1>, C4<1>; +L_0x1a06290 .functor OR 1, L_0x1a06140, L_0x1a061b0, L_0x1a06220, C4<0>; +v0x19bd190_0 .net "a", 0 0, L_0x1a063f0; 1 drivers +v0x19bd280_0 .net "addRes", 0 0, L_0x1a05c60; 1 drivers +v0x19bd350_0 .net "b", 0 0, L_0x1a06520; 1 drivers +v0x19bd450_0 .net "carryIn", 0 0, L_0x1a066e0; 1 drivers +v0x19bd520_0 .net "carryOut", 0 0, L_0x1a05ea0; 1 drivers +v0x19bd5c0_0 .net "finalA", 0 0, L_0x1a06220; 1 drivers +v0x19bd660_0 .net "finalAdd", 0 0, L_0x1a06140; 1 drivers +v0x19bd700_0 .net "finalXor", 0 0, L_0x1a061b0; 1 drivers +v0x19bd7a0_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19bd8d0_0 .var "isA", 0 0; +v0x19bd970_0 .var "isAdd", 0 0; +v0x19bda10_0 .var "isSubtract", 0 0; +v0x19bdab0_0 .var "isXor", 0 0; +v0x19bdb70_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19bdc80_0 .net "res", 0 0, L_0x1a06290; 1 drivers +v0x19bdd40_0 .net "xorRes", 0 0, L_0x1a06040; 1 drivers +S_0x19bc560 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19bc270; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a05ae0 .functor XOR 1, L_0x1a06520, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a05b50 .functor XOR 1, L_0x1a063f0, L_0x1a05ae0, C4<0>, C4<0>; +L_0x1a05c60 .functor XOR 1, L_0x1a05b50, L_0x1a066e0, C4<0>, C4<0>; +L_0x1a05dc0 .functor AND 1, L_0x1a063f0, L_0x1a05ae0, C4<1>, C4<1>; +L_0x1a05e30 .functor AND 1, L_0x1a05b50, L_0x1a066e0, C4<1>, C4<1>; +L_0x1a05ea0 .functor OR 1, L_0x1a05dc0, L_0x1a05e30, C4<0>, C4<0>; +v0x19bc7f0_0 .net "AandB", 0 0, L_0x1a05dc0; 1 drivers +v0x19bc8d0_0 .net "BxorSub", 0 0, L_0x1a05ae0; 1 drivers +v0x19bc990_0 .net "a", 0 0, L_0x1a063f0; alias, 1 drivers +v0x19bca60_0 .net "b", 0 0, L_0x1a06520; alias, 1 drivers +v0x19bcb20_0 .net "carryin", 0 0, L_0x1a066e0; alias, 1 drivers +v0x19bcc30_0 .net "carryout", 0 0, L_0x1a05ea0; alias, 1 drivers +v0x19bccf0_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19bce20_0 .net "res", 0 0, L_0x1a05c60; alias, 1 drivers +v0x19bcee0_0 .net "xAorB", 0 0, L_0x1a05b50; 1 drivers +v0x19bd010_0 .net "xAorBandCin", 0 0, L_0x1a05e30; 1 drivers +S_0x19bdf50 .scope generate, "genblk1[3]" "genblk1[3]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19be110 .param/l "i" 0 3 165, +C4<011>; +S_0x19be1d0 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19bdf50; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a06c90 .functor XOR 1, L_0x1a07040, L_0x1a07140, C4<0>, C4<0>; +L_0x1a06d90 .functor AND 1, L_0x1a068f0, v0x19bf810_0, C4<1>, C4<1>; +L_0x1a06e00 .functor AND 1, L_0x1a06c90, v0x19bf950_0, C4<1>, C4<1>; +L_0x1a06e70 .functor AND 1, L_0x1a07040, v0x19bf770_0, C4<1>, C4<1>; +L_0x1a06ee0 .functor OR 1, L_0x1a06d90, L_0x1a06e00, L_0x1a06e70, C4<0>; +v0x19bf090_0 .net "a", 0 0, L_0x1a07040; 1 drivers +v0x19bf150_0 .net "addRes", 0 0, L_0x1a068f0; 1 drivers +v0x19bf1f0_0 .net "b", 0 0, L_0x1a07140; 1 drivers +v0x19bf2f0_0 .net "carryIn", 0 0, L_0x1a07270; 1 drivers +v0x19bf3c0_0 .net "carryOut", 0 0, L_0x1a06b30; 1 drivers +v0x19bf460_0 .net "finalA", 0 0, L_0x1a06e70; 1 drivers +v0x19bf500_0 .net "finalAdd", 0 0, L_0x1a06d90; 1 drivers +v0x19bf5a0_0 .net "finalXor", 0 0, L_0x1a06e00; 1 drivers +v0x19bf640_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19bf770_0 .var "isA", 0 0; +v0x19bf810_0 .var "isAdd", 0 0; +v0x19bf8b0_0 .var "isSubtract", 0 0; +v0x19bf950_0 .var "isXor", 0 0; +v0x19bfa10_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19bfad0_0 .net "res", 0 0, L_0x1a06ee0; 1 drivers +v0x19bfb90_0 .net "xorRes", 0 0, L_0x1a06c90; 1 drivers +S_0x19be4c0 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19be1d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a06810 .functor XOR 1, L_0x1a07140, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a06880 .functor XOR 1, L_0x1a07040, L_0x1a06810, C4<0>, C4<0>; +L_0x1a068f0 .functor XOR 1, L_0x1a06880, L_0x1a07270, C4<0>, C4<0>; +L_0x1a06a50 .functor AND 1, L_0x1a07040, L_0x1a06810, C4<1>, C4<1>; +L_0x1a06ac0 .functor AND 1, L_0x1a06880, L_0x1a07270, C4<1>, C4<1>; +L_0x1a06b30 .functor OR 1, L_0x1a06a50, L_0x1a06ac0, C4<0>, C4<0>; +v0x19be750_0 .net "AandB", 0 0, L_0x1a06a50; 1 drivers +v0x19be830_0 .net "BxorSub", 0 0, L_0x1a06810; 1 drivers +v0x19be8f0_0 .net "a", 0 0, L_0x1a07040; alias, 1 drivers +v0x19be990_0 .net "b", 0 0, L_0x1a07140; alias, 1 drivers +v0x19bea50_0 .net "carryin", 0 0, L_0x1a07270; alias, 1 drivers +v0x19beb60_0 .net "carryout", 0 0, L_0x1a06b30; alias, 1 drivers +v0x19bec20_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19becc0_0 .net "res", 0 0, L_0x1a068f0; alias, 1 drivers +v0x19bed80_0 .net "xAorB", 0 0, L_0x1a06880; 1 drivers +v0x19beed0_0 .net "xAorBandCin", 0 0, L_0x1a06ac0; 1 drivers +S_0x19bfd50 .scope generate, "genblk1[4]" "genblk1[4]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19bff60 .param/l "i" 0 3 165, +C4<0100>; +S_0x19c0020 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19bfd50; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a07910 .functor XOR 1, L_0x1a07cf0, L_0x1a07d90, C4<0>, C4<0>; +L_0x1a07a10 .functor AND 1, L_0x1a07580, v0x19c17b0_0, C4<1>, C4<1>; +L_0x1a07a80 .functor AND 1, L_0x1a07910, v0x19c18f0_0, C4<1>, C4<1>; +L_0x1a07af0 .functor AND 1, L_0x1a07cf0, v0x19c1710_0, C4<1>, C4<1>; +L_0x1a07b60 .functor OR 1, L_0x1a07a10, L_0x1a07a80, L_0x1a07af0, C4<0>; +v0x19c0f70_0 .net "a", 0 0, L_0x1a07cf0; 1 drivers +v0x19c1030_0 .net "addRes", 0 0, L_0x1a07580; 1 drivers +v0x19c1100_0 .net "b", 0 0, L_0x1a07d90; 1 drivers +v0x19c1200_0 .net "carryIn", 0 0, L_0x1a07f40; 1 drivers +v0x19c12d0_0 .net "carryOut", 0 0, L_0x1a07770; 1 drivers +v0x19c1370_0 .net "finalA", 0 0, L_0x1a07af0; 1 drivers +v0x19c1410_0 .net "finalAdd", 0 0, L_0x1a07a10; 1 drivers +v0x19c14b0_0 .net "finalXor", 0 0, L_0x1a07a80; 1 drivers +v0x19c1550_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19c1710_0 .var "isA", 0 0; +v0x19c17b0_0 .var "isAdd", 0 0; +v0x19c1850_0 .var "isSubtract", 0 0; +v0x19c18f0_0 .var "isXor", 0 0; +v0x19c19b0_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19c1b00_0 .net "res", 0 0, L_0x1a07b60; 1 drivers +v0x19c1bc0_0 .net "xorRes", 0 0, L_0x1a07910; 1 drivers +S_0x19c0310 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19c0020; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a074a0 .functor XOR 1, L_0x1a07d90, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a07510 .functor XOR 1, L_0x1a07cf0, L_0x1a074a0, C4<0>, C4<0>; +L_0x1a07580 .functor XOR 1, L_0x1a07510, L_0x1a07f40, C4<0>, C4<0>; +L_0x1a07690 .functor AND 1, L_0x1a07cf0, L_0x1a074a0, C4<1>, C4<1>; +L_0x1a07700 .functor AND 1, L_0x1a07510, L_0x1a07f40, C4<1>, C4<1>; +L_0x1a07770 .functor OR 1, L_0x1a07690, L_0x1a07700, C4<0>, C4<0>; +v0x19c05a0_0 .net "AandB", 0 0, L_0x1a07690; 1 drivers +v0x19c0680_0 .net "BxorSub", 0 0, L_0x1a074a0; 1 drivers +v0x19c0740_0 .net "a", 0 0, L_0x1a07cf0; alias, 1 drivers +v0x19c07e0_0 .net "b", 0 0, L_0x1a07d90; alias, 1 drivers +v0x19c08a0_0 .net "carryin", 0 0, L_0x1a07f40; alias, 1 drivers +v0x19c09b0_0 .net "carryout", 0 0, L_0x1a07770; alias, 1 drivers +v0x19c0a70_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19c0c20_0 .net "res", 0 0, L_0x1a07580; alias, 1 drivers +v0x19c0cc0_0 .net "xAorB", 0 0, L_0x1a07510; 1 drivers +v0x19c0df0_0 .net "xAorBandCin", 0 0, L_0x1a07700; 1 drivers +S_0x19c1d80 .scope generate, "genblk1[5]" "genblk1[5]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19bcbc0 .param/l "i" 0 3 165, +C4<0101>; +S_0x19c1f60 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19c1d80; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a08510 .functor XOR 1, L_0x1a088f0, L_0x1a08a20, C4<0>, C4<0>; +L_0x1a08610 .functor AND 1, L_0x1a08130, v0x19c3600_0, C4<1>, C4<1>; +L_0x1a08680 .functor AND 1, L_0x1a08510, v0x19c3740_0, C4<1>, C4<1>; +L_0x1a086f0 .functor AND 1, L_0x1a088f0, v0x19c3560_0, C4<1>, C4<1>; +L_0x1a08760 .functor OR 1, L_0x1a08610, L_0x1a08680, L_0x1a086f0, C4<0>; +v0x19c2e50_0 .net "a", 0 0, L_0x1a088f0; 1 drivers +v0x19c2f10_0 .net "addRes", 0 0, L_0x1a08130; 1 drivers +v0x19c2fe0_0 .net "b", 0 0, L_0x1a08a20; 1 drivers +v0x19c30e0_0 .net "carryIn", 0 0, L_0x1a08b50; 1 drivers +v0x19c31b0_0 .net "carryOut", 0 0, L_0x1a08370; 1 drivers +v0x19c3250_0 .net "finalA", 0 0, L_0x1a086f0; 1 drivers +v0x19c32f0_0 .net "finalAdd", 0 0, L_0x1a08610; 1 drivers +v0x19c3390_0 .net "finalXor", 0 0, L_0x1a08680; 1 drivers +v0x19c3430_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19c3560_0 .var "isA", 0 0; +v0x19c3600_0 .var "isAdd", 0 0; +v0x19c36a0_0 .var "isSubtract", 0 0; +v0x19c3740_0 .var "isXor", 0 0; +v0x19c3800_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19c38c0_0 .net "res", 0 0, L_0x1a08760; 1 drivers +v0x19c3980_0 .net "xorRes", 0 0, L_0x1a08510; 1 drivers +S_0x19c2250 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19c1f60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a07430 .functor XOR 1, L_0x1a08a20, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a08070 .functor XOR 1, L_0x1a088f0, L_0x1a07430, C4<0>, C4<0>; +L_0x1a08130 .functor XOR 1, L_0x1a08070, L_0x1a08b50, C4<0>, C4<0>; +L_0x1a08290 .functor AND 1, L_0x1a088f0, L_0x1a07430, C4<1>, C4<1>; +L_0x1a08300 .functor AND 1, L_0x1a08070, L_0x1a08b50, C4<1>, C4<1>; +L_0x1a08370 .functor OR 1, L_0x1a08290, L_0x1a08300, C4<0>, C4<0>; +v0x19c24e0_0 .net "AandB", 0 0, L_0x1a08290; 1 drivers +v0x19c25c0_0 .net "BxorSub", 0 0, L_0x1a07430; 1 drivers +v0x19c2680_0 .net "a", 0 0, L_0x1a088f0; alias, 1 drivers +v0x19c2750_0 .net "b", 0 0, L_0x1a08a20; alias, 1 drivers +v0x19c2810_0 .net "carryin", 0 0, L_0x1a08b50; alias, 1 drivers +v0x19c2920_0 .net "carryout", 0 0, L_0x1a08370; alias, 1 drivers +v0x19c29e0_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19c2a80_0 .net "res", 0 0, L_0x1a08130; alias, 1 drivers +v0x19c2b40_0 .net "xAorB", 0 0, L_0x1a08070; 1 drivers +v0x19c2c90_0 .net "xAorBandCin", 0 0, L_0x1a08300; 1 drivers +S_0x19c3b40 .scope generate, "genblk1[6]" "genblk1[6]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19c3d00 .param/l "i" 0 3 165, +C4<0110>; +S_0x19c3dc0 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19c3b40; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a091c0 .functor XOR 1, L_0x1a095a0, L_0x1a09750, C4<0>, C4<0>; +L_0x1a092c0 .functor AND 1, L_0x1a08de0, v0x19c5460_0, C4<1>, C4<1>; +L_0x1a09330 .functor AND 1, L_0x1a091c0, v0x19c55a0_0, C4<1>, C4<1>; +L_0x1a093a0 .functor AND 1, L_0x1a095a0, v0x19c53c0_0, C4<1>, C4<1>; +L_0x1a09410 .functor OR 1, L_0x1a092c0, L_0x1a09330, L_0x1a093a0, C4<0>; +v0x19c4cb0_0 .net "a", 0 0, L_0x1a095a0; 1 drivers +v0x19c4d70_0 .net "addRes", 0 0, L_0x1a08de0; 1 drivers +v0x19c4e40_0 .net "b", 0 0, L_0x1a09750; 1 drivers +v0x19c4f40_0 .net "carryIn", 0 0, L_0x1a08c80; 1 drivers +v0x19c5010_0 .net "carryOut", 0 0, L_0x1a09020; 1 drivers +v0x19c50b0_0 .net "finalA", 0 0, L_0x1a093a0; 1 drivers +v0x19c5150_0 .net "finalAdd", 0 0, L_0x1a092c0; 1 drivers +v0x19c51f0_0 .net "finalXor", 0 0, L_0x1a09330; 1 drivers +v0x19c5290_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19c53c0_0 .var "isA", 0 0; +v0x19c5460_0 .var "isAdd", 0 0; +v0x19c5500_0 .var "isSubtract", 0 0; +v0x19c55a0_0 .var "isXor", 0 0; +v0x19c5660_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19c5720_0 .net "res", 0 0, L_0x1a09410; 1 drivers +v0x19c57e0_0 .net "xorRes", 0 0, L_0x1a091c0; 1 drivers +S_0x19c40b0 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19c3dc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a08990 .functor XOR 1, L_0x1a09750, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a08d20 .functor XOR 1, L_0x1a095a0, L_0x1a08990, C4<0>, C4<0>; +L_0x1a08de0 .functor XOR 1, L_0x1a08d20, L_0x1a08c80, C4<0>, C4<0>; +L_0x1a08f40 .functor AND 1, L_0x1a095a0, L_0x1a08990, C4<1>, C4<1>; +L_0x1a08fb0 .functor AND 1, L_0x1a08d20, L_0x1a08c80, C4<1>, C4<1>; +L_0x1a09020 .functor OR 1, L_0x1a08f40, L_0x1a08fb0, C4<0>, C4<0>; +v0x19c4340_0 .net "AandB", 0 0, L_0x1a08f40; 1 drivers +v0x19c4420_0 .net "BxorSub", 0 0, L_0x1a08990; 1 drivers +v0x19c44e0_0 .net "a", 0 0, L_0x1a095a0; alias, 1 drivers +v0x19c45b0_0 .net "b", 0 0, L_0x1a09750; alias, 1 drivers +v0x19c4670_0 .net "carryin", 0 0, L_0x1a08c80; alias, 1 drivers +v0x19c4780_0 .net "carryout", 0 0, L_0x1a09020; alias, 1 drivers +v0x19c4840_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19c48e0_0 .net "res", 0 0, L_0x1a08de0; alias, 1 drivers +v0x19c49a0_0 .net "xAorB", 0 0, L_0x1a08d20; 1 drivers +v0x19c4af0_0 .net "xAorBandCin", 0 0, L_0x1a08fb0; 1 drivers +S_0x19c59a0 .scope generate, "genblk1[7]" "genblk1[7]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19c5b60 .param/l "i" 0 3 165, +C4<0111>; +S_0x19c5c20 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19c59a0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a09ec0 .functor XOR 1, L_0x1a0a2a0, L_0x1a09900, C4<0>, C4<0>; +L_0x1a09fc0 .functor AND 1, L_0x1a09ae0, v0x19c72c0_0, C4<1>, C4<1>; +L_0x1a0a030 .functor AND 1, L_0x1a09ec0, v0x19c7400_0, C4<1>, C4<1>; +L_0x1a0a0a0 .functor AND 1, L_0x1a0a2a0, v0x19c7220_0, C4<1>, C4<1>; +L_0x1a0a110 .functor OR 1, L_0x1a09fc0, L_0x1a0a030, L_0x1a0a0a0, C4<0>; +v0x19c6b10_0 .net "a", 0 0, L_0x1a0a2a0; 1 drivers +v0x19c6bd0_0 .net "addRes", 0 0, L_0x1a09ae0; 1 drivers +v0x19c6ca0_0 .net "b", 0 0, L_0x1a09900; 1 drivers +v0x19c6da0_0 .net "carryIn", 0 0, L_0x1a0a490; 1 drivers +v0x19c6e70_0 .net "carryOut", 0 0, L_0x1a09d20; 1 drivers +v0x19c6f10_0 .net "finalA", 0 0, L_0x1a0a0a0; 1 drivers +v0x19c6fb0_0 .net "finalAdd", 0 0, L_0x1a09fc0; 1 drivers +v0x19c7050_0 .net "finalXor", 0 0, L_0x1a0a030; 1 drivers +v0x19c70f0_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19c7220_0 .var "isA", 0 0; +v0x19c72c0_0 .var "isAdd", 0 0; +v0x19c7360_0 .var "isSubtract", 0 0; +v0x19c7400_0 .var "isXor", 0 0; +v0x19c74c0_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19c7580_0 .net "res", 0 0, L_0x1a0a110; 1 drivers +v0x19c7640_0 .net "xorRes", 0 0, L_0x1a09ec0; 1 drivers +S_0x19c5f10 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19c5c20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a099b0 .functor XOR 1, L_0x1a09900, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a09a20 .functor XOR 1, L_0x1a0a2a0, L_0x1a099b0, C4<0>, C4<0>; +L_0x1a09ae0 .functor XOR 1, L_0x1a09a20, L_0x1a0a490, C4<0>, C4<0>; +L_0x1a09c40 .functor AND 1, L_0x1a0a2a0, L_0x1a099b0, C4<1>, C4<1>; +L_0x1a09cb0 .functor AND 1, L_0x1a09a20, L_0x1a0a490, C4<1>, C4<1>; +L_0x1a09d20 .functor OR 1, L_0x1a09c40, L_0x1a09cb0, C4<0>, C4<0>; +v0x19c61a0_0 .net "AandB", 0 0, L_0x1a09c40; 1 drivers +v0x19c6280_0 .net "BxorSub", 0 0, L_0x1a099b0; 1 drivers +v0x19c6340_0 .net "a", 0 0, L_0x1a0a2a0; alias, 1 drivers +v0x19c6410_0 .net "b", 0 0, L_0x1a09900; alias, 1 drivers +v0x19c64d0_0 .net "carryin", 0 0, L_0x1a0a490; alias, 1 drivers +v0x19c65e0_0 .net "carryout", 0 0, L_0x1a09d20; alias, 1 drivers +v0x19c66a0_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19c6740_0 .net "res", 0 0, L_0x1a09ae0; alias, 1 drivers +v0x19c6800_0 .net "xAorB", 0 0, L_0x1a09a20; 1 drivers +v0x19c6950_0 .net "xAorBandCin", 0 0, L_0x1a09cb0; 1 drivers +S_0x19c7800 .scope generate, "genblk1[8]" "genblk1[8]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19bff10 .param/l "i" 0 3 165, +C4<01000>; +S_0x19c7ac0 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19c7800; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a0ab80 .functor XOR 1, L_0x1a0af30, L_0x1a0afd0, C4<0>, C4<0>; +L_0x1a0ac80 .functor AND 1, L_0x1a0a7a0, v0x19c9380_0, C4<1>, C4<1>; +L_0x1a0acf0 .functor AND 1, L_0x1a0ab80, v0x19c94c0_0, C4<1>, C4<1>; +L_0x1a0ad60 .functor AND 1, L_0x1a0af30, v0x19c92e0_0, C4<1>, C4<1>; +L_0x1a0add0 .functor OR 1, L_0x1a0ac80, L_0x1a0acf0, L_0x1a0ad60, C4<0>; +v0x19c8ac0_0 .net "a", 0 0, L_0x1a0af30; 1 drivers +v0x19c8b80_0 .net "addRes", 0 0, L_0x1a0a7a0; 1 drivers +v0x19c8c50_0 .net "b", 0 0, L_0x1a0afd0; 1 drivers +v0x19c8d50_0 .net "carryIn", 0 0, L_0x1a0a6d0; 1 drivers +v0x19c8e20_0 .net "carryOut", 0 0, L_0x1a0a9e0; 1 drivers +v0x19c8ec0_0 .net "finalA", 0 0, L_0x1a0ad60; 1 drivers +v0x19c8f60_0 .net "finalAdd", 0 0, L_0x1a0ac80; 1 drivers +v0x19c9000_0 .net "finalXor", 0 0, L_0x1a0acf0; 1 drivers +v0x19c90a0_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19c92e0_0 .var "isA", 0 0; +v0x19c9380_0 .var "isAdd", 0 0; +v0x19c9420_0 .var "isSubtract", 0 0; +v0x19c94c0_0 .var "isXor", 0 0; +v0x19c9560_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19c9710_0 .net "res", 0 0, L_0x1a0add0; 1 drivers +v0x19c97b0_0 .net "xorRes", 0 0, L_0x1a0ab80; 1 drivers +S_0x19c7db0 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19c7ac0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a073a0 .functor XOR 1, L_0x1a0afd0, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a0a340 .functor XOR 1, L_0x1a0af30, L_0x1a073a0, C4<0>, C4<0>; +L_0x1a0a7a0 .functor XOR 1, L_0x1a0a340, L_0x1a0a6d0, C4<0>, C4<0>; +L_0x1a0a900 .functor AND 1, L_0x1a0af30, L_0x1a073a0, C4<1>, C4<1>; +L_0x1a0a970 .functor AND 1, L_0x1a0a340, L_0x1a0a6d0, C4<1>, C4<1>; +L_0x1a0a9e0 .functor OR 1, L_0x1a0a900, L_0x1a0a970, C4<0>, C4<0>; +v0x19c8040_0 .net "AandB", 0 0, L_0x1a0a900; 1 drivers +v0x19c8120_0 .net "BxorSub", 0 0, L_0x1a073a0; 1 drivers +v0x19c81e0_0 .net "a", 0 0, L_0x1a0af30; alias, 1 drivers +v0x19c82b0_0 .net "b", 0 0, L_0x1a0afd0; alias, 1 drivers +v0x19c8370_0 .net "carryin", 0 0, L_0x1a0a6d0; alias, 1 drivers +v0x19c8480_0 .net "carryout", 0 0, L_0x1a0a9e0; alias, 1 drivers +v0x19c8540_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19c0b10_0 .net "res", 0 0, L_0x1a0a7a0; alias, 1 drivers +v0x19c87f0_0 .net "xAorB", 0 0, L_0x1a0a340; 1 drivers +v0x19c8920_0 .net "xAorBandCin", 0 0, L_0x1a0a970; 1 drivers +S_0x19c98d0 .scope generate, "genblk1[9]" "genblk1[9]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19c9a90 .param/l "i" 0 3 165, +C4<01001>; +S_0x19c9b50 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19c98d0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a0b780 .functor XOR 1, L_0x1a0bb30, L_0x1a0b100, C4<0>, C4<0>; +L_0x1a0b880 .functor AND 1, L_0x1a0b3a0, v0x19cb1f0_0, C4<1>, C4<1>; +L_0x1a0b8f0 .functor AND 1, L_0x1a0b780, v0x19cb330_0, C4<1>, C4<1>; +L_0x1a0b960 .functor AND 1, L_0x1a0bb30, v0x19cb150_0, C4<1>, C4<1>; +L_0x1a0b9d0 .functor OR 1, L_0x1a0b880, L_0x1a0b8f0, L_0x1a0b960, C4<0>; +v0x19caa40_0 .net "a", 0 0, L_0x1a0bb30; 1 drivers +v0x19cab00_0 .net "addRes", 0 0, L_0x1a0b3a0; 1 drivers +v0x19cabd0_0 .net "b", 0 0, L_0x1a0b100; 1 drivers +v0x19cacd0_0 .net "carryIn", 0 0, L_0x1a0bd50; 1 drivers +v0x19cada0_0 .net "carryOut", 0 0, L_0x1a0b5e0; 1 drivers +v0x19cae40_0 .net "finalA", 0 0, L_0x1a0b960; 1 drivers +v0x19caee0_0 .net "finalAdd", 0 0, L_0x1a0b880; 1 drivers +v0x19caf80_0 .net "finalXor", 0 0, L_0x1a0b8f0; 1 drivers +v0x19cb020_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19cb150_0 .var "isA", 0 0; +v0x19cb1f0_0 .var "isAdd", 0 0; +v0x19cb290_0 .var "isSubtract", 0 0; +v0x19cb330_0 .var "isXor", 0 0; +v0x19cb3f0_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19cb4b0_0 .net "res", 0 0, L_0x1a0b9d0; 1 drivers +v0x19cb570_0 .net "xorRes", 0 0, L_0x1a0b780; 1 drivers +S_0x19c9e40 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19c9b50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a0b270 .functor XOR 1, L_0x1a0b100, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a0b2e0 .functor XOR 1, L_0x1a0bb30, L_0x1a0b270, C4<0>, C4<0>; +L_0x1a0b3a0 .functor XOR 1, L_0x1a0b2e0, L_0x1a0bd50, C4<0>, C4<0>; +L_0x1a0b500 .functor AND 1, L_0x1a0bb30, L_0x1a0b270, C4<1>, C4<1>; +L_0x1a0b570 .functor AND 1, L_0x1a0b2e0, L_0x1a0bd50, C4<1>, C4<1>; +L_0x1a0b5e0 .functor OR 1, L_0x1a0b500, L_0x1a0b570, C4<0>, C4<0>; +v0x19ca0d0_0 .net "AandB", 0 0, L_0x1a0b500; 1 drivers +v0x19ca1b0_0 .net "BxorSub", 0 0, L_0x1a0b270; 1 drivers +v0x19ca270_0 .net "a", 0 0, L_0x1a0bb30; alias, 1 drivers +v0x19ca340_0 .net "b", 0 0, L_0x1a0b100; alias, 1 drivers +v0x19ca400_0 .net "carryin", 0 0, L_0x1a0bd50; alias, 1 drivers +v0x19ca510_0 .net "carryout", 0 0, L_0x1a0b5e0; alias, 1 drivers +v0x19ca5d0_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19ca670_0 .net "res", 0 0, L_0x1a0b3a0; alias, 1 drivers +v0x19ca730_0 .net "xAorB", 0 0, L_0x1a0b2e0; 1 drivers +v0x19ca880_0 .net "xAorBandCin", 0 0, L_0x1a0b570; 1 drivers +S_0x19cb730 .scope generate, "genblk1[10]" "genblk1[10]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19cb8f0 .param/l "i" 0 3 165, +C4<01010>; +S_0x19cb9b0 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19cb730; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a0c370 .functor XOR 1, L_0x1a0c720, L_0x1a0c7c0, C4<0>, C4<0>; +L_0x1a0c470 .functor AND 1, L_0x1a0bfd0, v0x19cd050_0, C4<1>, C4<1>; +L_0x1a0c4e0 .functor AND 1, L_0x1a0c370, v0x19cd190_0, C4<1>, C4<1>; +L_0x1a0c550 .functor AND 1, L_0x1a0c720, v0x19ccfb0_0, C4<1>, C4<1>; +L_0x1a0c5c0 .functor OR 1, L_0x1a0c470, L_0x1a0c4e0, L_0x1a0c550, C4<0>; +v0x19cc8a0_0 .net "a", 0 0, L_0x1a0c720; 1 drivers +v0x19cc960_0 .net "addRes", 0 0, L_0x1a0bfd0; 1 drivers +v0x19cca30_0 .net "b", 0 0, L_0x1a0c7c0; 1 drivers +v0x19ccb30_0 .net "carryIn", 0 0, L_0x1a0be80; 1 drivers +v0x19ccc00_0 .net "carryOut", 0 0, L_0x1a0c210; 1 drivers +v0x19ccca0_0 .net "finalA", 0 0, L_0x1a0c550; 1 drivers +v0x19ccd40_0 .net "finalAdd", 0 0, L_0x1a0c470; 1 drivers +v0x19ccde0_0 .net "finalXor", 0 0, L_0x1a0c4e0; 1 drivers +v0x19cce80_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19ccfb0_0 .var "isA", 0 0; +v0x19cd050_0 .var "isAdd", 0 0; +v0x19cd0f0_0 .var "isSubtract", 0 0; +v0x19cd190_0 .var "isXor", 0 0; +v0x19cd250_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19cd310_0 .net "res", 0 0, L_0x1a0c5c0; 1 drivers +v0x19cd3d0_0 .net "xorRes", 0 0, L_0x1a0c370; 1 drivers +S_0x19cbca0 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19cb9b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a0bbd0 .functor XOR 1, L_0x1a0c7c0, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a0bc40 .functor XOR 1, L_0x1a0c720, L_0x1a0bbd0, C4<0>, C4<0>; +L_0x1a0bfd0 .functor XOR 1, L_0x1a0bc40, L_0x1a0be80, C4<0>, C4<0>; +L_0x1a0c130 .functor AND 1, L_0x1a0c720, L_0x1a0bbd0, C4<1>, C4<1>; +L_0x1a0c1a0 .functor AND 1, L_0x1a0bc40, L_0x1a0be80, C4<1>, C4<1>; +L_0x1a0c210 .functor OR 1, L_0x1a0c130, L_0x1a0c1a0, C4<0>, C4<0>; +v0x19cbf30_0 .net "AandB", 0 0, L_0x1a0c130; 1 drivers +v0x19cc010_0 .net "BxorSub", 0 0, L_0x1a0bbd0; 1 drivers +v0x19cc0d0_0 .net "a", 0 0, L_0x1a0c720; alias, 1 drivers +v0x19cc1a0_0 .net "b", 0 0, L_0x1a0c7c0; alias, 1 drivers +v0x19cc260_0 .net "carryin", 0 0, L_0x1a0be80; alias, 1 drivers +v0x19cc370_0 .net "carryout", 0 0, L_0x1a0c210; alias, 1 drivers +v0x19cc430_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19cc4d0_0 .net "res", 0 0, L_0x1a0bfd0; alias, 1 drivers +v0x19cc590_0 .net "xAorB", 0 0, L_0x1a0bc40; 1 drivers +v0x19cc6e0_0 .net "xAorBandCin", 0 0, L_0x1a0c1a0; 1 drivers +S_0x19cd590 .scope generate, "genblk1[11]" "genblk1[11]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19cd750 .param/l "i" 0 3 165, +C4<01011>; +S_0x19cd810 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19cd590; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a0cf50 .functor XOR 1, L_0x1a0d330, L_0x1a0c8f0, C4<0>, C4<0>; +L_0x1a0d050 .functor AND 1, L_0x1a0cb70, v0x19ceeb0_0, C4<1>, C4<1>; +L_0x1a0d0c0 .functor AND 1, L_0x1a0cf50, v0x19ceff0_0, C4<1>, C4<1>; +L_0x1a0d130 .functor AND 1, L_0x1a0d330, v0x19cee10_0, C4<1>, C4<1>; +L_0x1a0d1a0 .functor OR 1, L_0x1a0d050, L_0x1a0d0c0, L_0x1a0d130, C4<0>; +v0x19ce700_0 .net "a", 0 0, L_0x1a0d330; 1 drivers +v0x19ce7c0_0 .net "addRes", 0 0, L_0x1a0cb70; 1 drivers +v0x19ce890_0 .net "b", 0 0, L_0x1a0c8f0; 1 drivers +v0x19ce990_0 .net "carryIn", 0 0, L_0x1a0d580; 1 drivers +v0x19cea60_0 .net "carryOut", 0 0, L_0x1a0cdb0; 1 drivers +v0x19ceb00_0 .net "finalA", 0 0, L_0x1a0d130; 1 drivers +v0x19ceba0_0 .net "finalAdd", 0 0, L_0x1a0d050; 1 drivers +v0x19cec40_0 .net "finalXor", 0 0, L_0x1a0d0c0; 1 drivers +v0x19cece0_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19cee10_0 .var "isA", 0 0; +v0x19ceeb0_0 .var "isAdd", 0 0; +v0x19cef50_0 .var "isSubtract", 0 0; +v0x19ceff0_0 .var "isXor", 0 0; +v0x19cf0b0_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19cf170_0 .net "res", 0 0, L_0x1a0d1a0; 1 drivers +v0x19cf230_0 .net "xorRes", 0 0, L_0x1a0cf50; 1 drivers +S_0x19cdb00 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19cd810; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a0ca90 .functor XOR 1, L_0x1a0c8f0, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a0cb00 .functor XOR 1, L_0x1a0d330, L_0x1a0ca90, C4<0>, C4<0>; +L_0x1a0cb70 .functor XOR 1, L_0x1a0cb00, L_0x1a0d580, C4<0>, C4<0>; +L_0x1a0ccd0 .functor AND 1, L_0x1a0d330, L_0x1a0ca90, C4<1>, C4<1>; +L_0x1a0cd40 .functor AND 1, L_0x1a0cb00, L_0x1a0d580, C4<1>, C4<1>; +L_0x1a0cdb0 .functor OR 1, L_0x1a0ccd0, L_0x1a0cd40, C4<0>, C4<0>; +v0x19cdd90_0 .net "AandB", 0 0, L_0x1a0ccd0; 1 drivers +v0x19cde70_0 .net "BxorSub", 0 0, L_0x1a0ca90; 1 drivers +v0x19cdf30_0 .net "a", 0 0, L_0x1a0d330; alias, 1 drivers +v0x19ce000_0 .net "b", 0 0, L_0x1a0c8f0; alias, 1 drivers +v0x19ce0c0_0 .net "carryin", 0 0, L_0x1a0d580; alias, 1 drivers +v0x19ce1d0_0 .net "carryout", 0 0, L_0x1a0cdb0; alias, 1 drivers +v0x19ce290_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19ce330_0 .net "res", 0 0, L_0x1a0cb70; alias, 1 drivers +v0x19ce3f0_0 .net "xAorB", 0 0, L_0x1a0cb00; 1 drivers +v0x19ce540_0 .net "xAorBandCin", 0 0, L_0x1a0cd40; 1 drivers +S_0x19cf3f0 .scope generate, "genblk1[12]" "genblk1[12]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19cf5b0 .param/l "i" 0 3 165, +C4<01100>; +S_0x19cf670 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19cf3f0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a0db70 .functor XOR 1, L_0x1a0df50, L_0x1a0dff0, C4<0>, C4<0>; +L_0x1a0dc70 .functor AND 1, L_0x1a0d7e0, v0x19d0d10_0, C4<1>, C4<1>; +L_0x1a0dce0 .functor AND 1, L_0x1a0db70, v0x19d0e50_0, C4<1>, C4<1>; +L_0x1a0dd50 .functor AND 1, L_0x1a0df50, v0x19d0c70_0, C4<1>, C4<1>; +L_0x1a0ddc0 .functor OR 1, L_0x1a0dc70, L_0x1a0dce0, L_0x1a0dd50, C4<0>; +v0x19d0560_0 .net "a", 0 0, L_0x1a0df50; 1 drivers +v0x19d0620_0 .net "addRes", 0 0, L_0x1a0d7e0; 1 drivers +v0x19d06f0_0 .net "b", 0 0, L_0x1a0dff0; 1 drivers +v0x19d07f0_0 .net "carryIn", 0 0, L_0x1a0d6b0; 1 drivers +v0x19d08c0_0 .net "carryOut", 0 0, L_0x1a0d9d0; 1 drivers +v0x19d0960_0 .net "finalA", 0 0, L_0x1a0dd50; 1 drivers +v0x19d0a00_0 .net "finalAdd", 0 0, L_0x1a0dc70; 1 drivers +v0x19d0aa0_0 .net "finalXor", 0 0, L_0x1a0dce0; 1 drivers +v0x19d0b40_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19d0c70_0 .var "isA", 0 0; +v0x19d0d10_0 .var "isAdd", 0 0; +v0x19d0db0_0 .var "isSubtract", 0 0; +v0x19d0e50_0 .var "isXor", 0 0; +v0x19d0f10_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19d0fd0_0 .net "res", 0 0, L_0x1a0ddc0; 1 drivers +v0x19d1090_0 .net "xorRes", 0 0, L_0x1a0db70; 1 drivers +S_0x19cf960 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19cf670; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a0c990 .functor XOR 1, L_0x1a0dff0, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a0d3d0 .functor XOR 1, L_0x1a0df50, L_0x1a0c990, C4<0>, C4<0>; +L_0x1a0d7e0 .functor XOR 1, L_0x1a0d3d0, L_0x1a0d6b0, C4<0>, C4<0>; +L_0x1a0d8f0 .functor AND 1, L_0x1a0df50, L_0x1a0c990, C4<1>, C4<1>; +L_0x1a0d960 .functor AND 1, L_0x1a0d3d0, L_0x1a0d6b0, C4<1>, C4<1>; +L_0x1a0d9d0 .functor OR 1, L_0x1a0d8f0, L_0x1a0d960, C4<0>, C4<0>; +v0x19cfbf0_0 .net "AandB", 0 0, L_0x1a0d8f0; 1 drivers +v0x19cfcd0_0 .net "BxorSub", 0 0, L_0x1a0c990; 1 drivers +v0x19cfd90_0 .net "a", 0 0, L_0x1a0df50; alias, 1 drivers +v0x19cfe60_0 .net "b", 0 0, L_0x1a0dff0; alias, 1 drivers +v0x19cff20_0 .net "carryin", 0 0, L_0x1a0d6b0; alias, 1 drivers +v0x19d0030_0 .net "carryout", 0 0, L_0x1a0d9d0; alias, 1 drivers +v0x19d00f0_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19d0190_0 .net "res", 0 0, L_0x1a0d7e0; alias, 1 drivers +v0x19d0250_0 .net "xAorB", 0 0, L_0x1a0d3d0; 1 drivers +v0x19d03a0_0 .net "xAorBandCin", 0 0, L_0x1a0d960; 1 drivers +S_0x19d1250 .scope generate, "genblk1[13]" "genblk1[13]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19d1410 .param/l "i" 0 3 165, +C4<01101>; +S_0x19d14d0 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19d1250; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a0e770 .functor XOR 1, L_0x1a0eb50, L_0x1a0e120, C4<0>, C4<0>; +L_0x1a0e870 .functor AND 1, L_0x1a0e390, v0x19d2b70_0, C4<1>, C4<1>; +L_0x1a0e8e0 .functor AND 1, L_0x1a0e770, v0x19d2cb0_0, C4<1>, C4<1>; +L_0x1a0e950 .functor AND 1, L_0x1a0eb50, v0x19d2ad0_0, C4<1>, C4<1>; +L_0x1a0e9c0 .functor OR 1, L_0x1a0e870, L_0x1a0e8e0, L_0x1a0e950, C4<0>; +v0x19d23c0_0 .net "a", 0 0, L_0x1a0eb50; 1 drivers +v0x19d2480_0 .net "addRes", 0 0, L_0x1a0e390; 1 drivers +v0x19d2550_0 .net "b", 0 0, L_0x1a0e120; 1 drivers +v0x19d2650_0 .net "carryIn", 0 0, L_0x1a0ed40; 1 drivers +v0x19d2720_0 .net "carryOut", 0 0, L_0x1a0e5d0; 1 drivers +v0x19d27c0_0 .net "finalA", 0 0, L_0x1a0e950; 1 drivers +v0x19d2860_0 .net "finalAdd", 0 0, L_0x1a0e870; 1 drivers +v0x19d2900_0 .net "finalXor", 0 0, L_0x1a0e8e0; 1 drivers +v0x19d29a0_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19d2ad0_0 .var "isA", 0 0; +v0x19d2b70_0 .var "isAdd", 0 0; +v0x19d2c10_0 .var "isSubtract", 0 0; +v0x19d2cb0_0 .var "isXor", 0 0; +v0x19d2d70_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19d2e30_0 .net "res", 0 0, L_0x1a0e9c0; 1 drivers +v0x19d2ef0_0 .net "xorRes", 0 0, L_0x1a0e770; 1 drivers +S_0x19d17c0 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19d14d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a0e260 .functor XOR 1, L_0x1a0e120, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a0e2d0 .functor XOR 1, L_0x1a0eb50, L_0x1a0e260, C4<0>, C4<0>; +L_0x1a0e390 .functor XOR 1, L_0x1a0e2d0, L_0x1a0ed40, C4<0>, C4<0>; +L_0x1a0e4f0 .functor AND 1, L_0x1a0eb50, L_0x1a0e260, C4<1>, C4<1>; +L_0x1a0e560 .functor AND 1, L_0x1a0e2d0, L_0x1a0ed40, C4<1>, C4<1>; +L_0x1a0e5d0 .functor OR 1, L_0x1a0e4f0, L_0x1a0e560, C4<0>, C4<0>; +v0x19d1a50_0 .net "AandB", 0 0, L_0x1a0e4f0; 1 drivers +v0x19d1b30_0 .net "BxorSub", 0 0, L_0x1a0e260; 1 drivers +v0x19d1bf0_0 .net "a", 0 0, L_0x1a0eb50; alias, 1 drivers +v0x19d1cc0_0 .net "b", 0 0, L_0x1a0e120; alias, 1 drivers +v0x19d1d80_0 .net "carryin", 0 0, L_0x1a0ed40; alias, 1 drivers +v0x19d1e90_0 .net "carryout", 0 0, L_0x1a0e5d0; alias, 1 drivers +v0x19d1f50_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19d1ff0_0 .net "res", 0 0, L_0x1a0e390; alias, 1 drivers +v0x19d20b0_0 .net "xAorB", 0 0, L_0x1a0e2d0; 1 drivers +v0x19d2200_0 .net "xAorBandCin", 0 0, L_0x1a0e560; 1 drivers +S_0x19d30b0 .scope generate, "genblk1[14]" "genblk1[14]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19d3270 .param/l "i" 0 3 165, +C4<01110>; +S_0x19d3330 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19d30b0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a0f3b0 .functor XOR 1, L_0x1a0f790, L_0x1a09640, C4<0>, C4<0>; +L_0x1a0f4b0 .functor AND 1, L_0x1a0efd0, v0x19d49d0_0, C4<1>, C4<1>; +L_0x1a0f520 .functor AND 1, L_0x1a0f3b0, v0x19d4b10_0, C4<1>, C4<1>; +L_0x1a0f590 .functor AND 1, L_0x1a0f790, v0x19d4930_0, C4<1>, C4<1>; +L_0x1a0f600 .functor OR 1, L_0x1a0f4b0, L_0x1a0f520, L_0x1a0f590, C4<0>; +v0x19d4220_0 .net "a", 0 0, L_0x1a0f790; 1 drivers +v0x19d42e0_0 .net "addRes", 0 0, L_0x1a0efd0; 1 drivers +v0x19d43b0_0 .net "b", 0 0, L_0x1a09640; 1 drivers +v0x19d44b0_0 .net "carryIn", 0 0, L_0x1a097f0; 1 drivers +v0x19d4580_0 .net "carryOut", 0 0, L_0x1a0f210; 1 drivers +v0x19d4620_0 .net "finalA", 0 0, L_0x1a0f590; 1 drivers +v0x19d46c0_0 .net "finalAdd", 0 0, L_0x1a0f4b0; 1 drivers +v0x19d4760_0 .net "finalXor", 0 0, L_0x1a0f520; 1 drivers +v0x19d4800_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19d4930_0 .var "isA", 0 0; +v0x19d49d0_0 .var "isAdd", 0 0; +v0x19d4a70_0 .var "isSubtract", 0 0; +v0x19d4b10_0 .var "isXor", 0 0; +v0x19d4bd0_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19d4c90_0 .net "res", 0 0, L_0x1a0f600; 1 drivers +v0x19d4d50_0 .net "xorRes", 0 0, L_0x1a0f3b0; 1 drivers +S_0x19d3620 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19d3330; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a0ebf0 .functor XOR 1, L_0x1a09640, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a0ec60 .functor XOR 1, L_0x1a0f790, L_0x1a0ebf0, C4<0>, C4<0>; +L_0x1a0efd0 .functor XOR 1, L_0x1a0ec60, L_0x1a097f0, C4<0>, C4<0>; +L_0x1a0f130 .functor AND 1, L_0x1a0f790, L_0x1a0ebf0, C4<1>, C4<1>; +L_0x1a0f1a0 .functor AND 1, L_0x1a0ec60, L_0x1a097f0, C4<1>, C4<1>; +L_0x1a0f210 .functor OR 1, L_0x1a0f130, L_0x1a0f1a0, C4<0>, C4<0>; +v0x19d38b0_0 .net "AandB", 0 0, L_0x1a0f130; 1 drivers +v0x19d3990_0 .net "BxorSub", 0 0, L_0x1a0ebf0; 1 drivers +v0x19d3a50_0 .net "a", 0 0, L_0x1a0f790; alias, 1 drivers +v0x19d3b20_0 .net "b", 0 0, L_0x1a09640; alias, 1 drivers +v0x19d3be0_0 .net "carryin", 0 0, L_0x1a097f0; alias, 1 drivers +v0x19d3cf0_0 .net "carryout", 0 0, L_0x1a0f210; alias, 1 drivers +v0x19d3db0_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19d3e50_0 .net "res", 0 0, L_0x1a0efd0; alias, 1 drivers +v0x19d3f10_0 .net "xAorB", 0 0, L_0x1a0ec60; 1 drivers +v0x19d4060_0 .net "xAorBandCin", 0 0, L_0x1a0f1a0; 1 drivers +S_0x19d4f10 .scope generate, "genblk1[15]" "genblk1[15]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19d50d0 .param/l "i" 0 3 165, +C4<01111>; +S_0x19d5190 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19d4f10; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a101c0 .functor XOR 1, L_0x1a105a0, L_0x1a0fce0, C4<0>, C4<0>; +L_0x1a102c0 .functor AND 1, L_0x1a0ef50, v0x19d6830_0, C4<1>, C4<1>; +L_0x1a10330 .functor AND 1, L_0x1a101c0, v0x19d6970_0, C4<1>, C4<1>; +L_0x1a103a0 .functor AND 1, L_0x1a105a0, v0x19d6790_0, C4<1>, C4<1>; +L_0x1a10410 .functor OR 1, L_0x1a102c0, L_0x1a10330, L_0x1a103a0, C4<0>; +v0x19d6080_0 .net "a", 0 0, L_0x1a105a0; 1 drivers +v0x19d6140_0 .net "addRes", 0 0, L_0x1a0ef50; 1 drivers +v0x19d6210_0 .net "b", 0 0, L_0x1a0fce0; 1 drivers +v0x19d6310_0 .net "carryIn", 0 0, L_0x1a107c0; 1 drivers +v0x19d63e0_0 .net "carryOut", 0 0, L_0x1a10020; 1 drivers +v0x19d6480_0 .net "finalA", 0 0, L_0x1a103a0; 1 drivers +v0x19d6520_0 .net "finalAdd", 0 0, L_0x1a102c0; 1 drivers +v0x19d65c0_0 .net "finalXor", 0 0, L_0x1a10330; 1 drivers +v0x19d6660_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19d6790_0 .var "isA", 0 0; +v0x19d6830_0 .var "isAdd", 0 0; +v0x19d68d0_0 .var "isSubtract", 0 0; +v0x19d6970_0 .var "isXor", 0 0; +v0x19d6a30_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19d6af0_0 .net "res", 0 0, L_0x1a10410; 1 drivers +v0x19d6bb0_0 .net "xorRes", 0 0, L_0x1a101c0; 1 drivers +S_0x19d5480 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19d5190; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a096e0 .functor XOR 1, L_0x1a0fce0, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a09890 .functor XOR 1, L_0x1a105a0, L_0x1a096e0, C4<0>, C4<0>; +L_0x1a0ef50 .functor XOR 1, L_0x1a09890, L_0x1a107c0, C4<0>, C4<0>; +L_0x1a0ff40 .functor AND 1, L_0x1a105a0, L_0x1a096e0, C4<1>, C4<1>; +L_0x1a0ffb0 .functor AND 1, L_0x1a09890, L_0x1a107c0, C4<1>, C4<1>; +L_0x1a10020 .functor OR 1, L_0x1a0ff40, L_0x1a0ffb0, C4<0>, C4<0>; +v0x19d5710_0 .net "AandB", 0 0, L_0x1a0ff40; 1 drivers +v0x19d57f0_0 .net "BxorSub", 0 0, L_0x1a096e0; 1 drivers +v0x19d58b0_0 .net "a", 0 0, L_0x1a105a0; alias, 1 drivers +v0x19d5980_0 .net "b", 0 0, L_0x1a0fce0; alias, 1 drivers +v0x19d5a40_0 .net "carryin", 0 0, L_0x1a107c0; alias, 1 drivers +v0x19d5b50_0 .net "carryout", 0 0, L_0x1a10020; alias, 1 drivers +v0x19d5c10_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19d5cb0_0 .net "res", 0 0, L_0x1a0ef50; alias, 1 drivers +v0x19d5d70_0 .net "xAorB", 0 0, L_0x1a09890; 1 drivers +v0x19d5ec0_0 .net "xAorBandCin", 0 0, L_0x1a0ffb0; 1 drivers +S_0x19d6d70 .scope generate, "genblk1[16]" "genblk1[16]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19c79c0 .param/l "i" 0 3 165, +C4<010000>; +S_0x19d7090 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19d6d70; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a10f20 .functor XOR 1, L_0x1a112d0, L_0x1a11370, C4<0>, C4<0>; +L_0x1a11020 .functor AND 1, L_0x1a10690, v0x19d8a90_0, C4<1>, C4<1>; +L_0x1a11090 .functor AND 1, L_0x1a10f20, v0x19d8bd0_0, C4<1>, C4<1>; +L_0x1a11100 .functor AND 1, L_0x1a112d0, v0x19c91d0_0, C4<1>, C4<1>; +L_0x1a11170 .functor OR 1, L_0x1a11020, L_0x1a11090, L_0x1a11100, C4<0>; +v0x19d8140_0 .net "a", 0 0, L_0x1a112d0; 1 drivers +v0x19d8230_0 .net "addRes", 0 0, L_0x1a10690; 1 drivers +v0x19d8300_0 .net "b", 0 0, L_0x1a11370; 1 drivers +v0x19d8400_0 .net "carryIn", 0 0, L_0x1a10b00; 1 drivers +v0x19d84d0_0 .net "carryOut", 0 0, L_0x1a10dc0; 1 drivers +v0x19d8570_0 .net "finalA", 0 0, L_0x1a11100; 1 drivers +v0x19d8610_0 .net "finalAdd", 0 0, L_0x1a11020; 1 drivers +v0x19d86b0_0 .net "finalXor", 0 0, L_0x1a11090; 1 drivers +v0x19d8750_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19c91d0_0 .var "isA", 0 0; +v0x19d8a90_0 .var "isAdd", 0 0; +v0x19d8b30_0 .var "isSubtract", 0 0; +v0x19d8bd0_0 .var "isXor", 0 0; +v0x19d8c70_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19c9600_0 .net "res", 0 0, L_0x1a11170; 1 drivers +v0x19d8f20_0 .net "xorRes", 0 0, L_0x1a10f20; 1 drivers +S_0x19d7380 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19d7090; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a0a5c0 .functor XOR 1, L_0x1a11370, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a0a630 .functor XOR 1, L_0x1a112d0, L_0x1a0a5c0, C4<0>, C4<0>; +L_0x1a10690 .functor XOR 1, L_0x1a0a630, L_0x1a10b00, C4<0>, C4<0>; +L_0x1a10ce0 .functor AND 1, L_0x1a112d0, L_0x1a0a5c0, C4<1>, C4<1>; +L_0x1a10d50 .functor AND 1, L_0x1a0a630, L_0x1a10b00, C4<1>, C4<1>; +L_0x1a10dc0 .functor OR 1, L_0x1a10ce0, L_0x1a10d50, C4<0>, C4<0>; +v0x19d75f0_0 .net "AandB", 0 0, L_0x1a10ce0; 1 drivers +v0x19d76d0_0 .net "BxorSub", 0 0, L_0x1a0a5c0; 1 drivers +v0x19d7790_0 .net "a", 0 0, L_0x1a112d0; alias, 1 drivers +v0x19d7860_0 .net "b", 0 0, L_0x1a11370; alias, 1 drivers +v0x19d7920_0 .net "carryin", 0 0, L_0x1a10b00; alias, 1 drivers +v0x19d7a30_0 .net "carryout", 0 0, L_0x1a10dc0; alias, 1 drivers +v0x19d7af0_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19c85e0_0 .net "res", 0 0, L_0x1a10690; alias, 1 drivers +v0x19c86a0_0 .net "xAorB", 0 0, L_0x1a0a630; 1 drivers +v0x19d7fa0_0 .net "xAorBandCin", 0 0, L_0x1a10d50; 1 drivers +S_0x19d9080 .scope generate, "genblk1[17]" "genblk1[17]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19d9240 .param/l "i" 0 3 165, +C4<010001>; +S_0x19d9300 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19d9080; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a11b00 .functor XOR 1, L_0x1a11eb0, L_0x1a114a0, C4<0>, C4<0>; +L_0x1a11c00 .functor AND 1, L_0x1a11720, v0x19da9a0_0, C4<1>, C4<1>; +L_0x1a11c70 .functor AND 1, L_0x1a11b00, v0x19daae0_0, C4<1>, C4<1>; +L_0x1a11ce0 .functor AND 1, L_0x1a11eb0, v0x19da900_0, C4<1>, C4<1>; +L_0x1a11d50 .functor OR 1, L_0x1a11c00, L_0x1a11c70, L_0x1a11ce0, C4<0>; +v0x19da1f0_0 .net "a", 0 0, L_0x1a11eb0; 1 drivers +v0x19da2b0_0 .net "addRes", 0 0, L_0x1a11720; 1 drivers +v0x19da380_0 .net "b", 0 0, L_0x1a114a0; 1 drivers +v0x19da480_0 .net "carryIn", 0 0, L_0x1a12100; 1 drivers +v0x19da550_0 .net "carryOut", 0 0, L_0x1a11960; 1 drivers +v0x19da5f0_0 .net "finalA", 0 0, L_0x1a11ce0; 1 drivers +v0x19da690_0 .net "finalAdd", 0 0, L_0x1a11c00; 1 drivers +v0x19da730_0 .net "finalXor", 0 0, L_0x1a11c70; 1 drivers +v0x19da7d0_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19da900_0 .var "isA", 0 0; +v0x19da9a0_0 .var "isAdd", 0 0; +v0x19daa40_0 .var "isSubtract", 0 0; +v0x19daae0_0 .var "isXor", 0 0; +v0x19daba0_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19dac60_0 .net "res", 0 0, L_0x1a11d50; 1 drivers +v0x19dad20_0 .net "xorRes", 0 0, L_0x1a11b00; 1 drivers +S_0x19d95f0 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19d9300; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a11640 .functor XOR 1, L_0x1a114a0, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a116b0 .functor XOR 1, L_0x1a11eb0, L_0x1a11640, C4<0>, C4<0>; +L_0x1a11720 .functor XOR 1, L_0x1a116b0, L_0x1a12100, C4<0>, C4<0>; +L_0x1a11880 .functor AND 1, L_0x1a11eb0, L_0x1a11640, C4<1>, C4<1>; +L_0x1a118f0 .functor AND 1, L_0x1a116b0, L_0x1a12100, C4<1>, C4<1>; +L_0x1a11960 .functor OR 1, L_0x1a11880, L_0x1a118f0, C4<0>, C4<0>; +v0x19d9880_0 .net "AandB", 0 0, L_0x1a11880; 1 drivers +v0x19d9960_0 .net "BxorSub", 0 0, L_0x1a11640; 1 drivers +v0x19d9a20_0 .net "a", 0 0, L_0x1a11eb0; alias, 1 drivers +v0x19d9af0_0 .net "b", 0 0, L_0x1a114a0; alias, 1 drivers +v0x19d9bb0_0 .net "carryin", 0 0, L_0x1a12100; alias, 1 drivers +v0x19d9cc0_0 .net "carryout", 0 0, L_0x1a11960; alias, 1 drivers +v0x19d9d80_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19d9e20_0 .net "res", 0 0, L_0x1a11720; alias, 1 drivers +v0x19d9ee0_0 .net "xAorB", 0 0, L_0x1a116b0; 1 drivers +v0x19da030_0 .net "xAorBandCin", 0 0, L_0x1a118f0; 1 drivers +S_0x19daee0 .scope generate, "genblk1[18]" "genblk1[18]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19db0a0 .param/l "i" 0 3 165, +C4<010010>; +S_0x19db160 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19daee0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a12710 .functor XOR 1, L_0x1a12ac0, L_0x1a12b60, C4<0>, C4<0>; +L_0x1a12810 .functor AND 1, L_0x1a12010, v0x19dc800_0, C4<1>, C4<1>; +L_0x1a12880 .functor AND 1, L_0x1a12710, v0x19dc940_0, C4<1>, C4<1>; +L_0x1a128f0 .functor AND 1, L_0x1a12ac0, v0x19dc760_0, C4<1>, C4<1>; +L_0x1a12960 .functor OR 1, L_0x1a12810, L_0x1a12880, L_0x1a128f0, C4<0>; +v0x19dc050_0 .net "a", 0 0, L_0x1a12ac0; 1 drivers +v0x19dc110_0 .net "addRes", 0 0, L_0x1a12010; 1 drivers +v0x19dc1e0_0 .net "b", 0 0, L_0x1a12b60; 1 drivers +v0x19dc2e0_0 .net "carryIn", 0 0, L_0x1a12230; 1 drivers +v0x19dc3b0_0 .net "carryOut", 0 0, L_0x1a12570; 1 drivers +v0x19dc450_0 .net "finalA", 0 0, L_0x1a128f0; 1 drivers +v0x19dc4f0_0 .net "finalAdd", 0 0, L_0x1a12810; 1 drivers +v0x19dc590_0 .net "finalXor", 0 0, L_0x1a12880; 1 drivers +v0x19dc630_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19dc760_0 .var "isA", 0 0; +v0x19dc800_0 .var "isAdd", 0 0; +v0x19dc8a0_0 .var "isSubtract", 0 0; +v0x19dc940_0 .var "isXor", 0 0; +v0x19dca00_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19dcac0_0 .net "res", 0 0, L_0x1a12960; 1 drivers +v0x19dcb80_0 .net "xorRes", 0 0, L_0x1a12710; 1 drivers +S_0x19db450 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19db160; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a115d0 .functor XOR 1, L_0x1a12b60, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a11f50 .functor XOR 1, L_0x1a12ac0, L_0x1a115d0, C4<0>, C4<0>; +L_0x1a12010 .functor XOR 1, L_0x1a11f50, L_0x1a12230, C4<0>, C4<0>; +L_0x1a12490 .functor AND 1, L_0x1a12ac0, L_0x1a115d0, C4<1>, C4<1>; +L_0x1a12500 .functor AND 1, L_0x1a11f50, L_0x1a12230, C4<1>, C4<1>; +L_0x1a12570 .functor OR 1, L_0x1a12490, L_0x1a12500, C4<0>, C4<0>; +v0x19db6e0_0 .net "AandB", 0 0, L_0x1a12490; 1 drivers +v0x19db7c0_0 .net "BxorSub", 0 0, L_0x1a115d0; 1 drivers +v0x19db880_0 .net "a", 0 0, L_0x1a12ac0; alias, 1 drivers +v0x19db950_0 .net "b", 0 0, L_0x1a12b60; alias, 1 drivers +v0x19dba10_0 .net "carryin", 0 0, L_0x1a12230; alias, 1 drivers +v0x19dbb20_0 .net "carryout", 0 0, L_0x1a12570; alias, 1 drivers +v0x19dbbe0_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19dbc80_0 .net "res", 0 0, L_0x1a12010; alias, 1 drivers +v0x19dbd40_0 .net "xAorB", 0 0, L_0x1a11f50; 1 drivers +v0x19dbe90_0 .net "xAorBandCin", 0 0, L_0x1a12500; 1 drivers +S_0x19dcd40 .scope generate, "genblk1[19]" "genblk1[19]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19dcf00 .param/l "i" 0 3 165, +C4<010011>; +S_0x19dcfc0 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19dcd40; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a132c0 .functor XOR 1, L_0x1a136a0, L_0x1a12c90, C4<0>, C4<0>; +L_0x1a133c0 .functor AND 1, L_0x1a12f20, v0x19de650_0, C4<1>, C4<1>; +L_0x1a13430 .functor AND 1, L_0x1a132c0, v0x19de790_0, C4<1>, C4<1>; +L_0x1a134a0 .functor AND 1, L_0x1a136a0, v0x19de5b0_0, C4<1>, C4<1>; +L_0x1a13510 .functor OR 1, L_0x1a133c0, L_0x1a13430, L_0x1a134a0, C4<0>; +v0x19ddeb0_0 .net "a", 0 0, L_0x1a136a0; 1 drivers +v0x19ddf70_0 .net "addRes", 0 0, L_0x1a12f20; 1 drivers +v0x19de010_0 .net "b", 0 0, L_0x1a12c90; 1 drivers +v0x19de0e0_0 .net "carryIn", 0 0, L_0x1a12dc0; 1 drivers +v0x19de1b0_0 .net "carryOut", 0 0, L_0x1a13160; 1 drivers +v0x19de2a0_0 .net "finalA", 0 0, L_0x1a134a0; 1 drivers +v0x19de340_0 .net "finalAdd", 0 0, L_0x1a133c0; 1 drivers +v0x19de3e0_0 .net "finalXor", 0 0, L_0x1a13430; 1 drivers +v0x19de480_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19de5b0_0 .var "isA", 0 0; +v0x19de650_0 .var "isAdd", 0 0; +v0x19de6f0_0 .var "isSubtract", 0 0; +v0x19de790_0 .var "isXor", 0 0; +v0x19de830_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19de8f0_0 .net "res", 0 0, L_0x1a13510; 1 drivers +v0x19de9b0_0 .net "xorRes", 0 0, L_0x1a132c0; 1 drivers +S_0x19dd2b0 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19dcfc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a12360 .functor XOR 1, L_0x1a12c90, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a12e60 .functor XOR 1, L_0x1a136a0, L_0x1a12360, C4<0>, C4<0>; +L_0x1a12f20 .functor XOR 1, L_0x1a12e60, L_0x1a12dc0, C4<0>, C4<0>; +L_0x1a13080 .functor AND 1, L_0x1a136a0, L_0x1a12360, C4<1>, C4<1>; +L_0x1a130f0 .functor AND 1, L_0x1a12e60, L_0x1a12dc0, C4<1>, C4<1>; +L_0x1a13160 .functor OR 1, L_0x1a13080, L_0x1a130f0, C4<0>, C4<0>; +v0x19dd540_0 .net "AandB", 0 0, L_0x1a13080; 1 drivers +v0x19dd620_0 .net "BxorSub", 0 0, L_0x1a12360; 1 drivers +v0x19dd6e0_0 .net "a", 0 0, L_0x1a136a0; alias, 1 drivers +v0x19dd7b0_0 .net "b", 0 0, L_0x1a12c90; alias, 1 drivers +v0x19dd870_0 .net "carryin", 0 0, L_0x1a12dc0; alias, 1 drivers +v0x19dd980_0 .net "carryout", 0 0, L_0x1a13160; alias, 1 drivers +v0x19dda40_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19ddae0_0 .net "res", 0 0, L_0x1a12f20; alias, 1 drivers +v0x19ddba0_0 .net "xAorB", 0 0, L_0x1a12e60; 1 drivers +v0x19ddcf0_0 .net "xAorBandCin", 0 0, L_0x1a130f0; 1 drivers +S_0x19deb70 .scope generate, "genblk1[20]" "genblk1[20]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19ded30 .param/l "i" 0 3 165, +C4<010100>; +S_0x19dedf0 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19deb70; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a13ed0 .functor XOR 1, L_0x1a142b0, L_0x1a14350, C4<0>, C4<0>; +L_0x1a13fd0 .functor AND 1, L_0x1a13870, v0x19e04d0_0, C4<1>, C4<1>; +L_0x1a14040 .functor AND 1, L_0x1a13ed0, v0x19e0610_0, C4<1>, C4<1>; +L_0x1a140b0 .functor AND 1, L_0x1a142b0, v0x19e0430_0, C4<1>, C4<1>; +L_0x1a14120 .functor OR 1, L_0x1a13fd0, L_0x1a14040, L_0x1a140b0, C4<0>; +v0x19dfd20_0 .net "a", 0 0, L_0x1a142b0; 1 drivers +v0x19dfde0_0 .net "addRes", 0 0, L_0x1a13870; 1 drivers +v0x19dfeb0_0 .net "b", 0 0, L_0x1a14350; 1 drivers +v0x19dffb0_0 .net "carryIn", 0 0, L_0x1a139b0; 1 drivers +v0x19e0080_0 .net "carryOut", 0 0, L_0x1a13d70; 1 drivers +v0x19e0120_0 .net "finalA", 0 0, L_0x1a140b0; 1 drivers +v0x19e01c0_0 .net "finalAdd", 0 0, L_0x1a13fd0; 1 drivers +v0x19e0260_0 .net "finalXor", 0 0, L_0x1a14040; 1 drivers +v0x19e0300_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19e0430_0 .var "isA", 0 0; +v0x19e04d0_0 .var "isAdd", 0 0; +v0x19e0570_0 .var "isSubtract", 0 0; +v0x19e0610_0 .var "isXor", 0 0; +v0x19e06d0_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19e0790_0 .net "res", 0 0, L_0x1a14120; 1 drivers +v0x19e0850_0 .net "xorRes", 0 0, L_0x1a13ed0; 1 drivers +S_0x19df0e0 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19dedf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a13740 .functor XOR 1, L_0x1a14350, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a137b0 .functor XOR 1, L_0x1a142b0, L_0x1a13740, C4<0>, C4<0>; +L_0x1a13870 .functor XOR 1, L_0x1a137b0, L_0x1a139b0, C4<0>, C4<0>; +L_0x1a13c90 .functor AND 1, L_0x1a142b0, L_0x1a13740, C4<1>, C4<1>; +L_0x1a13d00 .functor AND 1, L_0x1a137b0, L_0x1a139b0, C4<1>, C4<1>; +L_0x1a13d70 .functor OR 1, L_0x1a13c90, L_0x1a13d00, C4<0>, C4<0>; +v0x19df3b0_0 .net "AandB", 0 0, L_0x1a13c90; 1 drivers +v0x19df490_0 .net "BxorSub", 0 0, L_0x1a13740; 1 drivers +v0x19df550_0 .net "a", 0 0, L_0x1a142b0; alias, 1 drivers +v0x19df620_0 .net "b", 0 0, L_0x1a14350; alias, 1 drivers +v0x19df6e0_0 .net "carryin", 0 0, L_0x1a139b0; alias, 1 drivers +v0x19df7f0_0 .net "carryout", 0 0, L_0x1a13d70; alias, 1 drivers +v0x19df8b0_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19df950_0 .net "res", 0 0, L_0x1a13870; alias, 1 drivers +v0x19dfa10_0 .net "xAorB", 0 0, L_0x1a137b0; 1 drivers +v0x19dfb60_0 .net "xAorBandCin", 0 0, L_0x1a13d00; 1 drivers +S_0x19e0a10 .scope generate, "genblk1[21]" "genblk1[21]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19e0bd0 .param/l "i" 0 3 165, +C4<010101>; +S_0x19e0c90 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19e0a10; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a14ad0 .functor XOR 1, L_0x1a14eb0, L_0x1a14480, C4<0>, C4<0>; +L_0x1a14bd0 .functor AND 1, L_0x1a146f0, v0x19e2330_0, C4<1>, C4<1>; +L_0x1a14c40 .functor AND 1, L_0x1a14ad0, v0x19e2470_0, C4<1>, C4<1>; +L_0x1a14cb0 .functor AND 1, L_0x1a14eb0, v0x19e2290_0, C4<1>, C4<1>; +L_0x1a14d20 .functor OR 1, L_0x1a14bd0, L_0x1a14c40, L_0x1a14cb0, C4<0>; +v0x19e1b80_0 .net "a", 0 0, L_0x1a14eb0; 1 drivers +v0x19e1c40_0 .net "addRes", 0 0, L_0x1a146f0; 1 drivers +v0x19e1d10_0 .net "b", 0 0, L_0x1a14480; 1 drivers +v0x19e1e10_0 .net "carryIn", 0 0, L_0x1a145b0; 1 drivers +v0x19e1ee0_0 .net "carryOut", 0 0, L_0x1a14930; 1 drivers +v0x19e1f80_0 .net "finalA", 0 0, L_0x1a14cb0; 1 drivers +v0x19e2020_0 .net "finalAdd", 0 0, L_0x1a14bd0; 1 drivers +v0x19e20c0_0 .net "finalXor", 0 0, L_0x1a14c40; 1 drivers +v0x19e2160_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19e2290_0 .var "isA", 0 0; +v0x19e2330_0 .var "isAdd", 0 0; +v0x19e23d0_0 .var "isSubtract", 0 0; +v0x19e2470_0 .var "isXor", 0 0; +v0x19e2530_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19e25f0_0 .net "res", 0 0, L_0x1a14d20; 1 drivers +v0x19e26b0_0 .net "xorRes", 0 0, L_0x1a14ad0; 1 drivers +S_0x19e0f80 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19e0c90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a13ae0 .functor XOR 1, L_0x1a14480, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a14680 .functor XOR 1, L_0x1a14eb0, L_0x1a13ae0, C4<0>, C4<0>; +L_0x1a146f0 .functor XOR 1, L_0x1a14680, L_0x1a145b0, C4<0>, C4<0>; +L_0x1a14850 .functor AND 1, L_0x1a14eb0, L_0x1a13ae0, C4<1>, C4<1>; +L_0x1a148c0 .functor AND 1, L_0x1a14680, L_0x1a145b0, C4<1>, C4<1>; +L_0x1a14930 .functor OR 1, L_0x1a14850, L_0x1a148c0, C4<0>, C4<0>; +v0x19e1210_0 .net "AandB", 0 0, L_0x1a14850; 1 drivers +v0x19e12f0_0 .net "BxorSub", 0 0, L_0x1a13ae0; 1 drivers +v0x19e13b0_0 .net "a", 0 0, L_0x1a14eb0; alias, 1 drivers +v0x19e1480_0 .net "b", 0 0, L_0x1a14480; alias, 1 drivers +v0x19e1540_0 .net "carryin", 0 0, L_0x1a145b0; alias, 1 drivers +v0x19e1650_0 .net "carryout", 0 0, L_0x1a14930; alias, 1 drivers +v0x19e1710_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19e17b0_0 .net "res", 0 0, L_0x1a146f0; alias, 1 drivers +v0x19e1870_0 .net "xAorB", 0 0, L_0x1a14680; 1 drivers +v0x19e19c0_0 .net "xAorBandCin", 0 0, L_0x1a148c0; 1 drivers +S_0x19e2870 .scope generate, "genblk1[22]" "genblk1[22]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19e2a30 .param/l "i" 0 3 165, +C4<010110>; +S_0x19e2af0 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19e2870; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a15730 .functor XOR 1, L_0x1a15ae0, L_0x1a15b80, C4<0>, C4<0>; +L_0x1a15830 .functor AND 1, L_0x1a15080, v0x19e4190_0, C4<1>, C4<1>; +L_0x1a158a0 .functor AND 1, L_0x1a15730, v0x19e42d0_0, C4<1>, C4<1>; +L_0x1a15910 .functor AND 1, L_0x1a15ae0, v0x19e40f0_0, C4<1>, C4<1>; +L_0x1a15980 .functor OR 1, L_0x1a15830, L_0x1a158a0, L_0x1a15910, C4<0>; +v0x19e39e0_0 .net "a", 0 0, L_0x1a15ae0; 1 drivers +v0x19e3aa0_0 .net "addRes", 0 0, L_0x1a15080; 1 drivers +v0x19e3b70_0 .net "b", 0 0, L_0x1a15b80; 1 drivers +v0x19e3c70_0 .net "carryIn", 0 0, L_0x1a151f0; 1 drivers +v0x19e3d40_0 .net "carryOut", 0 0, L_0x1a15590; 1 drivers +v0x19e3de0_0 .net "finalA", 0 0, L_0x1a15910; 1 drivers +v0x19e3e80_0 .net "finalAdd", 0 0, L_0x1a15830; 1 drivers +v0x19e3f20_0 .net "finalXor", 0 0, L_0x1a158a0; 1 drivers +v0x19e3fc0_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19e40f0_0 .var "isA", 0 0; +v0x19e4190_0 .var "isAdd", 0 0; +v0x19e4230_0 .var "isSubtract", 0 0; +v0x19e42d0_0 .var "isXor", 0 0; +v0x19e4390_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19e4450_0 .net "res", 0 0, L_0x1a15980; 1 drivers +v0x19e4510_0 .net "xorRes", 0 0, L_0x1a15730; 1 drivers +S_0x19e2de0 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19e2af0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a14f50 .functor XOR 1, L_0x1a15b80, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a14fc0 .functor XOR 1, L_0x1a15ae0, L_0x1a14f50, C4<0>, C4<0>; +L_0x1a15080 .functor XOR 1, L_0x1a14fc0, L_0x1a151f0, C4<0>, C4<0>; +L_0x1a154b0 .functor AND 1, L_0x1a15ae0, L_0x1a14f50, C4<1>, C4<1>; +L_0x1a15520 .functor AND 1, L_0x1a14fc0, L_0x1a151f0, C4<1>, C4<1>; +L_0x1a15590 .functor OR 1, L_0x1a154b0, L_0x1a15520, C4<0>, C4<0>; +v0x19e3070_0 .net "AandB", 0 0, L_0x1a154b0; 1 drivers +v0x19e3150_0 .net "BxorSub", 0 0, L_0x1a14f50; 1 drivers +v0x19e3210_0 .net "a", 0 0, L_0x1a15ae0; alias, 1 drivers +v0x19e32e0_0 .net "b", 0 0, L_0x1a15b80; alias, 1 drivers +v0x19e33a0_0 .net "carryin", 0 0, L_0x1a151f0; alias, 1 drivers +v0x19e34b0_0 .net "carryout", 0 0, L_0x1a15590; alias, 1 drivers +v0x19e3570_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19e3610_0 .net "res", 0 0, L_0x1a15080; alias, 1 drivers +v0x19e36d0_0 .net "xAorB", 0 0, L_0x1a14fc0; 1 drivers +v0x19e3820_0 .net "xAorBandCin", 0 0, L_0x1a15520; 1 drivers +S_0x19e46d0 .scope generate, "genblk1[23]" "genblk1[23]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19e4890 .param/l "i" 0 3 165, +C4<010111>; +S_0x19e4950 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19e46d0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a16310 .functor XOR 1, L_0x1a166f0, L_0x1a15cb0, C4<0>, C4<0>; +L_0x1a16410 .functor AND 1, L_0x1a15f30, v0x19e5ff0_0, C4<1>, C4<1>; +L_0x1a16480 .functor AND 1, L_0x1a16310, v0x19e6130_0, C4<1>, C4<1>; +L_0x1a164f0 .functor AND 1, L_0x1a166f0, v0x19e5f50_0, C4<1>, C4<1>; +L_0x1a16560 .functor OR 1, L_0x1a16410, L_0x1a16480, L_0x1a164f0, C4<0>; +v0x19e5840_0 .net "a", 0 0, L_0x1a166f0; 1 drivers +v0x19e5900_0 .net "addRes", 0 0, L_0x1a15f30; 1 drivers +v0x19e59d0_0 .net "b", 0 0, L_0x1a15cb0; 1 drivers +v0x19e5ad0_0 .net "carryIn", 0 0, L_0x1a15de0; 1 drivers +v0x19e5ba0_0 .net "carryOut", 0 0, L_0x1a16170; 1 drivers +v0x19e5c40_0 .net "finalA", 0 0, L_0x1a164f0; 1 drivers +v0x19e5ce0_0 .net "finalAdd", 0 0, L_0x1a16410; 1 drivers +v0x19e5d80_0 .net "finalXor", 0 0, L_0x1a16480; 1 drivers +v0x19e5e20_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19e5f50_0 .var "isA", 0 0; +v0x19e5ff0_0 .var "isAdd", 0 0; +v0x19e6090_0 .var "isSubtract", 0 0; +v0x19e6130_0 .var "isXor", 0 0; +v0x19e61f0_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19e62b0_0 .net "res", 0 0, L_0x1a16560; 1 drivers +v0x19e6370_0 .net "xorRes", 0 0, L_0x1a16310; 1 drivers +S_0x19e4c40 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19e4950; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a15320 .functor XOR 1, L_0x1a15cb0, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a15390 .functor XOR 1, L_0x1a166f0, L_0x1a15320, C4<0>, C4<0>; +L_0x1a15f30 .functor XOR 1, L_0x1a15390, L_0x1a15de0, C4<0>, C4<0>; +L_0x1a16090 .functor AND 1, L_0x1a166f0, L_0x1a15320, C4<1>, C4<1>; +L_0x1a16100 .functor AND 1, L_0x1a15390, L_0x1a15de0, C4<1>, C4<1>; +L_0x1a16170 .functor OR 1, L_0x1a16090, L_0x1a16100, C4<0>, C4<0>; +v0x19e4ed0_0 .net "AandB", 0 0, L_0x1a16090; 1 drivers +v0x19e4fb0_0 .net "BxorSub", 0 0, L_0x1a15320; 1 drivers +v0x19e5070_0 .net "a", 0 0, L_0x1a166f0; alias, 1 drivers +v0x19e5140_0 .net "b", 0 0, L_0x1a15cb0; alias, 1 drivers +v0x19e5200_0 .net "carryin", 0 0, L_0x1a15de0; alias, 1 drivers +v0x19e5310_0 .net "carryout", 0 0, L_0x1a16170; alias, 1 drivers +v0x19e53d0_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19e5470_0 .net "res", 0 0, L_0x1a15f30; alias, 1 drivers +v0x19e5530_0 .net "xAorB", 0 0, L_0x1a15390; 1 drivers +v0x19e5680_0 .net "xAorBandCin", 0 0, L_0x1a16100; 1 drivers +S_0x19e6530 .scope generate, "genblk1[24]" "genblk1[24]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19e66f0 .param/l "i" 0 3 165, +C4<011000>; +S_0x19e67b0 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19e6530; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a16f30 .functor XOR 1, L_0x1a17310, L_0x1a173b0, C4<0>, C4<0>; +L_0x1a17030 .functor AND 1, L_0x1a168c0, v0x19e7e50_0, C4<1>, C4<1>; +L_0x1a170a0 .functor AND 1, L_0x1a16f30, v0x19e7f90_0, C4<1>, C4<1>; +L_0x1a17110 .functor AND 1, L_0x1a17310, v0x19e7db0_0, C4<1>, C4<1>; +L_0x1a17180 .functor OR 1, L_0x1a17030, L_0x1a170a0, L_0x1a17110, C4<0>; +v0x19e76a0_0 .net "a", 0 0, L_0x1a17310; 1 drivers +v0x19e7760_0 .net "addRes", 0 0, L_0x1a168c0; 1 drivers +v0x19e7830_0 .net "b", 0 0, L_0x1a173b0; 1 drivers +v0x19e7930_0 .net "carryIn", 0 0, L_0x1a16a60; 1 drivers +v0x19e7a00_0 .net "carryOut", 0 0, L_0x1a16d90; 1 drivers +v0x19e7aa0_0 .net "finalA", 0 0, L_0x1a17110; 1 drivers +v0x19e7b40_0 .net "finalAdd", 0 0, L_0x1a17030; 1 drivers +v0x19e7be0_0 .net "finalXor", 0 0, L_0x1a170a0; 1 drivers +v0x19e7c80_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19e7db0_0 .var "isA", 0 0; +v0x19e7e50_0 .var "isAdd", 0 0; +v0x19e7ef0_0 .var "isSubtract", 0 0; +v0x19e7f90_0 .var "isXor", 0 0; +v0x19e8050_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19e8110_0 .net "res", 0 0, L_0x1a17180; 1 drivers +v0x19e81d0_0 .net "xorRes", 0 0, L_0x1a16f30; 1 drivers +S_0x19e6aa0 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19e67b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a16790 .functor XOR 1, L_0x1a173b0, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a16800 .functor XOR 1, L_0x1a17310, L_0x1a16790, C4<0>, C4<0>; +L_0x1a168c0 .functor XOR 1, L_0x1a16800, L_0x1a16a60, C4<0>, C4<0>; +L_0x1a16cb0 .functor AND 1, L_0x1a17310, L_0x1a16790, C4<1>, C4<1>; +L_0x1a16d20 .functor AND 1, L_0x1a16800, L_0x1a16a60, C4<1>, C4<1>; +L_0x1a16d90 .functor OR 1, L_0x1a16cb0, L_0x1a16d20, C4<0>, C4<0>; +v0x19e6d30_0 .net "AandB", 0 0, L_0x1a16cb0; 1 drivers +v0x19e6e10_0 .net "BxorSub", 0 0, L_0x1a16790; 1 drivers +v0x19e6ed0_0 .net "a", 0 0, L_0x1a17310; alias, 1 drivers +v0x19e6fa0_0 .net "b", 0 0, L_0x1a173b0; alias, 1 drivers +v0x19e7060_0 .net "carryin", 0 0, L_0x1a16a60; alias, 1 drivers +v0x19e7170_0 .net "carryout", 0 0, L_0x1a16d90; alias, 1 drivers +v0x19e7230_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19e72d0_0 .net "res", 0 0, L_0x1a168c0; alias, 1 drivers +v0x19e7390_0 .net "xAorB", 0 0, L_0x1a16800; 1 drivers +v0x19e74e0_0 .net "xAorBandCin", 0 0, L_0x1a16d20; 1 drivers +S_0x19e8390 .scope generate, "genblk1[25]" "genblk1[25]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19e8550 .param/l "i" 0 3 165, +C4<011001>; +S_0x19e8610 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19e8390; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a17b80 .functor XOR 1, L_0x1a17f60, L_0x1a174e0, C4<0>, C4<0>; +L_0x1a17c80 .functor AND 1, L_0x1a177e0, v0x19e9cb0_0, C4<1>, C4<1>; +L_0x1a17cf0 .functor AND 1, L_0x1a17b80, v0x19e9df0_0, C4<1>, C4<1>; +L_0x1a17d60 .functor AND 1, L_0x1a17f60, v0x19e9c10_0, C4<1>, C4<1>; +L_0x1a17dd0 .functor OR 1, L_0x1a17c80, L_0x1a17cf0, L_0x1a17d60, C4<0>; +v0x19e9500_0 .net "a", 0 0, L_0x1a17f60; 1 drivers +v0x19e95c0_0 .net "addRes", 0 0, L_0x1a177e0; 1 drivers +v0x19e9690_0 .net "b", 0 0, L_0x1a174e0; 1 drivers +v0x19e9790_0 .net "carryIn", 0 0, L_0x1a17610; 1 drivers +v0x19e9860_0 .net "carryOut", 0 0, L_0x1a17a20; 1 drivers +v0x19e9900_0 .net "finalA", 0 0, L_0x1a17d60; 1 drivers +v0x19e99a0_0 .net "finalAdd", 0 0, L_0x1a17c80; 1 drivers +v0x19e9a40_0 .net "finalXor", 0 0, L_0x1a17cf0; 1 drivers +v0x19e9ae0_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19e9c10_0 .var "isA", 0 0; +v0x19e9cb0_0 .var "isAdd", 0 0; +v0x19e9d50_0 .var "isSubtract", 0 0; +v0x19e9df0_0 .var "isXor", 0 0; +v0x19e9eb0_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19e9f70_0 .net "res", 0 0, L_0x1a17dd0; 1 drivers +v0x19ea030_0 .net "xorRes", 0 0, L_0x1a17b80; 1 drivers +S_0x19e8900 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19e8610; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a16b90 .functor XOR 1, L_0x1a174e0, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a16c00 .functor XOR 1, L_0x1a17f60, L_0x1a16b90, C4<0>, C4<0>; +L_0x1a177e0 .functor XOR 1, L_0x1a16c00, L_0x1a17610, C4<0>, C4<0>; +L_0x1a17940 .functor AND 1, L_0x1a17f60, L_0x1a16b90, C4<1>, C4<1>; +L_0x1a179b0 .functor AND 1, L_0x1a16c00, L_0x1a17610, C4<1>, C4<1>; +L_0x1a17a20 .functor OR 1, L_0x1a17940, L_0x1a179b0, C4<0>, C4<0>; +v0x19e8b90_0 .net "AandB", 0 0, L_0x1a17940; 1 drivers +v0x19e8c70_0 .net "BxorSub", 0 0, L_0x1a16b90; 1 drivers +v0x19e8d30_0 .net "a", 0 0, L_0x1a17f60; alias, 1 drivers +v0x19e8e00_0 .net "b", 0 0, L_0x1a174e0; alias, 1 drivers +v0x19e8ec0_0 .net "carryin", 0 0, L_0x1a17610; alias, 1 drivers +v0x19e8fd0_0 .net "carryout", 0 0, L_0x1a17a20; alias, 1 drivers +v0x19e9090_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19e9130_0 .net "res", 0 0, L_0x1a177e0; alias, 1 drivers +v0x19e91f0_0 .net "xAorB", 0 0, L_0x1a16c00; 1 drivers +v0x19e9340_0 .net "xAorBandCin", 0 0, L_0x1a179b0; 1 drivers +S_0x19ea1f0 .scope generate, "genblk1[26]" "genblk1[26]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19ea3b0 .param/l "i" 0 3 165, +C4<011010>; +S_0x19ea470 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19ea1f0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a18790 .functor XOR 1, L_0x1a18b70, L_0x1a18c10, C4<0>, C4<0>; +L_0x1a18890 .functor AND 1, L_0x1a183b0, v0x19ebb10_0, C4<1>, C4<1>; +L_0x1a18900 .functor AND 1, L_0x1a18790, v0x19ebc50_0, C4<1>, C4<1>; +L_0x1a18970 .functor AND 1, L_0x1a18b70, v0x19eba70_0, C4<1>, C4<1>; +L_0x1a189e0 .functor OR 1, L_0x1a18890, L_0x1a18900, L_0x1a18970, C4<0>; +v0x19eb360_0 .net "a", 0 0, L_0x1a18b70; 1 drivers +v0x19eb420_0 .net "addRes", 0 0, L_0x1a183b0; 1 drivers +v0x19eb4f0_0 .net "b", 0 0, L_0x1a18c10; 1 drivers +v0x19eb5f0_0 .net "carryIn", 0 0, L_0x1a18000; 1 drivers +v0x19eb6c0_0 .net "carryOut", 0 0, L_0x1a185f0; 1 drivers +v0x19eb760_0 .net "finalA", 0 0, L_0x1a18970; 1 drivers +v0x19eb800_0 .net "finalAdd", 0 0, L_0x1a18890; 1 drivers +v0x19eb8a0_0 .net "finalXor", 0 0, L_0x1a18900; 1 drivers +v0x19eb940_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19eba70_0 .var "isA", 0 0; +v0x19ebb10_0 .var "isAdd", 0 0; +v0x19ebbb0_0 .var "isSubtract", 0 0; +v0x19ebc50_0 .var "isXor", 0 0; +v0x19ebd10_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19ebdd0_0 .net "res", 0 0, L_0x1a189e0; 1 drivers +v0x19ebe90_0 .net "xorRes", 0 0, L_0x1a18790; 1 drivers +S_0x19ea760 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19ea470; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a18280 .functor XOR 1, L_0x1a18c10, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a182f0 .functor XOR 1, L_0x1a18b70, L_0x1a18280, C4<0>, C4<0>; +L_0x1a183b0 .functor XOR 1, L_0x1a182f0, L_0x1a18000, C4<0>, C4<0>; +L_0x1a18510 .functor AND 1, L_0x1a18b70, L_0x1a18280, C4<1>, C4<1>; +L_0x1a18580 .functor AND 1, L_0x1a182f0, L_0x1a18000, C4<1>, C4<1>; +L_0x1a185f0 .functor OR 1, L_0x1a18510, L_0x1a18580, C4<0>, C4<0>; +v0x19ea9f0_0 .net "AandB", 0 0, L_0x1a18510; 1 drivers +v0x19eaad0_0 .net "BxorSub", 0 0, L_0x1a18280; 1 drivers +v0x19eab90_0 .net "a", 0 0, L_0x1a18b70; alias, 1 drivers +v0x19eac60_0 .net "b", 0 0, L_0x1a18c10; alias, 1 drivers +v0x19ead20_0 .net "carryin", 0 0, L_0x1a18000; alias, 1 drivers +v0x19eae30_0 .net "carryout", 0 0, L_0x1a185f0; alias, 1 drivers +v0x19eaef0_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19eaf90_0 .net "res", 0 0, L_0x1a183b0; alias, 1 drivers +v0x19eb050_0 .net "xAorB", 0 0, L_0x1a182f0; 1 drivers +v0x19eb1a0_0 .net "xAorBandCin", 0 0, L_0x1a18580; 1 drivers +S_0x19ec050 .scope generate, "genblk1[27]" "genblk1[27]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19ec210 .param/l "i" 0 3 165, +C4<011011>; +S_0x19ec2d0 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19ec050; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a193b0 .functor XOR 1, L_0x1a19790, L_0x1a18d40, C4<0>, C4<0>; +L_0x1a194b0 .functor AND 1, L_0x1a18fd0, v0x19ed970_0, C4<1>, C4<1>; +L_0x1a19520 .functor AND 1, L_0x1a193b0, v0x19edab0_0, C4<1>, C4<1>; +L_0x1a19590 .functor AND 1, L_0x1a19790, v0x19ed8d0_0, C4<1>, C4<1>; +L_0x1a19600 .functor OR 1, L_0x1a194b0, L_0x1a19520, L_0x1a19590, C4<0>; +v0x19ed1c0_0 .net "a", 0 0, L_0x1a19790; 1 drivers +v0x19ed280_0 .net "addRes", 0 0, L_0x1a18fd0; 1 drivers +v0x19ed350_0 .net "b", 0 0, L_0x1a18d40; 1 drivers +v0x19ed450_0 .net "carryIn", 0 0, L_0x1a18e70; 1 drivers +v0x19ed520_0 .net "carryOut", 0 0, L_0x1a19210; 1 drivers +v0x19ed5c0_0 .net "finalA", 0 0, L_0x1a19590; 1 drivers +v0x19ed660_0 .net "finalAdd", 0 0, L_0x1a194b0; 1 drivers +v0x19ed700_0 .net "finalXor", 0 0, L_0x1a19520; 1 drivers +v0x19ed7a0_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19ed8d0_0 .var "isA", 0 0; +v0x19ed970_0 .var "isAdd", 0 0; +v0x19eda10_0 .var "isSubtract", 0 0; +v0x19edab0_0 .var "isXor", 0 0; +v0x19edb70_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19edc30_0 .net "res", 0 0, L_0x1a19600; 1 drivers +v0x19edcf0_0 .net "xorRes", 0 0, L_0x1a193b0; 1 drivers +S_0x19ec5c0 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19ec2d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a18130 .functor XOR 1, L_0x1a18d40, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a181a0 .functor XOR 1, L_0x1a19790, L_0x1a18130, C4<0>, C4<0>; +L_0x1a18fd0 .functor XOR 1, L_0x1a181a0, L_0x1a18e70, C4<0>, C4<0>; +L_0x1a19130 .functor AND 1, L_0x1a19790, L_0x1a18130, C4<1>, C4<1>; +L_0x1a191a0 .functor AND 1, L_0x1a181a0, L_0x1a18e70, C4<1>, C4<1>; +L_0x1a19210 .functor OR 1, L_0x1a19130, L_0x1a191a0, C4<0>, C4<0>; +v0x19ec850_0 .net "AandB", 0 0, L_0x1a19130; 1 drivers +v0x19ec930_0 .net "BxorSub", 0 0, L_0x1a18130; 1 drivers +v0x19ec9f0_0 .net "a", 0 0, L_0x1a19790; alias, 1 drivers +v0x19ecac0_0 .net "b", 0 0, L_0x1a18d40; alias, 1 drivers +v0x19ecb80_0 .net "carryin", 0 0, L_0x1a18e70; alias, 1 drivers +v0x19ecc90_0 .net "carryout", 0 0, L_0x1a19210; alias, 1 drivers +v0x19ecd50_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19ecdf0_0 .net "res", 0 0, L_0x1a18fd0; alias, 1 drivers +v0x19eceb0_0 .net "xAorB", 0 0, L_0x1a181a0; 1 drivers +v0x19ed000_0 .net "xAorBandCin", 0 0, L_0x1a191a0; 1 drivers +S_0x19edeb0 .scope generate, "genblk1[28]" "genblk1[28]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19ee070 .param/l "i" 0 3 165, +C4<011100>; +S_0x19ee130 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19edeb0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a19ff0 .functor XOR 1, L_0x1a1a3a0, L_0x1a1a440, C4<0>, C4<0>; +L_0x1a1a0f0 .functor AND 1, L_0x1a19c10, v0x19ef7d0_0, C4<1>, C4<1>; +L_0x1a1a160 .functor AND 1, L_0x1a19ff0, v0x19ef910_0, C4<1>, C4<1>; +L_0x1a1a1d0 .functor AND 1, L_0x1a1a3a0, v0x19ef730_0, C4<1>, C4<1>; +L_0x1a1a240 .functor OR 1, L_0x1a1a0f0, L_0x1a1a160, L_0x1a1a1d0, C4<0>; +v0x19ef020_0 .net "a", 0 0, L_0x1a1a3a0; 1 drivers +v0x19ef0e0_0 .net "addRes", 0 0, L_0x1a19c10; 1 drivers +v0x19ef1b0_0 .net "b", 0 0, L_0x1a1a440; 1 drivers +v0x19ef2b0_0 .net "carryIn", 0 0, L_0x1a19830; 1 drivers +v0x19ef380_0 .net "carryOut", 0 0, L_0x1a19e50; 1 drivers +v0x19ef420_0 .net "finalA", 0 0, L_0x1a1a1d0; 1 drivers +v0x19ef4c0_0 .net "finalAdd", 0 0, L_0x1a1a0f0; 1 drivers +v0x19ef560_0 .net "finalXor", 0 0, L_0x1a1a160; 1 drivers +v0x19ef600_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19ef730_0 .var "isA", 0 0; +v0x19ef7d0_0 .var "isAdd", 0 0; +v0x19ef870_0 .var "isSubtract", 0 0; +v0x19ef910_0 .var "isXor", 0 0; +v0x19ef9d0_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19efa90_0 .net "res", 0 0, L_0x1a1a240; 1 drivers +v0x19efb50_0 .net "xorRes", 0 0, L_0x1a19ff0; 1 drivers +S_0x19ee420 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19ee130; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a19ae0 .functor XOR 1, L_0x1a1a440, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a19b50 .functor XOR 1, L_0x1a1a3a0, L_0x1a19ae0, C4<0>, C4<0>; +L_0x1a19c10 .functor XOR 1, L_0x1a19b50, L_0x1a19830, C4<0>, C4<0>; +L_0x1a19d70 .functor AND 1, L_0x1a1a3a0, L_0x1a19ae0, C4<1>, C4<1>; +L_0x1a19de0 .functor AND 1, L_0x1a19b50, L_0x1a19830, C4<1>, C4<1>; +L_0x1a19e50 .functor OR 1, L_0x1a19d70, L_0x1a19de0, C4<0>, C4<0>; +v0x19ee6b0_0 .net "AandB", 0 0, L_0x1a19d70; 1 drivers +v0x19ee790_0 .net "BxorSub", 0 0, L_0x1a19ae0; 1 drivers +v0x19ee850_0 .net "a", 0 0, L_0x1a1a3a0; alias, 1 drivers +v0x19ee920_0 .net "b", 0 0, L_0x1a1a440; alias, 1 drivers +v0x19ee9e0_0 .net "carryin", 0 0, L_0x1a19830; alias, 1 drivers +v0x19eeaf0_0 .net "carryout", 0 0, L_0x1a19e50; alias, 1 drivers +v0x19eebb0_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19eec50_0 .net "res", 0 0, L_0x1a19c10; alias, 1 drivers +v0x19eed10_0 .net "xAorB", 0 0, L_0x1a19b50; 1 drivers +v0x19eee60_0 .net "xAorBandCin", 0 0, L_0x1a19de0; 1 drivers +S_0x19efd10 .scope generate, "genblk1[29]" "genblk1[29]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19efed0 .param/l "i" 0 3 165, +C4<011101>; +S_0x19eff90 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19efd10; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a1abc0 .functor XOR 1, L_0x1a1afa0, L_0x1a1a570, C4<0>, C4<0>; +L_0x1a1acc0 .functor AND 1, L_0x1a1a830, v0x19f1630_0, C4<1>, C4<1>; +L_0x1a1ad30 .functor AND 1, L_0x1a1abc0, v0x19f1770_0, C4<1>, C4<1>; +L_0x1a1ada0 .functor AND 1, L_0x1a1afa0, v0x19f1590_0, C4<1>, C4<1>; +L_0x1a1ae10 .functor OR 1, L_0x1a1acc0, L_0x1a1ad30, L_0x1a1ada0, C4<0>; +v0x19f0e80_0 .net "a", 0 0, L_0x1a1afa0; 1 drivers +v0x19f0f40_0 .net "addRes", 0 0, L_0x1a1a830; 1 drivers +v0x19f1010_0 .net "b", 0 0, L_0x1a1a570; 1 drivers +v0x19f1110_0 .net "carryIn", 0 0, L_0x1a1a6a0; 1 drivers +v0x19f11e0_0 .net "carryOut", 0 0, L_0x1a1aa20; 1 drivers +v0x19f1280_0 .net "finalA", 0 0, L_0x1a1ada0; 1 drivers +v0x19f1320_0 .net "finalAdd", 0 0, L_0x1a1acc0; 1 drivers +v0x19f13c0_0 .net "finalXor", 0 0, L_0x1a1ad30; 1 drivers +v0x19f1460_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19f1590_0 .var "isA", 0 0; +v0x19f1630_0 .var "isAdd", 0 0; +v0x19f16d0_0 .var "isSubtract", 0 0; +v0x19f1770_0 .var "isXor", 0 0; +v0x19f1830_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19f18f0_0 .net "res", 0 0, L_0x1a1ae10; 1 drivers +v0x19f19b0_0 .net "xorRes", 0 0, L_0x1a1abc0; 1 drivers +S_0x19f0280 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19eff90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a19960 .functor XOR 1, L_0x1a1a570, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a199d0 .functor XOR 1, L_0x1a1afa0, L_0x1a19960, C4<0>, C4<0>; +L_0x1a1a830 .functor XOR 1, L_0x1a199d0, L_0x1a1a6a0, C4<0>, C4<0>; +L_0x1a1a940 .functor AND 1, L_0x1a1afa0, L_0x1a19960, C4<1>, C4<1>; +L_0x1a1a9b0 .functor AND 1, L_0x1a199d0, L_0x1a1a6a0, C4<1>, C4<1>; +L_0x1a1aa20 .functor OR 1, L_0x1a1a940, L_0x1a1a9b0, C4<0>, C4<0>; +v0x19f0510_0 .net "AandB", 0 0, L_0x1a1a940; 1 drivers +v0x19f05f0_0 .net "BxorSub", 0 0, L_0x1a19960; 1 drivers +v0x19f06b0_0 .net "a", 0 0, L_0x1a1afa0; alias, 1 drivers +v0x19f0780_0 .net "b", 0 0, L_0x1a1a570; alias, 1 drivers +v0x19f0840_0 .net "carryin", 0 0, L_0x1a1a6a0; alias, 1 drivers +v0x19f0950_0 .net "carryout", 0 0, L_0x1a1aa20; alias, 1 drivers +v0x19f0a10_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19f0ab0_0 .net "res", 0 0, L_0x1a1a830; alias, 1 drivers +v0x19f0b70_0 .net "xAorB", 0 0, L_0x1a199d0; 1 drivers +v0x19f0cc0_0 .net "xAorBandCin", 0 0, L_0x1a1a9b0; 1 drivers +S_0x19f1b70 .scope generate, "genblk1[30]" "genblk1[30]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f1d30 .param/l "i" 0 3 165, +C4<011110>; +S_0x19f1df0 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19f1b70; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a1b7e0 .functor XOR 1, L_0x1a1bbc0, L_0x1a0f830, C4<0>, C4<0>; +L_0x1a1b8e0 .functor AND 1, L_0x1a1b400, v0x19f3490_0, C4<1>, C4<1>; +L_0x1a1b950 .functor AND 1, L_0x1a1b7e0, v0x19f35d0_0, C4<1>, C4<1>; +L_0x1a1b9c0 .functor AND 1, L_0x1a1bbc0, v0x19f33f0_0, C4<1>, C4<1>; +L_0x1a1ba30 .functor OR 1, L_0x1a1b8e0, L_0x1a1b950, L_0x1a1b9c0, C4<0>; +v0x19f2ce0_0 .net "a", 0 0, L_0x1a1bbc0; 1 drivers +v0x19f2da0_0 .net "addRes", 0 0, L_0x1a1b400; 1 drivers +v0x19f2e70_0 .net "b", 0 0, L_0x1a0f830; 1 drivers +v0x19f2f70_0 .net "carryIn", 0 0, L_0x1a0f960; 1 drivers +v0x19f3040_0 .net "carryOut", 0 0, L_0x1a1b640; 1 drivers +v0x19f30e0_0 .net "finalA", 0 0, L_0x1a1b9c0; 1 drivers +v0x19f3180_0 .net "finalAdd", 0 0, L_0x1a1b8e0; 1 drivers +v0x19f3220_0 .net "finalXor", 0 0, L_0x1a1b950; 1 drivers +v0x19f32c0_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19f33f0_0 .var "isA", 0 0; +v0x19f3490_0 .var "isAdd", 0 0; +v0x19f3530_0 .var "isSubtract", 0 0; +v0x19f35d0_0 .var "isXor", 0 0; +v0x19f3690_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19f3750_0 .net "res", 0 0, L_0x1a1ba30; 1 drivers +v0x19f3810_0 .net "xorRes", 0 0, L_0x1a1b7e0; 1 drivers +S_0x19f20e0 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19f1df0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a1b320 .functor XOR 1, L_0x1a0f830, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a1b390 .functor XOR 1, L_0x1a1bbc0, L_0x1a1b320, C4<0>, C4<0>; +L_0x1a1b400 .functor XOR 1, L_0x1a1b390, L_0x1a0f960, C4<0>, C4<0>; +L_0x1a1b560 .functor AND 1, L_0x1a1bbc0, L_0x1a1b320, C4<1>, C4<1>; +L_0x1a1b5d0 .functor AND 1, L_0x1a1b390, L_0x1a0f960, C4<1>, C4<1>; +L_0x1a1b640 .functor OR 1, L_0x1a1b560, L_0x1a1b5d0, C4<0>, C4<0>; +v0x19f2370_0 .net "AandB", 0 0, L_0x1a1b560; 1 drivers +v0x19f2450_0 .net "BxorSub", 0 0, L_0x1a1b320; 1 drivers +v0x19f2510_0 .net "a", 0 0, L_0x1a1bbc0; alias, 1 drivers +v0x19f25e0_0 .net "b", 0 0, L_0x1a0f830; alias, 1 drivers +v0x19f26a0_0 .net "carryin", 0 0, L_0x1a0f960; alias, 1 drivers +v0x19f27b0_0 .net "carryout", 0 0, L_0x1a1b640; alias, 1 drivers +v0x19f2870_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19f2910_0 .net "res", 0 0, L_0x1a1b400; alias, 1 drivers +v0x19f29d0_0 .net "xAorB", 0 0, L_0x1a1b390; 1 drivers +v0x19f2b20_0 .net "xAorBandCin", 0 0, L_0x1a1b5d0; 1 drivers +S_0x19f39d0 .scope generate, "genblk1[31]" "genblk1[31]" 3 165, 3 165 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f3b90 .param/l "i" 0 3 165, +C4<011111>; +S_0x19f3c50 .scope module, "aluBitSlice" "ALUBitSlice" 3 168, 3 18 0, S_0x19f39d0; + .timescale -9 -12; + .port_info 0 /INPUT 1 "a" + .port_info 1 /INPUT 1 "b" + .port_info 2 /INPUT 6 "opcode" + .port_info 3 /INPUT 6 "funct" + .port_info 4 /INPUT 1 "carryIn" + .port_info 5 /OUTPUT 1 "res" + .port_info 6 /OUTPUT 1 "carryOut" + .port_info 7 /OUTPUT 1 "isSubtract" +L_0x1a1b280 .functor XOR 1, L_0x1a1cab0, L_0x1a1c480, C4<0>, C4<0>; +L_0x1a1c800 .functor AND 1, L_0x1a07ec0, v0x19f52f0_0, C4<1>, C4<1>; +L_0x1a1c870 .functor AND 1, L_0x1a1b280, v0x19f5430_0, C4<1>, C4<1>; +L_0x1a1c8e0 .functor AND 1, L_0x1a1cab0, v0x19f5250_0, C4<1>, C4<1>; +L_0x1a1c950 .functor OR 1, L_0x1a1c800, L_0x1a1c870, L_0x1a1c8e0, C4<0>; +v0x19f4b40_0 .net "a", 0 0, L_0x1a1cab0; 1 drivers +v0x19f4c00_0 .net "addRes", 0 0, L_0x1a07ec0; 1 drivers +v0x19f4cd0_0 .net "b", 0 0, L_0x1a1c480; 1 drivers +v0x19f4dd0_0 .net "carryIn", 0 0, L_0x1a1c5b0; 1 drivers +v0x19f4ea0_0 .net "carryOut", 0 0, L_0x1a1b120; 1 drivers +v0x19f4f40_0 .net "finalA", 0 0, L_0x1a1c8e0; 1 drivers +v0x19f4fe0_0 .net "finalAdd", 0 0, L_0x1a1c800; 1 drivers +v0x19f5080_0 .net "finalXor", 0 0, L_0x1a1c870; 1 drivers +v0x19f5120_0 .net "funct", 5 0, v0x1a03b70_0; alias, 1 drivers +v0x19f5250_0 .var "isA", 0 0; +v0x19f52f0_0 .var "isAdd", 0 0; +v0x19f5390_0 .var "isSubtract", 0 0; +v0x19f5430_0 .var "isXor", 0 0; +v0x19f54f0_0 .net "opcode", 5 0, v0x1a03c10_0; alias, 1 drivers +v0x19f55b0_0 .net "res", 0 0, L_0x1a1c950; 1 drivers +v0x19f5670_0 .net "xorRes", 0 0, L_0x1a1b280; 1 drivers +S_0x19f3f40 .scope module, "adder" "AdderAndSubtractor" 3 37, 3 81 0, S_0x19f3c50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "res" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "isSubtract" + .port_info 5 /INPUT 1 "carryin" +L_0x1a0fb60 .functor XOR 1, L_0x1a1c480, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a0fbd0 .functor XOR 1, L_0x1a1cab0, L_0x1a0fb60, C4<0>, C4<0>; +L_0x1a07ec0 .functor XOR 1, L_0x1a0fbd0, L_0x1a1c5b0, C4<0>, C4<0>; +L_0x1a1b040 .functor AND 1, L_0x1a1cab0, L_0x1a0fb60, C4<1>, C4<1>; +L_0x1a1b0b0 .functor AND 1, L_0x1a0fbd0, L_0x1a1c5b0, C4<1>, C4<1>; +L_0x1a1b120 .functor OR 1, L_0x1a1b040, L_0x1a1b0b0, C4<0>, C4<0>; +v0x19f41d0_0 .net "AandB", 0 0, L_0x1a1b040; 1 drivers +v0x19f42b0_0 .net "BxorSub", 0 0, L_0x1a0fb60; 1 drivers +v0x19f4370_0 .net "a", 0 0, L_0x1a1cab0; alias, 1 drivers +v0x19f4440_0 .net "b", 0 0, L_0x1a1c480; alias, 1 drivers +v0x19f4500_0 .net "carryin", 0 0, L_0x1a1c5b0; alias, 1 drivers +v0x19f4610_0 .net "carryout", 0 0, L_0x1a1b120; alias, 1 drivers +v0x19f46d0_0 .net8 "isSubtract", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +v0x19f4770_0 .net "res", 0 0, L_0x1a07ec0; alias, 1 drivers +v0x19f4830_0 .net "xAorB", 0 0, L_0x1a0fbd0; 1 drivers +v0x19f4980_0 .net "xAorBandCin", 0 0, L_0x1a1b0b0; 1 drivers +S_0x19f5830 .scope generate, "genblk2[0]" "genblk2[0]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19d6f30 .param/l "j" 0 3 217, +C4<00>; +L_0x1a1db60 .functor AND 1, L_0x1a1dbd0, L_0x1a21240, C4<1>, C4<1>; +v0x19f5c00_0 .net *"_s1", 0 0, L_0x1a1dbd0; 1 drivers +S_0x19f5ca0 .scope generate, "genblk2[1]" "genblk2[1]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f5eb0 .param/l "j" 0 3 217, +C4<01>; +L_0x1a1d260 .functor AND 1, L_0x1a1d320, L_0x1a21240, C4<1>, C4<1>; +v0x19f5f70_0 .net *"_s1", 0 0, L_0x1a1d320; 1 drivers +S_0x19f6050 .scope generate, "genblk2[2]" "genblk2[2]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f6260 .param/l "j" 0 3 217, +C4<010>; +L_0x1a1d410 .functor AND 1, L_0x1a1d480, L_0x1a21240, C4<1>, C4<1>; +v0x19f6320_0 .net *"_s1", 0 0, L_0x1a1d480; 1 drivers +S_0x19f6400 .scope generate, "genblk2[3]" "genblk2[3]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f6610 .param/l "j" 0 3 217, +C4<011>; +L_0x1a1dd10 .functor AND 1, L_0x1a1de10, L_0x1a21240, C4<1>, C4<1>; +v0x19f66d0_0 .net *"_s1", 0 0, L_0x1a1de10; 1 drivers +S_0x19f67b0 .scope generate, "genblk2[4]" "genblk2[4]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f69c0 .param/l "j" 0 3 217, +C4<0100>; +L_0x1a1deb0 .functor AND 1, L_0x1a1df20, L_0x1a21240, C4<1>, C4<1>; +v0x19f6a80_0 .net *"_s1", 0 0, L_0x1a1df20; 1 drivers +S_0x19f6b60 .scope generate, "genblk2[5]" "genblk2[5]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f6d70 .param/l "j" 0 3 217, +C4<0101>; +L_0x1a1dfc0 .functor AND 1, L_0x1a1e400, L_0x1a21240, C4<1>, C4<1>; +v0x19f6e30_0 .net *"_s1", 0 0, L_0x1a1e400; 1 drivers +S_0x19f6f10 .scope generate, "genblk2[6]" "genblk2[6]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f7120 .param/l "j" 0 3 217, +C4<0110>; +L_0x1a1e4f0 .functor AND 1, L_0x1a1e560, L_0x1a21240, C4<1>, C4<1>; +v0x19f71e0_0 .net *"_s1", 0 0, L_0x1a1e560; 1 drivers +S_0x19f72c0 .scope generate, "genblk2[7]" "genblk2[7]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f74d0 .param/l "j" 0 3 217, +C4<0111>; +L_0x1a1e030 .functor AND 1, L_0x1a1e1b0, L_0x1a21240, C4<1>, C4<1>; +v0x19f7590_0 .net *"_s1", 0 0, L_0x1a1e1b0; 1 drivers +S_0x19f7670 .scope generate, "genblk2[8]" "genblk2[8]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f7880 .param/l "j" 0 3 217, +C4<01000>; +L_0x1a1e2a0 .functor AND 1, L_0x1a1e310, L_0x1a21240, C4<1>, C4<1>; +v0x19f7940_0 .net *"_s1", 0 0, L_0x1a1e310; 1 drivers +S_0x19f7a20 .scope generate, "genblk2[9]" "genblk2[9]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f7c30 .param/l "j" 0 3 217, +C4<01001>; +L_0x1a1dd80 .functor AND 1, L_0x1a1eac0, L_0x1a21240, C4<1>, C4<1>; +v0x19f7cf0_0 .net *"_s1", 0 0, L_0x1a1eac0; 1 drivers +S_0x19f7dd0 .scope generate, "genblk2[10]" "genblk2[10]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f7fe0 .param/l "j" 0 3 217, +C4<01010>; +L_0x1a1ebb0 .functor AND 1, L_0x1a1ec20, L_0x1a21240, C4<1>, C4<1>; +v0x19f80a0_0 .net *"_s1", 0 0, L_0x1a1ec20; 1 drivers +S_0x19f8180 .scope generate, "genblk2[11]" "genblk2[11]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f8390 .param/l "j" 0 3 217, +C4<01011>; +L_0x1a1e760 .functor AND 1, L_0x1a1e7d0, L_0x1a21240, C4<1>, C4<1>; +v0x19f8450_0 .net *"_s1", 0 0, L_0x1a1e7d0; 1 drivers +S_0x19f8530 .scope generate, "genblk2[12]" "genblk2[12]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f8740 .param/l "j" 0 3 217, +C4<01100>; +L_0x1a1e8c0 .functor AND 1, L_0x1a1e930, L_0x1a21240, C4<1>, C4<1>; +v0x19f8800_0 .net *"_s1", 0 0, L_0x1a1e930; 1 drivers +S_0x19f88e0 .scope generate, "genblk2[13]" "genblk2[13]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f8af0 .param/l "j" 0 3 217, +C4<01101>; +L_0x1a1ea20 .functor AND 1, L_0x1a1f090, L_0x1a21240, C4<1>, C4<1>; +v0x19f8bb0_0 .net *"_s1", 0 0, L_0x1a1f090; 1 drivers +S_0x19f8c90 .scope generate, "genblk2[14]" "genblk2[14]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f8ea0 .param/l "j" 0 3 217, +C4<01110>; +L_0x1a1f180 .functor AND 1, L_0x1a1f1f0, L_0x1a21240, C4<1>, C4<1>; +v0x19f8f60_0 .net *"_s1", 0 0, L_0x1a1f1f0; 1 drivers +S_0x19f9040 .scope generate, "genblk2[15]" "genblk2[15]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f9250 .param/l "j" 0 3 217, +C4<01111>; +L_0x1a1e650 .functor AND 1, L_0x1a1e6c0, L_0x1a21240, C4<1>, C4<1>; +v0x19f9310_0 .net *"_s1", 0 0, L_0x1a1e6c0; 1 drivers +S_0x19f93f0 .scope generate, "genblk2[16]" "genblk2[16]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f9600 .param/l "j" 0 3 217, +C4<010000>; +L_0x1a1e0f0 .functor AND 1, L_0x1a1ef20, L_0x1a21240, C4<1>, C4<1>; +v0x19f96c0_0 .net *"_s1", 0 0, L_0x1a1ef20; 1 drivers +S_0x19f97a0 .scope generate, "genblk2[17]" "genblk2[17]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f99b0 .param/l "j" 0 3 217, +C4<010001>; +L_0x1a1efc0 .functor AND 1, L_0x1a1f890, L_0x1a21240, C4<1>, C4<1>; +v0x19f9a70_0 .net *"_s1", 0 0, L_0x1a1f890; 1 drivers +S_0x19f9b50 .scope generate, "genblk2[18]" "genblk2[18]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19f9d60 .param/l "j" 0 3 217, +C4<010010>; +L_0x1a1f930 .functor AND 1, L_0x1a1f9a0, L_0x1a21240, C4<1>, C4<1>; +v0x19f9e20_0 .net *"_s1", 0 0, L_0x1a1f9a0; 1 drivers +S_0x19f9f00 .scope generate, "genblk2[19]" "genblk2[19]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19fa110 .param/l "j" 0 3 217, +C4<010011>; +L_0x1a1f4f0 .functor AND 1, L_0x1a1f560, L_0x1a21240, C4<1>, C4<1>; +v0x19fa1d0_0 .net *"_s1", 0 0, L_0x1a1f560; 1 drivers +S_0x19fa2b0 .scope generate, "genblk2[20]" "genblk2[20]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19fa4c0 .param/l "j" 0 3 217, +C4<010100>; +L_0x1a1f650 .functor AND 1, L_0x1a1f6c0, L_0x1a21240, C4<1>, C4<1>; +v0x19fa580_0 .net *"_s1", 0 0, L_0x1a1f6c0; 1 drivers +S_0x19fa660 .scope generate, "genblk2[21]" "genblk2[21]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19fa870 .param/l "j" 0 3 217, +C4<010101>; +L_0x1a1f7b0 .functor AND 1, L_0x1a1fe50, L_0x1a21240, C4<1>, C4<1>; +v0x19fa930_0 .net *"_s1", 0 0, L_0x1a1fe50; 1 drivers +S_0x19faa10 .scope generate, "genblk2[22]" "genblk2[22]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19fac20 .param/l "j" 0 3 217, +C4<010110>; +L_0x1a1fef0 .functor AND 1, L_0x1a1ff60, L_0x1a21240, C4<1>, C4<1>; +v0x19face0_0 .net *"_s1", 0 0, L_0x1a1ff60; 1 drivers +S_0x19fadc0 .scope generate, "genblk2[23]" "genblk2[23]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19fafd0 .param/l "j" 0 3 217, +C4<010111>; +L_0x1a1fa90 .functor AND 1, L_0x1a1fb00, L_0x1a21240, C4<1>, C4<1>; +v0x19fb090_0 .net *"_s1", 0 0, L_0x1a1fb00; 1 drivers +S_0x19fb170 .scope generate, "genblk2[24]" "genblk2[24]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19fb380 .param/l "j" 0 3 217, +C4<011000>; +L_0x1a1fbf0 .functor AND 1, L_0x1a1fc60, L_0x1a21240, C4<1>, C4<1>; +v0x19fb440_0 .net *"_s1", 0 0, L_0x1a1fc60; 1 drivers +S_0x19fb520 .scope generate, "genblk2[25]" "genblk2[25]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19fb730 .param/l "j" 0 3 217, +C4<011001>; +L_0x1a1fd50 .functor AND 1, L_0x1a20430, L_0x1a21240, C4<1>, C4<1>; +v0x19fb7f0_0 .net *"_s1", 0 0, L_0x1a20430; 1 drivers +S_0x19fb8d0 .scope generate, "genblk2[26]" "genblk2[26]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19fbae0 .param/l "j" 0 3 217, +C4<011010>; +L_0x1a204d0 .functor AND 1, L_0x1a20540, L_0x1a21240, C4<1>, C4<1>; +v0x19fbba0_0 .net *"_s1", 0 0, L_0x1a20540; 1 drivers +S_0x19fbc80 .scope generate, "genblk2[27]" "genblk2[27]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19fbe90 .param/l "j" 0 3 217, +C4<011011>; +L_0x1a20050 .functor AND 1, L_0x1a200c0, L_0x1a21240, C4<1>, C4<1>; +v0x19fbf50_0 .net *"_s1", 0 0, L_0x1a200c0; 1 drivers +S_0x19fc030 .scope generate, "genblk2[28]" "genblk2[28]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19fc240 .param/l "j" 0 3 217, +C4<011100>; +L_0x1a201b0 .functor AND 1, L_0x1a20220, L_0x1a21240, C4<1>, C4<1>; +v0x19fc300_0 .net *"_s1", 0 0, L_0x1a20220; 1 drivers +S_0x19fc3e0 .scope generate, "genblk2[29]" "genblk2[29]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19fc5f0 .param/l "j" 0 3 217, +C4<011101>; +L_0x1a20310 .functor AND 1, L_0x1a20380, L_0x1a21240, C4<1>, C4<1>; +v0x19fc6b0_0 .net *"_s1", 0 0, L_0x1a20380; 1 drivers +S_0x19fc790 .scope generate, "genblk2[30]" "genblk2[30]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19fc9a0 .param/l "j" 0 3 217, +C4<011110>; +L_0x1a20a80 .functor AND 1, L_0x1a20af0, L_0x1a21240, C4<1>, C4<1>; +v0x19fca60_0 .net *"_s1", 0 0, L_0x1a20af0; 1 drivers +S_0x19fcb40 .scope generate, "genblk2[31]" "genblk2[31]" 3 217, 3 217 0, S_0x18c67f0; + .timescale -9 -12; +P_0x19fcd50 .param/l "j" 0 3 217, +C4<011111>; +L_0x1a219a0 .functor AND 1, L_0x1a1ed10, L_0x1a21240, C4<1>, C4<1>; +v0x19fce10_0 .net *"_s1", 0 0, L_0x1a1ed10; 1 drivers +S_0x19fcef0 .scope module, "overflowCalc" "didOverflow" 3 225, 3 115 0, S_0x18c67f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "overflow" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "s" + .port_info 4 /INPUT 1 "sub" +L_0x1a22150 .functor XOR 1, L_0x1a22e80, RS_0x7fa24fdc8138, C4<0>, C4<0>; +L_0x1a221c0 .functor NOT 1, L_0x1a22de0, C4<0>, C4<0>, C4<0>; +L_0x1a22770 .functor NOT 1, L_0x1a22150, C4<0>, C4<0>, C4<0>; +L_0x1a227e0 .functor NOT 1, L_0x1a22330, C4<0>, C4<0>, C4<0>; +L_0x1a22850 .functor AND 1, L_0x1a22de0, L_0x1a22150, C4<1>, C4<1>; +L_0x1a22910 .functor AND 1, L_0x1a221c0, L_0x1a22770, C4<1>, C4<1>; +L_0x1a22a20 .functor AND 1, L_0x1a22850, L_0x1a227e0, C4<1>, C4<1>; +L_0x1a22b30 .functor AND 1, L_0x1a22910, L_0x1a22330, C4<1>, C4<1>; +L_0x1a22c90 .functor OR 1, L_0x1a22a20, L_0x1a22b30, C4<0>, C4<0>; +v0x19f5a70_0 .net "BxorSub", 0 0, L_0x1a22150; 1 drivers +v0x19f5b50_0 .net "a", 0 0, L_0x1a22de0; 1 drivers +v0x19fd4f0_0 .net "aAndB", 0 0, L_0x1a22850; 1 drivers +v0x19fd5c0_0 .net "b", 0 0, L_0x1a22e80; 1 drivers +v0x19fd680_0 .net "negToPos", 0 0, L_0x1a22a20; 1 drivers +v0x19fd790_0 .net "notA", 0 0, L_0x1a221c0; 1 drivers +v0x19fd850_0 .net "notB", 0 0, L_0x1a22770; 1 drivers +v0x19fd910_0 .net "notS", 0 0, L_0x1a227e0; 1 drivers +v0x19fd9d0_0 .net "notaAndNotb", 0 0, L_0x1a22910; 1 drivers +v0x19fdb20_0 .net "overflow", 0 0, L_0x1a22c90; alias, 1 drivers +v0x19fdbe0_0 .net "posToNeg", 0 0, L_0x1a22b30; 1 drivers +v0x19fdca0_0 .net "s", 0 0, L_0x1a22330; 1 drivers +v0x19fdd60_0 .net8 "sub", 0 0, RS_0x7fa24fdc8138; alias, 32 drivers +S_0x19d7bf0 .scope module, "zeroCalc" "isZero" 3 233, 3 102 0, S_0x18c67f0; + .timescale -9 -12; + .port_info 0 /INPUT 32 "zeroBit" + .port_info 1 /OUTPUT 1 "out" +L_0x1a223d0/0/0 .functor OR 1, L_0x1a22550, L_0x1a22640, L_0x1a233c0, L_0x1a234b0; +L_0x1a223d0/0/4 .functor OR 1, L_0x1a236b0, L_0x1a23750, L_0x1a23840, L_0x1a23930; +L_0x1a223d0/0/8 .functor OR 1, L_0x1a23a70, L_0x1a23b60, L_0x1a23cb0, L_0x1a23d50; +L_0x1a223d0/0/12 .functor OR 1, L_0x1a23610, L_0x1a240a0, L_0x1a24210, L_0x1a24300; +L_0x1a223d0/0/16 .functor OR 1, L_0x1a24480, L_0x1a24570, L_0x1a24700, L_0x1a247a0; +L_0x1a223d0/0/20 .functor OR 1, L_0x1a24660, L_0x1a24990, L_0x1a24890, L_0x1a24b90; +L_0x1a223d0/0/24 .functor OR 1, L_0x1a24a80, L_0x1a24da0, L_0x1a24c80, L_0x1a24fc0; +L_0x1a223d0/0/28 .functor OR 1, L_0x1a24e90, L_0x1a23f30, L_0x1a23e40, L_0x1a255c0; +L_0x1a223d0/1/0 .functor OR 1, L_0x1a223d0/0/0, L_0x1a223d0/0/4, L_0x1a223d0/0/8, L_0x1a223d0/0/12; +L_0x1a223d0/1/4 .functor OR 1, L_0x1a223d0/0/16, L_0x1a223d0/0/20, L_0x1a223d0/0/24, L_0x1a223d0/0/28; +L_0x1a223d0 .functor OR 1, L_0x1a223d0/1/0, L_0x1a223d0/1/4, C4<0>, C4<0>; +L_0x1a24190 .functor NOT 1, L_0x1a223d0, C4<0>, C4<0>, C4<0>; +v0x19d7de0_0 .net *"_s1", 0 0, L_0x1a22550; 1 drivers +v0x19d7ee0_0 .net *"_s11", 0 0, L_0x1a23750; 1 drivers +v0x19fe630_0 .net *"_s13", 0 0, L_0x1a23840; 1 drivers +v0x19fe720_0 .net *"_s15", 0 0, L_0x1a23930; 1 drivers +v0x19fe800_0 .net *"_s17", 0 0, L_0x1a23a70; 1 drivers +v0x19fe930_0 .net *"_s19", 0 0, L_0x1a23b60; 1 drivers +v0x19fea10_0 .net *"_s21", 0 0, L_0x1a23cb0; 1 drivers +v0x19feaf0_0 .net *"_s23", 0 0, L_0x1a23d50; 1 drivers +v0x19febd0_0 .net *"_s25", 0 0, L_0x1a23610; 1 drivers +v0x19fed40_0 .net *"_s27", 0 0, L_0x1a240a0; 1 drivers +v0x19fee20_0 .net *"_s29", 0 0, L_0x1a24210; 1 drivers +v0x19fef00_0 .net *"_s3", 0 0, L_0x1a22640; 1 drivers +v0x19fefe0_0 .net *"_s31", 0 0, L_0x1a24300; 1 drivers +v0x19ff080_0 .net *"_s33", 0 0, L_0x1a24480; 1 drivers +v0x19ff140_0 .net *"_s35", 0 0, L_0x1a24570; 1 drivers +v0x19ff220_0 .net *"_s37", 0 0, L_0x1a24700; 1 drivers +v0x19ff300_0 .net *"_s39", 0 0, L_0x1a247a0; 1 drivers +v0x19ff4b0_0 .net *"_s41", 0 0, L_0x1a24660; 1 drivers +v0x19ff550_0 .net *"_s43", 0 0, L_0x1a24990; 1 drivers +v0x19ff630_0 .net *"_s45", 0 0, L_0x1a24890; 1 drivers +v0x19ff710_0 .net *"_s47", 0 0, L_0x1a24b90; 1 drivers +v0x19ff7f0_0 .net *"_s49", 0 0, L_0x1a24a80; 1 drivers +v0x19ff8d0_0 .net *"_s5", 0 0, L_0x1a233c0; 1 drivers +v0x19ff9b0_0 .net *"_s51", 0 0, L_0x1a24da0; 1 drivers +v0x19ffa90_0 .net *"_s53", 0 0, L_0x1a24c80; 1 drivers +v0x19ffb70_0 .net *"_s55", 0 0, L_0x1a24fc0; 1 drivers +v0x19ffc50_0 .net *"_s57", 0 0, L_0x1a24e90; 1 drivers +v0x19ffd30_0 .net *"_s59", 0 0, L_0x1a23f30; 1 drivers +v0x19ffe10_0 .net *"_s61", 0 0, L_0x1a23e40; 1 drivers +v0x19ffef0_0 .net *"_s63", 0 0, L_0x1a255c0; 1 drivers +v0x19fffd0_0 .net *"_s7", 0 0, L_0x1a234b0; 1 drivers +v0x1a000b0_0 .net *"_s9", 0 0, L_0x1a236b0; 1 drivers +v0x1a00190_0 .net "out", 0 0, L_0x1a24190; alias, 1 drivers +v0x19ff3c0_0 .net "outInv", 0 0, L_0x1a223d0; 1 drivers +v0x1a00440_0 .net8 "zeroBit", 31 0, RS_0x7fa24fdd4a38; alias, 2 drivers +L_0x1a22550 .part RS_0x7fa24fdd4a38, 0, 1; +L_0x1a22640 .part RS_0x7fa24fdd4a38, 1, 1; +L_0x1a233c0 .part RS_0x7fa24fdd4a38, 2, 1; +L_0x1a234b0 .part RS_0x7fa24fdd4a38, 3, 1; +L_0x1a236b0 .part RS_0x7fa24fdd4a38, 4, 1; +L_0x1a23750 .part RS_0x7fa24fdd4a38, 5, 1; +L_0x1a23840 .part RS_0x7fa24fdd4a38, 6, 1; +L_0x1a23930 .part RS_0x7fa24fdd4a38, 7, 1; +L_0x1a23a70 .part RS_0x7fa24fdd4a38, 8, 1; +L_0x1a23b60 .part RS_0x7fa24fdd4a38, 9, 1; +L_0x1a23cb0 .part RS_0x7fa24fdd4a38, 10, 1; +L_0x1a23d50 .part RS_0x7fa24fdd4a38, 11, 1; +L_0x1a23610 .part RS_0x7fa24fdd4a38, 12, 1; +L_0x1a240a0 .part RS_0x7fa24fdd4a38, 13, 1; +L_0x1a24210 .part RS_0x7fa24fdd4a38, 14, 1; +L_0x1a24300 .part RS_0x7fa24fdd4a38, 15, 1; +L_0x1a24480 .part RS_0x7fa24fdd4a38, 16, 1; +L_0x1a24570 .part RS_0x7fa24fdd4a38, 17, 1; +L_0x1a24700 .part RS_0x7fa24fdd4a38, 18, 1; +L_0x1a247a0 .part RS_0x7fa24fdd4a38, 19, 1; +L_0x1a24660 .part RS_0x7fa24fdd4a38, 20, 1; +L_0x1a24990 .part RS_0x7fa24fdd4a38, 21, 1; +L_0x1a24890 .part RS_0x7fa24fdd4a38, 22, 1; +L_0x1a24b90 .part RS_0x7fa24fdd4a38, 23, 1; +L_0x1a24a80 .part RS_0x7fa24fdd4a38, 24, 1; +L_0x1a24da0 .part RS_0x7fa24fdd4a38, 25, 1; +L_0x1a24c80 .part RS_0x7fa24fdd4a38, 26, 1; +L_0x1a24fc0 .part RS_0x7fa24fdd4a38, 27, 1; +L_0x1a24e90 .part RS_0x7fa24fdd4a38, 28, 1; +L_0x1a23f30 .part RS_0x7fa24fdd4a38, 29, 1; +L_0x1a23e40 .part RS_0x7fa24fdd4a38, 30, 1; +L_0x1a255c0 .part RS_0x7fa24fdd4a38, 31, 1; + .scope S_0x18b9160; +T_0 ; + %wait E_0x18beec0; + %load/vec4 v0x19b9de0_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_0.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_0.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_0.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_0.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_0.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_0.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_0.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_0.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_0.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_0.10; +T_0.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19b9b10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9bb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9d40_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9c70_0, 0, 1; + %jmp T_0.10; +T_0.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19b9b10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9bb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9d40_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9c70_0, 0, 1; + %jmp T_0.10; +T_0.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19b9b10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9bb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9d40_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9c70_0, 0, 1; + %jmp T_0.10; +T_0.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19b9b10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9bb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9d40_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9c70_0, 0, 1; + %jmp T_0.10; +T_0.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9b10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19b9bb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9d40_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19b9c70_0, 0, 1; + %jmp T_0.10; +T_0.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9b10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19b9bb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9d40_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19b9c70_0, 0, 1; + %jmp T_0.10; +T_0.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9b10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9bb0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19b9d40_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9c70_0, 0, 1; + %jmp T_0.10; +T_0.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9b10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19b9bb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9d40_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9c70_0, 0, 1; + %jmp T_0.10; +T_0.8 ; + %load/vec4 v0x19b99e0_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_0.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_0.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_0.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_0.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_0.16; +T_0.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19b9b10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9bb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9d40_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9c70_0, 0, 1; + %jmp T_0.16; +T_0.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9b10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19b9bb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9d40_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9c70_0, 0, 1; + %jmp T_0.16; +T_0.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9b10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19b9bb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9d40_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19b9c70_0, 0, 1; + %jmp T_0.16; +T_0.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9b10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19b9bb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19b9d40_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19b9c70_0, 0, 1; + %jmp T_0.16; +T_0.16 ; + %pop/vec4 1; + %jmp T_0.10; +T_0.10 ; + %pop/vec4 1; + %jmp T_0; + .thread T_0, $push; + .scope S_0x19ba3c0; +T_1 ; + %wait E_0x18beec0; + %load/vec4 v0x19bbc90_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_1.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_1.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_1.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_1.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_1.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_1.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_1.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_1.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_1.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_1.10; +T_1.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bba10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbbf0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbb50_0, 0, 1; + %jmp T_1.10; +T_1.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bba10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbbf0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbb50_0, 0, 1; + %jmp T_1.10; +T_1.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bba10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbbf0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbb50_0, 0, 1; + %jmp T_1.10; +T_1.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bba10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbbf0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbb50_0, 0, 1; + %jmp T_1.10; +T_1.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bba10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bbab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbbf0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bbb50_0, 0, 1; + %jmp T_1.10; +T_1.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bba10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bbab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbbf0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bbb50_0, 0, 1; + %jmp T_1.10; +T_1.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bba10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbab0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bbbf0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbb50_0, 0, 1; + %jmp T_1.10; +T_1.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bba10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bbab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbbf0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbb50_0, 0, 1; + %jmp T_1.10; +T_1.8 ; + %load/vec4 v0x19bb8b0_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_1.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_1.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_1.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_1.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_1.16; +T_1.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bba10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbbf0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbb50_0, 0, 1; + %jmp T_1.16; +T_1.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bba10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bbab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbbf0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbb50_0, 0, 1; + %jmp T_1.16; +T_1.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bba10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bbab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbbf0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bbb50_0, 0, 1; + %jmp T_1.16; +T_1.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bba10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bbab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bbbf0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bbb50_0, 0, 1; + %jmp T_1.16; +T_1.16 ; + %pop/vec4 1; + %jmp T_1.10; +T_1.10 ; + %pop/vec4 1; + %jmp T_1; + .thread T_1, $push; + .scope S_0x19bc270; +T_2 ; + %wait E_0x18beec0; + %load/vec4 v0x19bdb70_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_2.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_2.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_2.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_2.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_2.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_2.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_2.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_2.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_2.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_2.10; +T_2.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bd8d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bd970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bdab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bda10_0, 0, 1; + %jmp T_2.10; +T_2.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bd8d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bd970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bdab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bda10_0, 0, 1; + %jmp T_2.10; +T_2.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bd8d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bd970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bdab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bda10_0, 0, 1; + %jmp T_2.10; +T_2.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bd8d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bd970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bdab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bda10_0, 0, 1; + %jmp T_2.10; +T_2.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bd8d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bd970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bdab0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bda10_0, 0, 1; + %jmp T_2.10; +T_2.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bd8d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bd970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bdab0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bda10_0, 0, 1; + %jmp T_2.10; +T_2.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bd8d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bd970_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bdab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bda10_0, 0, 1; + %jmp T_2.10; +T_2.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bd8d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bd970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bdab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bda10_0, 0, 1; + %jmp T_2.10; +T_2.8 ; + %load/vec4 v0x19bd7a0_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_2.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_2.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_2.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_2.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_2.16; +T_2.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bd8d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bd970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bdab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bda10_0, 0, 1; + %jmp T_2.16; +T_2.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bd8d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bd970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bdab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bda10_0, 0, 1; + %jmp T_2.16; +T_2.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bd8d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bd970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bdab0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bda10_0, 0, 1; + %jmp T_2.16; +T_2.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bd8d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bd970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bdab0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bda10_0, 0, 1; + %jmp T_2.16; +T_2.16 ; + %pop/vec4 1; + %jmp T_2.10; +T_2.10 ; + %pop/vec4 1; + %jmp T_2; + .thread T_2, $push; + .scope S_0x19be1d0; +T_3 ; + %wait E_0x18beec0; + %load/vec4 v0x19bfa10_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_3.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_3.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_3.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_3.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_3.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_3.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_3.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_3.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_3.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_3.10; +T_3.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bf770_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf810_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf950_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf8b0_0, 0, 1; + %jmp T_3.10; +T_3.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bf770_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf810_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf950_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf8b0_0, 0, 1; + %jmp T_3.10; +T_3.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bf770_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf810_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf950_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf8b0_0, 0, 1; + %jmp T_3.10; +T_3.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bf770_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf810_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf950_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf8b0_0, 0, 1; + %jmp T_3.10; +T_3.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf770_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bf810_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf950_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bf8b0_0, 0, 1; + %jmp T_3.10; +T_3.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf770_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bf810_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf950_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bf8b0_0, 0, 1; + %jmp T_3.10; +T_3.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf770_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf810_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bf950_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf8b0_0, 0, 1; + %jmp T_3.10; +T_3.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf770_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bf810_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf950_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf8b0_0, 0, 1; + %jmp T_3.10; +T_3.8 ; + %load/vec4 v0x19bf640_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_3.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_3.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_3.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_3.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_3.16; +T_3.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bf770_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf810_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf950_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf8b0_0, 0, 1; + %jmp T_3.16; +T_3.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf770_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bf810_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf950_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf8b0_0, 0, 1; + %jmp T_3.16; +T_3.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf770_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bf810_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf950_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bf8b0_0, 0, 1; + %jmp T_3.16; +T_3.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf770_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bf810_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19bf950_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19bf8b0_0, 0, 1; + %jmp T_3.16; +T_3.16 ; + %pop/vec4 1; + %jmp T_3.10; +T_3.10 ; + %pop/vec4 1; + %jmp T_3; + .thread T_3, $push; + .scope S_0x19c0020; +T_4 ; + %wait E_0x18beec0; + %load/vec4 v0x19c19b0_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_4.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_4.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_4.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_4.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_4.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_4.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_4.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_4.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_4.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_4.10; +T_4.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c1710_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c17b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c18f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c1850_0, 0, 1; + %jmp T_4.10; +T_4.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c1710_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c17b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c18f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c1850_0, 0, 1; + %jmp T_4.10; +T_4.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c1710_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c17b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c18f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c1850_0, 0, 1; + %jmp T_4.10; +T_4.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c1710_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c17b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c18f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c1850_0, 0, 1; + %jmp T_4.10; +T_4.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c1710_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c17b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c18f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c1850_0, 0, 1; + %jmp T_4.10; +T_4.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c1710_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c17b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c18f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c1850_0, 0, 1; + %jmp T_4.10; +T_4.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c1710_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c17b0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c18f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c1850_0, 0, 1; + %jmp T_4.10; +T_4.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c1710_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c17b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c18f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c1850_0, 0, 1; + %jmp T_4.10; +T_4.8 ; + %load/vec4 v0x19c1550_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_4.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_4.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_4.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_4.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_4.16; +T_4.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c1710_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c17b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c18f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c1850_0, 0, 1; + %jmp T_4.16; +T_4.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c1710_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c17b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c18f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c1850_0, 0, 1; + %jmp T_4.16; +T_4.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c1710_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c17b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c18f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c1850_0, 0, 1; + %jmp T_4.16; +T_4.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c1710_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c17b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c18f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c1850_0, 0, 1; + %jmp T_4.16; +T_4.16 ; + %pop/vec4 1; + %jmp T_4.10; +T_4.10 ; + %pop/vec4 1; + %jmp T_4; + .thread T_4, $push; + .scope S_0x19c1f60; +T_5 ; + %wait E_0x18beec0; + %load/vec4 v0x19c3800_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_5.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_5.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_5.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_5.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_5.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_5.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_5.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_5.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_5.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_5.10; +T_5.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c3560_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3740_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c36a0_0, 0, 1; + %jmp T_5.10; +T_5.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c3560_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3740_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c36a0_0, 0, 1; + %jmp T_5.10; +T_5.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c3560_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3740_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c36a0_0, 0, 1; + %jmp T_5.10; +T_5.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c3560_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3740_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c36a0_0, 0, 1; + %jmp T_5.10; +T_5.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3560_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c3600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3740_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c36a0_0, 0, 1; + %jmp T_5.10; +T_5.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3560_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c3600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3740_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c36a0_0, 0, 1; + %jmp T_5.10; +T_5.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3560_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3600_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c3740_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c36a0_0, 0, 1; + %jmp T_5.10; +T_5.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3560_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c3600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3740_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c36a0_0, 0, 1; + %jmp T_5.10; +T_5.8 ; + %load/vec4 v0x19c3430_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_5.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_5.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_5.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_5.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_5.16; +T_5.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c3560_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3740_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c36a0_0, 0, 1; + %jmp T_5.16; +T_5.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3560_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c3600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3740_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c36a0_0, 0, 1; + %jmp T_5.16; +T_5.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3560_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c3600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3740_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c36a0_0, 0, 1; + %jmp T_5.16; +T_5.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3560_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c3600_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c3740_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c36a0_0, 0, 1; + %jmp T_5.16; +T_5.16 ; + %pop/vec4 1; + %jmp T_5.10; +T_5.10 ; + %pop/vec4 1; + %jmp T_5; + .thread T_5, $push; + .scope S_0x19c3dc0; +T_6 ; + %wait E_0x18beec0; + %load/vec4 v0x19c5660_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_6.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_6.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_6.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_6.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_6.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_6.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_6.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_6.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_6.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_6.10; +T_6.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c53c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c5460_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c55a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c5500_0, 0, 1; + %jmp T_6.10; +T_6.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c53c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c5460_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c55a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c5500_0, 0, 1; + %jmp T_6.10; +T_6.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c53c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c5460_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c55a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c5500_0, 0, 1; + %jmp T_6.10; +T_6.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c53c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c5460_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c55a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c5500_0, 0, 1; + %jmp T_6.10; +T_6.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c53c0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c5460_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c55a0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c5500_0, 0, 1; + %jmp T_6.10; +T_6.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c53c0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c5460_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c55a0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c5500_0, 0, 1; + %jmp T_6.10; +T_6.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c53c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c5460_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c55a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c5500_0, 0, 1; + %jmp T_6.10; +T_6.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c53c0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c5460_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c55a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c5500_0, 0, 1; + %jmp T_6.10; +T_6.8 ; + %load/vec4 v0x19c5290_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_6.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_6.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_6.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_6.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_6.16; +T_6.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c53c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c5460_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c55a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c5500_0, 0, 1; + %jmp T_6.16; +T_6.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c53c0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c5460_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c55a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c5500_0, 0, 1; + %jmp T_6.16; +T_6.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c53c0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c5460_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c55a0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c5500_0, 0, 1; + %jmp T_6.16; +T_6.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c53c0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c5460_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c55a0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c5500_0, 0, 1; + %jmp T_6.16; +T_6.16 ; + %pop/vec4 1; + %jmp T_6.10; +T_6.10 ; + %pop/vec4 1; + %jmp T_6; + .thread T_6, $push; + .scope S_0x19c5c20; +T_7 ; + %wait E_0x18beec0; + %load/vec4 v0x19c74c0_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_7.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_7.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_7.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_7.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_7.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_7.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_7.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_7.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_7.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_7.10; +T_7.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c7220_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c72c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7360_0, 0, 1; + %jmp T_7.10; +T_7.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c7220_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c72c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7360_0, 0, 1; + %jmp T_7.10; +T_7.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c7220_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c72c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7360_0, 0, 1; + %jmp T_7.10; +T_7.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c7220_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c72c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7360_0, 0, 1; + %jmp T_7.10; +T_7.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7220_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c72c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c7360_0, 0, 1; + %jmp T_7.10; +T_7.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7220_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c72c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c7360_0, 0, 1; + %jmp T_7.10; +T_7.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7220_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c72c0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c7400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7360_0, 0, 1; + %jmp T_7.10; +T_7.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7220_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c72c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7360_0, 0, 1; + %jmp T_7.10; +T_7.8 ; + %load/vec4 v0x19c70f0_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_7.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_7.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_7.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_7.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_7.16; +T_7.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c7220_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c72c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7360_0, 0, 1; + %jmp T_7.16; +T_7.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7220_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c72c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7400_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7360_0, 0, 1; + %jmp T_7.16; +T_7.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7220_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c72c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c7360_0, 0, 1; + %jmp T_7.16; +T_7.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7220_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c72c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c7400_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c7360_0, 0, 1; + %jmp T_7.16; +T_7.16 ; + %pop/vec4 1; + %jmp T_7.10; +T_7.10 ; + %pop/vec4 1; + %jmp T_7; + .thread T_7, $push; + .scope S_0x19c7ac0; +T_8 ; + %wait E_0x18beec0; + %load/vec4 v0x19c9560_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_8.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_8.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_8.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_8.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_8.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_8.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_8.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_8.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_8.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_8.10; +T_8.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c92e0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c9380_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c94c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c9420_0, 0, 1; + %jmp T_8.10; +T_8.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c92e0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c9380_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c94c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c9420_0, 0, 1; + %jmp T_8.10; +T_8.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c92e0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c9380_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c94c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c9420_0, 0, 1; + %jmp T_8.10; +T_8.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c92e0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c9380_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c94c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c9420_0, 0, 1; + %jmp T_8.10; +T_8.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c92e0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c9380_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c94c0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c9420_0, 0, 1; + %jmp T_8.10; +T_8.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c92e0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c9380_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c94c0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c9420_0, 0, 1; + %jmp T_8.10; +T_8.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c92e0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c9380_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c94c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c9420_0, 0, 1; + %jmp T_8.10; +T_8.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c92e0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c9380_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c94c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c9420_0, 0, 1; + %jmp T_8.10; +T_8.8 ; + %load/vec4 v0x19c90a0_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_8.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_8.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_8.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_8.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_8.16; +T_8.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c92e0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c9380_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c94c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c9420_0, 0, 1; + %jmp T_8.16; +T_8.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c92e0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c9380_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c94c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c9420_0, 0, 1; + %jmp T_8.16; +T_8.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c92e0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c9380_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c94c0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c9420_0, 0, 1; + %jmp T_8.16; +T_8.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c92e0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c9380_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c94c0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c9420_0, 0, 1; + %jmp T_8.16; +T_8.16 ; + %pop/vec4 1; + %jmp T_8.10; +T_8.10 ; + %pop/vec4 1; + %jmp T_8; + .thread T_8, $push; + .scope S_0x19c9b50; +T_9 ; + %wait E_0x18beec0; + %load/vec4 v0x19cb3f0_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_9.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_9.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_9.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_9.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_9.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_9.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_9.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_9.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_9.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_9.10; +T_9.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cb150_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb1f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb330_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb290_0, 0, 1; + %jmp T_9.10; +T_9.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cb150_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb1f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb330_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb290_0, 0, 1; + %jmp T_9.10; +T_9.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cb150_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb1f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb330_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb290_0, 0, 1; + %jmp T_9.10; +T_9.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cb150_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb1f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb330_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb290_0, 0, 1; + %jmp T_9.10; +T_9.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb150_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cb1f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb330_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cb290_0, 0, 1; + %jmp T_9.10; +T_9.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb150_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cb1f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb330_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cb290_0, 0, 1; + %jmp T_9.10; +T_9.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb150_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb1f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cb330_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb290_0, 0, 1; + %jmp T_9.10; +T_9.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb150_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cb1f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb330_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb290_0, 0, 1; + %jmp T_9.10; +T_9.8 ; + %load/vec4 v0x19cb020_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_9.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_9.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_9.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_9.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_9.16; +T_9.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cb150_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb1f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb330_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb290_0, 0, 1; + %jmp T_9.16; +T_9.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb150_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cb1f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb330_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb290_0, 0, 1; + %jmp T_9.16; +T_9.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb150_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cb1f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb330_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cb290_0, 0, 1; + %jmp T_9.16; +T_9.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb150_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cb1f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cb330_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cb290_0, 0, 1; + %jmp T_9.16; +T_9.16 ; + %pop/vec4 1; + %jmp T_9.10; +T_9.10 ; + %pop/vec4 1; + %jmp T_9; + .thread T_9, $push; + .scope S_0x19cb9b0; +T_10 ; + %wait E_0x18beec0; + %load/vec4 v0x19cd250_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_10.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_10.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_10.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_10.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_10.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_10.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_10.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_10.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_10.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_10.10; +T_10.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ccfb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd050_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd190_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd0f0_0, 0, 1; + %jmp T_10.10; +T_10.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ccfb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd050_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd190_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd0f0_0, 0, 1; + %jmp T_10.10; +T_10.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ccfb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd050_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd190_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd0f0_0, 0, 1; + %jmp T_10.10; +T_10.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ccfb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd050_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd190_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd0f0_0, 0, 1; + %jmp T_10.10; +T_10.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ccfb0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cd050_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd190_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cd0f0_0, 0, 1; + %jmp T_10.10; +T_10.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ccfb0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cd050_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd190_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cd0f0_0, 0, 1; + %jmp T_10.10; +T_10.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ccfb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd050_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cd190_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd0f0_0, 0, 1; + %jmp T_10.10; +T_10.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ccfb0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cd050_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd190_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd0f0_0, 0, 1; + %jmp T_10.10; +T_10.8 ; + %load/vec4 v0x19cce80_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_10.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_10.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_10.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_10.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_10.16; +T_10.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ccfb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd050_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd190_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd0f0_0, 0, 1; + %jmp T_10.16; +T_10.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ccfb0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cd050_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd190_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd0f0_0, 0, 1; + %jmp T_10.16; +T_10.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ccfb0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cd050_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd190_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cd0f0_0, 0, 1; + %jmp T_10.16; +T_10.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ccfb0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cd050_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cd190_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cd0f0_0, 0, 1; + %jmp T_10.16; +T_10.16 ; + %pop/vec4 1; + %jmp T_10.10; +T_10.10 ; + %pop/vec4 1; + %jmp T_10; + .thread T_10, $push; + .scope S_0x19cd810; +T_11 ; + %wait E_0x18beec0; + %load/vec4 v0x19cf0b0_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_11.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_11.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_11.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_11.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_11.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_11.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_11.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_11.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_11.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_11.10; +T_11.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cee10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ceeb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ceff0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cef50_0, 0, 1; + %jmp T_11.10; +T_11.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cee10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ceeb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ceff0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cef50_0, 0, 1; + %jmp T_11.10; +T_11.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cee10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ceeb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ceff0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cef50_0, 0, 1; + %jmp T_11.10; +T_11.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cee10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ceeb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ceff0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cef50_0, 0, 1; + %jmp T_11.10; +T_11.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cee10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ceeb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ceff0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cef50_0, 0, 1; + %jmp T_11.10; +T_11.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cee10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ceeb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ceff0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cef50_0, 0, 1; + %jmp T_11.10; +T_11.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cee10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ceeb0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ceff0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cef50_0, 0, 1; + %jmp T_11.10; +T_11.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cee10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ceeb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ceff0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cef50_0, 0, 1; + %jmp T_11.10; +T_11.8 ; + %load/vec4 v0x19cece0_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_11.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_11.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_11.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_11.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_11.16; +T_11.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cee10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ceeb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ceff0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cef50_0, 0, 1; + %jmp T_11.16; +T_11.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cee10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ceeb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ceff0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cef50_0, 0, 1; + %jmp T_11.16; +T_11.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cee10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ceeb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ceff0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cef50_0, 0, 1; + %jmp T_11.16; +T_11.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19cee10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ceeb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ceff0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19cef50_0, 0, 1; + %jmp T_11.16; +T_11.16 ; + %pop/vec4 1; + %jmp T_11.10; +T_11.10 ; + %pop/vec4 1; + %jmp T_11; + .thread T_11, $push; + .scope S_0x19cf670; +T_12 ; + %wait E_0x18beec0; + %load/vec4 v0x19d0f10_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_12.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_12.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_12.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_12.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_12.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_12.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_12.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_12.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_12.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_12.10; +T_12.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d0c70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0d10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0e50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0db0_0, 0, 1; + %jmp T_12.10; +T_12.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d0c70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0d10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0e50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0db0_0, 0, 1; + %jmp T_12.10; +T_12.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d0c70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0d10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0e50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0db0_0, 0, 1; + %jmp T_12.10; +T_12.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d0c70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0d10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0e50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0db0_0, 0, 1; + %jmp T_12.10; +T_12.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0c70_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d0d10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0e50_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d0db0_0, 0, 1; + %jmp T_12.10; +T_12.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0c70_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d0d10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0e50_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d0db0_0, 0, 1; + %jmp T_12.10; +T_12.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0c70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0d10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d0e50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0db0_0, 0, 1; + %jmp T_12.10; +T_12.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0c70_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d0d10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0e50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0db0_0, 0, 1; + %jmp T_12.10; +T_12.8 ; + %load/vec4 v0x19d0b40_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_12.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_12.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_12.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_12.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_12.16; +T_12.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d0c70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0d10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0e50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0db0_0, 0, 1; + %jmp T_12.16; +T_12.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0c70_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d0d10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0e50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0db0_0, 0, 1; + %jmp T_12.16; +T_12.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0c70_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d0d10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0e50_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d0db0_0, 0, 1; + %jmp T_12.16; +T_12.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0c70_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d0d10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d0e50_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d0db0_0, 0, 1; + %jmp T_12.16; +T_12.16 ; + %pop/vec4 1; + %jmp T_12.10; +T_12.10 ; + %pop/vec4 1; + %jmp T_12; + .thread T_12, $push; + .scope S_0x19d14d0; +T_13 ; + %wait E_0x18beec0; + %load/vec4 v0x19d2d70_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_13.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_13.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_13.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_13.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_13.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_13.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_13.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_13.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_13.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_13.10; +T_13.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d2ad0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2b70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2cb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2c10_0, 0, 1; + %jmp T_13.10; +T_13.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d2ad0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2b70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2cb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2c10_0, 0, 1; + %jmp T_13.10; +T_13.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d2ad0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2b70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2cb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2c10_0, 0, 1; + %jmp T_13.10; +T_13.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d2ad0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2b70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2cb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2c10_0, 0, 1; + %jmp T_13.10; +T_13.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2ad0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d2b70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2cb0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d2c10_0, 0, 1; + %jmp T_13.10; +T_13.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2ad0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d2b70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2cb0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d2c10_0, 0, 1; + %jmp T_13.10; +T_13.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2ad0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2b70_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d2cb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2c10_0, 0, 1; + %jmp T_13.10; +T_13.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2ad0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d2b70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2cb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2c10_0, 0, 1; + %jmp T_13.10; +T_13.8 ; + %load/vec4 v0x19d29a0_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_13.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_13.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_13.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_13.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_13.16; +T_13.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d2ad0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2b70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2cb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2c10_0, 0, 1; + %jmp T_13.16; +T_13.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2ad0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d2b70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2cb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2c10_0, 0, 1; + %jmp T_13.16; +T_13.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2ad0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d2b70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2cb0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d2c10_0, 0, 1; + %jmp T_13.16; +T_13.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2ad0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d2b70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d2cb0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d2c10_0, 0, 1; + %jmp T_13.16; +T_13.16 ; + %pop/vec4 1; + %jmp T_13.10; +T_13.10 ; + %pop/vec4 1; + %jmp T_13; + .thread T_13, $push; + .scope S_0x19d3330; +T_14 ; + %wait E_0x18beec0; + %load/vec4 v0x19d4bd0_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_14.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_14.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_14.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_14.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_14.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_14.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_14.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_14.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_14.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_14.10; +T_14.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d4930_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d49d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4b10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4a70_0, 0, 1; + %jmp T_14.10; +T_14.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d4930_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d49d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4b10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4a70_0, 0, 1; + %jmp T_14.10; +T_14.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d4930_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d49d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4b10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4a70_0, 0, 1; + %jmp T_14.10; +T_14.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d4930_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d49d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4b10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4a70_0, 0, 1; + %jmp T_14.10; +T_14.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4930_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d49d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4b10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d4a70_0, 0, 1; + %jmp T_14.10; +T_14.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4930_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d49d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4b10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d4a70_0, 0, 1; + %jmp T_14.10; +T_14.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4930_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d49d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d4b10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4a70_0, 0, 1; + %jmp T_14.10; +T_14.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4930_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d49d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4b10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4a70_0, 0, 1; + %jmp T_14.10; +T_14.8 ; + %load/vec4 v0x19d4800_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_14.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_14.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_14.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_14.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_14.16; +T_14.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d4930_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d49d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4b10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4a70_0, 0, 1; + %jmp T_14.16; +T_14.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4930_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d49d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4b10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4a70_0, 0, 1; + %jmp T_14.16; +T_14.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4930_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d49d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4b10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d4a70_0, 0, 1; + %jmp T_14.16; +T_14.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4930_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d49d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d4b10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d4a70_0, 0, 1; + %jmp T_14.16; +T_14.16 ; + %pop/vec4 1; + %jmp T_14.10; +T_14.10 ; + %pop/vec4 1; + %jmp T_14; + .thread T_14, $push; + .scope S_0x19d5190; +T_15 ; + %wait E_0x18beec0; + %load/vec4 v0x19d6a30_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_15.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_15.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_15.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_15.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_15.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_15.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_15.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_15.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_15.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_15.10; +T_15.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d6790_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6830_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d68d0_0, 0, 1; + %jmp T_15.10; +T_15.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d6790_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6830_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d68d0_0, 0, 1; + %jmp T_15.10; +T_15.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d6790_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6830_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d68d0_0, 0, 1; + %jmp T_15.10; +T_15.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d6790_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6830_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d68d0_0, 0, 1; + %jmp T_15.10; +T_15.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6790_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d6830_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6970_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d68d0_0, 0, 1; + %jmp T_15.10; +T_15.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6790_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d6830_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6970_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d68d0_0, 0, 1; + %jmp T_15.10; +T_15.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6790_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6830_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d6970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d68d0_0, 0, 1; + %jmp T_15.10; +T_15.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6790_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d6830_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d68d0_0, 0, 1; + %jmp T_15.10; +T_15.8 ; + %load/vec4 v0x19d6660_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_15.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_15.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_15.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_15.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_15.16; +T_15.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d6790_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6830_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d68d0_0, 0, 1; + %jmp T_15.16; +T_15.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6790_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d6830_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d68d0_0, 0, 1; + %jmp T_15.16; +T_15.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6790_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d6830_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6970_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d68d0_0, 0, 1; + %jmp T_15.16; +T_15.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6790_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d6830_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d6970_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d68d0_0, 0, 1; + %jmp T_15.16; +T_15.16 ; + %pop/vec4 1; + %jmp T_15.10; +T_15.10 ; + %pop/vec4 1; + %jmp T_15; + .thread T_15, $push; + .scope S_0x19d7090; +T_16 ; + %wait E_0x18beec0; + %load/vec4 v0x19d8c70_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_16.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_16.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_16.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_16.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_16.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_16.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_16.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_16.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_16.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_16.10; +T_16.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c91d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8a90_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8bd0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8b30_0, 0, 1; + %jmp T_16.10; +T_16.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c91d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8a90_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8bd0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8b30_0, 0, 1; + %jmp T_16.10; +T_16.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c91d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8a90_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8bd0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8b30_0, 0, 1; + %jmp T_16.10; +T_16.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c91d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8a90_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8bd0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8b30_0, 0, 1; + %jmp T_16.10; +T_16.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c91d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8a90_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8bd0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8b30_0, 0, 1; + %jmp T_16.10; +T_16.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c91d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8a90_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8bd0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8b30_0, 0, 1; + %jmp T_16.10; +T_16.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c91d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8a90_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8bd0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8b30_0, 0, 1; + %jmp T_16.10; +T_16.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c91d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8a90_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8bd0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8b30_0, 0, 1; + %jmp T_16.10; +T_16.8 ; + %load/vec4 v0x19d8750_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_16.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_16.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_16.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_16.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_16.16; +T_16.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19c91d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8a90_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8bd0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8b30_0, 0, 1; + %jmp T_16.16; +T_16.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c91d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8a90_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8bd0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8b30_0, 0, 1; + %jmp T_16.16; +T_16.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c91d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8a90_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8bd0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8b30_0, 0, 1; + %jmp T_16.16; +T_16.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19c91d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8a90_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8bd0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8b30_0, 0, 1; + %jmp T_16.16; +T_16.16 ; + %pop/vec4 1; + %jmp T_16.10; +T_16.10 ; + %pop/vec4 1; + %jmp T_16; + .thread T_16, $push; + .scope S_0x19d9300; +T_17 ; + %wait E_0x18beec0; + %load/vec4 v0x19daba0_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_17.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_17.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_17.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_17.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_17.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_17.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_17.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_17.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_17.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_17.10; +T_17.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19da900_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19da9a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19daae0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19daa40_0, 0, 1; + %jmp T_17.10; +T_17.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19da900_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19da9a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19daae0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19daa40_0, 0, 1; + %jmp T_17.10; +T_17.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19da900_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19da9a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19daae0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19daa40_0, 0, 1; + %jmp T_17.10; +T_17.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19da900_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19da9a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19daae0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19daa40_0, 0, 1; + %jmp T_17.10; +T_17.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19da900_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19da9a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19daae0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19daa40_0, 0, 1; + %jmp T_17.10; +T_17.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19da900_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19da9a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19daae0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19daa40_0, 0, 1; + %jmp T_17.10; +T_17.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19da900_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19da9a0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19daae0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19daa40_0, 0, 1; + %jmp T_17.10; +T_17.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19da900_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19da9a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19daae0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19daa40_0, 0, 1; + %jmp T_17.10; +T_17.8 ; + %load/vec4 v0x19da7d0_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_17.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_17.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_17.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_17.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_17.16; +T_17.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19da900_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19da9a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19daae0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19daa40_0, 0, 1; + %jmp T_17.16; +T_17.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19da900_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19da9a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19daae0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19daa40_0, 0, 1; + %jmp T_17.16; +T_17.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19da900_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19da9a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19daae0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19daa40_0, 0, 1; + %jmp T_17.16; +T_17.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19da900_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19da9a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19daae0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19daa40_0, 0, 1; + %jmp T_17.16; +T_17.16 ; + %pop/vec4 1; + %jmp T_17.10; +T_17.10 ; + %pop/vec4 1; + %jmp T_17; + .thread T_17, $push; + .scope S_0x19db160; +T_18 ; + %wait E_0x18beec0; + %load/vec4 v0x19dca00_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_18.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_18.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_18.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_18.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_18.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_18.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_18.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_18.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_18.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_18.10; +T_18.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19dc760_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc800_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc940_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc8a0_0, 0, 1; + %jmp T_18.10; +T_18.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19dc760_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc800_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc940_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc8a0_0, 0, 1; + %jmp T_18.10; +T_18.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19dc760_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc800_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc940_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc8a0_0, 0, 1; + %jmp T_18.10; +T_18.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19dc760_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc800_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc940_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc8a0_0, 0, 1; + %jmp T_18.10; +T_18.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc760_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19dc800_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc940_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19dc8a0_0, 0, 1; + %jmp T_18.10; +T_18.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc760_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19dc800_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc940_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19dc8a0_0, 0, 1; + %jmp T_18.10; +T_18.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc760_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc800_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19dc940_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc8a0_0, 0, 1; + %jmp T_18.10; +T_18.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc760_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19dc800_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc940_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc8a0_0, 0, 1; + %jmp T_18.10; +T_18.8 ; + %load/vec4 v0x19dc630_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_18.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_18.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_18.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_18.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_18.16; +T_18.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19dc760_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc800_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc940_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc8a0_0, 0, 1; + %jmp T_18.16; +T_18.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc760_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19dc800_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc940_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc8a0_0, 0, 1; + %jmp T_18.16; +T_18.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc760_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19dc800_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc940_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19dc8a0_0, 0, 1; + %jmp T_18.16; +T_18.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc760_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19dc800_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19dc940_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19dc8a0_0, 0, 1; + %jmp T_18.16; +T_18.16 ; + %pop/vec4 1; + %jmp T_18.10; +T_18.10 ; + %pop/vec4 1; + %jmp T_18; + .thread T_18, $push; + .scope S_0x19dcfc0; +T_19 ; + %wait E_0x18beec0; + %load/vec4 v0x19de830_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_19.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_19.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_19.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_19.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_19.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_19.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_19.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_19.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_19.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_19.10; +T_19.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19de5b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de650_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de790_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de6f0_0, 0, 1; + %jmp T_19.10; +T_19.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19de5b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de650_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de790_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de6f0_0, 0, 1; + %jmp T_19.10; +T_19.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19de5b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de650_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de790_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de6f0_0, 0, 1; + %jmp T_19.10; +T_19.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19de5b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de650_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de790_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de6f0_0, 0, 1; + %jmp T_19.10; +T_19.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de5b0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19de650_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de790_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19de6f0_0, 0, 1; + %jmp T_19.10; +T_19.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de5b0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19de650_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de790_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19de6f0_0, 0, 1; + %jmp T_19.10; +T_19.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de5b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de650_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19de790_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de6f0_0, 0, 1; + %jmp T_19.10; +T_19.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de5b0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19de650_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de790_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de6f0_0, 0, 1; + %jmp T_19.10; +T_19.8 ; + %load/vec4 v0x19de480_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_19.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_19.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_19.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_19.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_19.16; +T_19.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19de5b0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de650_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de790_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de6f0_0, 0, 1; + %jmp T_19.16; +T_19.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de5b0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19de650_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de790_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de6f0_0, 0, 1; + %jmp T_19.16; +T_19.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de5b0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19de650_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de790_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19de6f0_0, 0, 1; + %jmp T_19.16; +T_19.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de5b0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19de650_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19de790_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19de6f0_0, 0, 1; + %jmp T_19.16; +T_19.16 ; + %pop/vec4 1; + %jmp T_19.10; +T_19.10 ; + %pop/vec4 1; + %jmp T_19; + .thread T_19, $push; + .scope S_0x19dedf0; +T_20 ; + %wait E_0x18beec0; + %load/vec4 v0x19e06d0_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_20.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_20.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_20.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_20.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_20.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_20.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_20.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_20.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_20.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_20.10; +T_20.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e0430_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e04d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0610_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0570_0, 0, 1; + %jmp T_20.10; +T_20.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e0430_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e04d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0610_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0570_0, 0, 1; + %jmp T_20.10; +T_20.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e0430_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e04d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0610_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0570_0, 0, 1; + %jmp T_20.10; +T_20.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e0430_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e04d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0610_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0570_0, 0, 1; + %jmp T_20.10; +T_20.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0430_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e04d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0610_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e0570_0, 0, 1; + %jmp T_20.10; +T_20.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0430_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e04d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0610_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e0570_0, 0, 1; + %jmp T_20.10; +T_20.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0430_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e04d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e0610_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0570_0, 0, 1; + %jmp T_20.10; +T_20.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0430_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e04d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0610_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0570_0, 0, 1; + %jmp T_20.10; +T_20.8 ; + %load/vec4 v0x19e0300_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_20.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_20.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_20.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_20.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_20.16; +T_20.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e0430_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e04d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0610_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0570_0, 0, 1; + %jmp T_20.16; +T_20.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0430_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e04d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0610_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0570_0, 0, 1; + %jmp T_20.16; +T_20.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0430_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e04d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0610_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e0570_0, 0, 1; + %jmp T_20.16; +T_20.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0430_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e04d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e0610_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e0570_0, 0, 1; + %jmp T_20.16; +T_20.16 ; + %pop/vec4 1; + %jmp T_20.10; +T_20.10 ; + %pop/vec4 1; + %jmp T_20; + .thread T_20, $push; + .scope S_0x19e0c90; +T_21 ; + %wait E_0x18beec0; + %load/vec4 v0x19e2530_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_21.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_21.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_21.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_21.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_21.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_21.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_21.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_21.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_21.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_21.10; +T_21.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e2290_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2330_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2470_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e23d0_0, 0, 1; + %jmp T_21.10; +T_21.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e2290_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2330_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2470_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e23d0_0, 0, 1; + %jmp T_21.10; +T_21.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e2290_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2330_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2470_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e23d0_0, 0, 1; + %jmp T_21.10; +T_21.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e2290_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2330_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2470_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e23d0_0, 0, 1; + %jmp T_21.10; +T_21.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2290_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e2330_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2470_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e23d0_0, 0, 1; + %jmp T_21.10; +T_21.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2290_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e2330_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2470_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e23d0_0, 0, 1; + %jmp T_21.10; +T_21.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2290_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2330_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e2470_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e23d0_0, 0, 1; + %jmp T_21.10; +T_21.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2290_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e2330_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2470_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e23d0_0, 0, 1; + %jmp T_21.10; +T_21.8 ; + %load/vec4 v0x19e2160_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_21.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_21.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_21.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_21.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_21.16; +T_21.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e2290_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2330_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2470_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e23d0_0, 0, 1; + %jmp T_21.16; +T_21.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2290_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e2330_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2470_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e23d0_0, 0, 1; + %jmp T_21.16; +T_21.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2290_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e2330_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2470_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e23d0_0, 0, 1; + %jmp T_21.16; +T_21.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2290_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e2330_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e2470_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e23d0_0, 0, 1; + %jmp T_21.16; +T_21.16 ; + %pop/vec4 1; + %jmp T_21.10; +T_21.10 ; + %pop/vec4 1; + %jmp T_21; + .thread T_21, $push; + .scope S_0x19e2af0; +T_22 ; + %wait E_0x18beec0; + %load/vec4 v0x19e4390_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_22.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_22.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_22.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_22.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_22.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_22.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_22.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_22.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_22.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_22.10; +T_22.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e40f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e4190_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e42d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e4230_0, 0, 1; + %jmp T_22.10; +T_22.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e40f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e4190_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e42d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e4230_0, 0, 1; + %jmp T_22.10; +T_22.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e40f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e4190_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e42d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e4230_0, 0, 1; + %jmp T_22.10; +T_22.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e40f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e4190_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e42d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e4230_0, 0, 1; + %jmp T_22.10; +T_22.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e40f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e4190_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e42d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e4230_0, 0, 1; + %jmp T_22.10; +T_22.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e40f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e4190_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e42d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e4230_0, 0, 1; + %jmp T_22.10; +T_22.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e40f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e4190_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e42d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e4230_0, 0, 1; + %jmp T_22.10; +T_22.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e40f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e4190_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e42d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e4230_0, 0, 1; + %jmp T_22.10; +T_22.8 ; + %load/vec4 v0x19e3fc0_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_22.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_22.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_22.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_22.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_22.16; +T_22.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e40f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e4190_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e42d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e4230_0, 0, 1; + %jmp T_22.16; +T_22.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e40f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e4190_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e42d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e4230_0, 0, 1; + %jmp T_22.16; +T_22.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e40f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e4190_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e42d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e4230_0, 0, 1; + %jmp T_22.16; +T_22.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e40f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e4190_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e42d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e4230_0, 0, 1; + %jmp T_22.16; +T_22.16 ; + %pop/vec4 1; + %jmp T_22.10; +T_22.10 ; + %pop/vec4 1; + %jmp T_22; + .thread T_22, $push; + .scope S_0x19e4950; +T_23 ; + %wait E_0x18beec0; + %load/vec4 v0x19e61f0_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_23.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_23.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_23.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_23.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_23.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_23.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_23.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_23.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_23.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_23.10; +T_23.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e5f50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e5ff0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e6130_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e6090_0, 0, 1; + %jmp T_23.10; +T_23.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e5f50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e5ff0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e6130_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e6090_0, 0, 1; + %jmp T_23.10; +T_23.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e5f50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e5ff0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e6130_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e6090_0, 0, 1; + %jmp T_23.10; +T_23.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e5f50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e5ff0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e6130_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e6090_0, 0, 1; + %jmp T_23.10; +T_23.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e5f50_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e5ff0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e6130_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e6090_0, 0, 1; + %jmp T_23.10; +T_23.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e5f50_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e5ff0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e6130_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e6090_0, 0, 1; + %jmp T_23.10; +T_23.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e5f50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e5ff0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e6130_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e6090_0, 0, 1; + %jmp T_23.10; +T_23.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e5f50_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e5ff0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e6130_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e6090_0, 0, 1; + %jmp T_23.10; +T_23.8 ; + %load/vec4 v0x19e5e20_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_23.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_23.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_23.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_23.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_23.16; +T_23.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e5f50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e5ff0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e6130_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e6090_0, 0, 1; + %jmp T_23.16; +T_23.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e5f50_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e5ff0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e6130_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e6090_0, 0, 1; + %jmp T_23.16; +T_23.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e5f50_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e5ff0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e6130_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e6090_0, 0, 1; + %jmp T_23.16; +T_23.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e5f50_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e5ff0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e6130_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e6090_0, 0, 1; + %jmp T_23.16; +T_23.16 ; + %pop/vec4 1; + %jmp T_23.10; +T_23.10 ; + %pop/vec4 1; + %jmp T_23; + .thread T_23, $push; + .scope S_0x19e67b0; +T_24 ; + %wait E_0x18beec0; + %load/vec4 v0x19e8050_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_24.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_24.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_24.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_24.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_24.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_24.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_24.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_24.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_24.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_24.10; +T_24.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e7db0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7e50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7f90_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7ef0_0, 0, 1; + %jmp T_24.10; +T_24.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e7db0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7e50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7f90_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7ef0_0, 0, 1; + %jmp T_24.10; +T_24.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e7db0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7e50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7f90_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7ef0_0, 0, 1; + %jmp T_24.10; +T_24.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e7db0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7e50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7f90_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7ef0_0, 0, 1; + %jmp T_24.10; +T_24.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7db0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e7e50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7f90_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e7ef0_0, 0, 1; + %jmp T_24.10; +T_24.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7db0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e7e50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7f90_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e7ef0_0, 0, 1; + %jmp T_24.10; +T_24.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7db0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7e50_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e7f90_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7ef0_0, 0, 1; + %jmp T_24.10; +T_24.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7db0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e7e50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7f90_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7ef0_0, 0, 1; + %jmp T_24.10; +T_24.8 ; + %load/vec4 v0x19e7c80_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_24.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_24.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_24.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_24.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_24.16; +T_24.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e7db0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7e50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7f90_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7ef0_0, 0, 1; + %jmp T_24.16; +T_24.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7db0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e7e50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7f90_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7ef0_0, 0, 1; + %jmp T_24.16; +T_24.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7db0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e7e50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7f90_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e7ef0_0, 0, 1; + %jmp T_24.16; +T_24.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7db0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e7e50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e7f90_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e7ef0_0, 0, 1; + %jmp T_24.16; +T_24.16 ; + %pop/vec4 1; + %jmp T_24.10; +T_24.10 ; + %pop/vec4 1; + %jmp T_24; + .thread T_24, $push; + .scope S_0x19e8610; +T_25 ; + %wait E_0x18beec0; + %load/vec4 v0x19e9eb0_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_25.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_25.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_25.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_25.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_25.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_25.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_25.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_25.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_25.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_25.10; +T_25.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e9c10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9cb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9df0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9d50_0, 0, 1; + %jmp T_25.10; +T_25.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e9c10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9cb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9df0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9d50_0, 0, 1; + %jmp T_25.10; +T_25.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e9c10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9cb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9df0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9d50_0, 0, 1; + %jmp T_25.10; +T_25.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e9c10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9cb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9df0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9d50_0, 0, 1; + %jmp T_25.10; +T_25.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9c10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e9cb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9df0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e9d50_0, 0, 1; + %jmp T_25.10; +T_25.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9c10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e9cb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9df0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e9d50_0, 0, 1; + %jmp T_25.10; +T_25.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9c10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9cb0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e9df0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9d50_0, 0, 1; + %jmp T_25.10; +T_25.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9c10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e9cb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9df0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9d50_0, 0, 1; + %jmp T_25.10; +T_25.8 ; + %load/vec4 v0x19e9ae0_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_25.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_25.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_25.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_25.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_25.16; +T_25.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e9c10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9cb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9df0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9d50_0, 0, 1; + %jmp T_25.16; +T_25.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9c10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e9cb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9df0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9d50_0, 0, 1; + %jmp T_25.16; +T_25.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9c10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e9cb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9df0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e9d50_0, 0, 1; + %jmp T_25.16; +T_25.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9c10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e9cb0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19e9df0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19e9d50_0, 0, 1; + %jmp T_25.16; +T_25.16 ; + %pop/vec4 1; + %jmp T_25.10; +T_25.10 ; + %pop/vec4 1; + %jmp T_25; + .thread T_25, $push; + .scope S_0x19ea470; +T_26 ; + %wait E_0x18beec0; + %load/vec4 v0x19ebd10_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_26.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_26.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_26.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_26.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_26.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_26.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_26.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_26.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_26.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_26.10; +T_26.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19eba70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebb10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebc50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebbb0_0, 0, 1; + %jmp T_26.10; +T_26.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19eba70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebb10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebc50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebbb0_0, 0, 1; + %jmp T_26.10; +T_26.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19eba70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebb10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebc50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebbb0_0, 0, 1; + %jmp T_26.10; +T_26.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19eba70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebb10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebc50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebbb0_0, 0, 1; + %jmp T_26.10; +T_26.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19eba70_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ebb10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebc50_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ebbb0_0, 0, 1; + %jmp T_26.10; +T_26.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19eba70_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ebb10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebc50_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ebbb0_0, 0, 1; + %jmp T_26.10; +T_26.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19eba70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebb10_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ebc50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebbb0_0, 0, 1; + %jmp T_26.10; +T_26.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19eba70_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ebb10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebc50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebbb0_0, 0, 1; + %jmp T_26.10; +T_26.8 ; + %load/vec4 v0x19eb940_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_26.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_26.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_26.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_26.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_26.16; +T_26.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19eba70_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebb10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebc50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebbb0_0, 0, 1; + %jmp T_26.16; +T_26.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19eba70_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ebb10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebc50_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebbb0_0, 0, 1; + %jmp T_26.16; +T_26.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19eba70_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ebb10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebc50_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ebbb0_0, 0, 1; + %jmp T_26.16; +T_26.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19eba70_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ebb10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ebc50_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ebbb0_0, 0, 1; + %jmp T_26.16; +T_26.16 ; + %pop/vec4 1; + %jmp T_26.10; +T_26.10 ; + %pop/vec4 1; + %jmp T_26; + .thread T_26, $push; + .scope S_0x19ec2d0; +T_27 ; + %wait E_0x18beec0; + %load/vec4 v0x19edb70_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_27.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_27.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_27.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_27.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_27.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_27.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_27.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_27.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_27.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_27.10; +T_27.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ed8d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ed970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19edab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19eda10_0, 0, 1; + %jmp T_27.10; +T_27.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ed8d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ed970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19edab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19eda10_0, 0, 1; + %jmp T_27.10; +T_27.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ed8d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ed970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19edab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19eda10_0, 0, 1; + %jmp T_27.10; +T_27.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ed8d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ed970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19edab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19eda10_0, 0, 1; + %jmp T_27.10; +T_27.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ed8d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ed970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19edab0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19eda10_0, 0, 1; + %jmp T_27.10; +T_27.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ed8d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ed970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19edab0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19eda10_0, 0, 1; + %jmp T_27.10; +T_27.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ed8d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ed970_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19edab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19eda10_0, 0, 1; + %jmp T_27.10; +T_27.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ed8d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ed970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19edab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19eda10_0, 0, 1; + %jmp T_27.10; +T_27.8 ; + %load/vec4 v0x19ed7a0_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_27.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_27.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_27.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_27.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_27.16; +T_27.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ed8d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ed970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19edab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19eda10_0, 0, 1; + %jmp T_27.16; +T_27.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ed8d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ed970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19edab0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19eda10_0, 0, 1; + %jmp T_27.16; +T_27.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ed8d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ed970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19edab0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19eda10_0, 0, 1; + %jmp T_27.16; +T_27.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ed8d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ed970_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19edab0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19eda10_0, 0, 1; + %jmp T_27.16; +T_27.16 ; + %pop/vec4 1; + %jmp T_27.10; +T_27.10 ; + %pop/vec4 1; + %jmp T_27; + .thread T_27, $push; + .scope S_0x19ee130; +T_28 ; + %wait E_0x18beec0; + %load/vec4 v0x19ef9d0_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_28.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_28.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_28.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_28.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_28.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_28.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_28.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_28.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_28.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_28.10; +T_28.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ef730_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef7d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef910_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef870_0, 0, 1; + %jmp T_28.10; +T_28.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ef730_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef7d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef910_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef870_0, 0, 1; + %jmp T_28.10; +T_28.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ef730_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef7d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef910_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef870_0, 0, 1; + %jmp T_28.10; +T_28.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ef730_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef7d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef910_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef870_0, 0, 1; + %jmp T_28.10; +T_28.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef730_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ef7d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef910_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ef870_0, 0, 1; + %jmp T_28.10; +T_28.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef730_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ef7d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef910_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ef870_0, 0, 1; + %jmp T_28.10; +T_28.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef730_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef7d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ef910_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef870_0, 0, 1; + %jmp T_28.10; +T_28.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef730_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ef7d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef910_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef870_0, 0, 1; + %jmp T_28.10; +T_28.8 ; + %load/vec4 v0x19ef600_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_28.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_28.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_28.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_28.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_28.16; +T_28.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ef730_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef7d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef910_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef870_0, 0, 1; + %jmp T_28.16; +T_28.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef730_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ef7d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef910_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef870_0, 0, 1; + %jmp T_28.16; +T_28.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef730_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ef7d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef910_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ef870_0, 0, 1; + %jmp T_28.16; +T_28.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef730_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ef7d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19ef910_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19ef870_0, 0, 1; + %jmp T_28.16; +T_28.16 ; + %pop/vec4 1; + %jmp T_28.10; +T_28.10 ; + %pop/vec4 1; + %jmp T_28; + .thread T_28, $push; + .scope S_0x19eff90; +T_29 ; + %wait E_0x18beec0; + %load/vec4 v0x19f1830_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_29.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_29.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_29.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_29.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_29.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_29.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_29.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_29.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_29.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_29.10; +T_29.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f1590_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1630_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1770_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f16d0_0, 0, 1; + %jmp T_29.10; +T_29.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f1590_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1630_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1770_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f16d0_0, 0, 1; + %jmp T_29.10; +T_29.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f1590_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1630_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1770_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f16d0_0, 0, 1; + %jmp T_29.10; +T_29.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f1590_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1630_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1770_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f16d0_0, 0, 1; + %jmp T_29.10; +T_29.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1590_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f1630_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1770_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f16d0_0, 0, 1; + %jmp T_29.10; +T_29.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1590_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f1630_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1770_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f16d0_0, 0, 1; + %jmp T_29.10; +T_29.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1590_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1630_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f1770_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f16d0_0, 0, 1; + %jmp T_29.10; +T_29.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1590_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f1630_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1770_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f16d0_0, 0, 1; + %jmp T_29.10; +T_29.8 ; + %load/vec4 v0x19f1460_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_29.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_29.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_29.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_29.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_29.16; +T_29.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f1590_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1630_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1770_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f16d0_0, 0, 1; + %jmp T_29.16; +T_29.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1590_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f1630_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1770_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f16d0_0, 0, 1; + %jmp T_29.16; +T_29.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1590_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f1630_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1770_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f16d0_0, 0, 1; + %jmp T_29.16; +T_29.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1590_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f1630_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f1770_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f16d0_0, 0, 1; + %jmp T_29.16; +T_29.16 ; + %pop/vec4 1; + %jmp T_29.10; +T_29.10 ; + %pop/vec4 1; + %jmp T_29; + .thread T_29, $push; + .scope S_0x19f1df0; +T_30 ; + %wait E_0x18beec0; + %load/vec4 v0x19f3690_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_30.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_30.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_30.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_30.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_30.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_30.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_30.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_30.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_30.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_30.10; +T_30.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f33f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f3490_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f35d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f3530_0, 0, 1; + %jmp T_30.10; +T_30.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f33f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f3490_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f35d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f3530_0, 0, 1; + %jmp T_30.10; +T_30.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f33f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f3490_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f35d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f3530_0, 0, 1; + %jmp T_30.10; +T_30.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f33f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f3490_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f35d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f3530_0, 0, 1; + %jmp T_30.10; +T_30.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f33f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f3490_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f35d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f3530_0, 0, 1; + %jmp T_30.10; +T_30.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f33f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f3490_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f35d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f3530_0, 0, 1; + %jmp T_30.10; +T_30.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f33f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f3490_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f35d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f3530_0, 0, 1; + %jmp T_30.10; +T_30.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f33f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f3490_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f35d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f3530_0, 0, 1; + %jmp T_30.10; +T_30.8 ; + %load/vec4 v0x19f32c0_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_30.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_30.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_30.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_30.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_30.16; +T_30.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f33f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f3490_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f35d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f3530_0, 0, 1; + %jmp T_30.16; +T_30.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f33f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f3490_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f35d0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f3530_0, 0, 1; + %jmp T_30.16; +T_30.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f33f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f3490_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f35d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f3530_0, 0, 1; + %jmp T_30.16; +T_30.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f33f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f3490_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f35d0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f3530_0, 0, 1; + %jmp T_30.16; +T_30.16 ; + %pop/vec4 1; + %jmp T_30.10; +T_30.10 ; + %pop/vec4 1; + %jmp T_30; + .thread T_30, $push; + .scope S_0x19f3c50; +T_31 ; + %wait E_0x18beec0; + %load/vec4 v0x19f54f0_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_31.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_31.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_31.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_31.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_31.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_31.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_31.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_31.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_31.8, 6; + %vpi_call 3 69 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_31.10; +T_31.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f5250_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f52f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5430_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5390_0, 0, 1; + %jmp T_31.10; +T_31.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f5250_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f52f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5430_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5390_0, 0, 1; + %jmp T_31.10; +T_31.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f5250_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f52f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5430_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5390_0, 0, 1; + %jmp T_31.10; +T_31.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f5250_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f52f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5430_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5390_0, 0, 1; + %jmp T_31.10; +T_31.4 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5250_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f52f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5430_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f5390_0, 0, 1; + %jmp T_31.10; +T_31.5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5250_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f52f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5430_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f5390_0, 0, 1; + %jmp T_31.10; +T_31.6 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5250_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f52f0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f5430_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5390_0, 0, 1; + %jmp T_31.10; +T_31.7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5250_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f52f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5430_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5390_0, 0, 1; + %jmp T_31.10; +T_31.8 ; + %load/vec4 v0x19f5120_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_31.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_31.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_31.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_31.14, 6; + %vpi_call 3 66 "$display", "Error in ALUBitSlice: Invalid funct" {0 0 0}; + %jmp T_31.16; +T_31.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f5250_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f52f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5430_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5390_0, 0, 1; + %jmp T_31.16; +T_31.12 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5250_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f52f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5430_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5390_0, 0, 1; + %jmp T_31.16; +T_31.13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5250_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f52f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5430_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f5390_0, 0, 1; + %jmp T_31.16; +T_31.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5250_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f52f0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19f5430_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19f5390_0, 0, 1; + %jmp T_31.16; +T_31.16 ; + %pop/vec4 1; + %jmp T_31.10; +T_31.10 ; + %pop/vec4 1; + %jmp T_31; + .thread T_31, $push; + .scope S_0x18c67f0; +T_32 ; + %wait E_0x18beec0; + %load/vec4 v0x1a03240_0; + %dup/vec4; + %pushi/vec4 35, 0, 6; + %cmp/u; + %jmp/1 T_32.0, 6; + %dup/vec4; + %pushi/vec4 43, 0, 6; + %cmp/u; + %jmp/1 T_32.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 6; + %cmp/u; + %jmp/1 T_32.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 6; + %cmp/u; + %jmp/1 T_32.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 6; + %cmp/u; + %jmp/1 T_32.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 6; + %cmp/u; + %jmp/1 T_32.5, 6; + %dup/vec4; + %pushi/vec4 14, 0, 6; + %cmp/u; + %jmp/1 T_32.6, 6; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_32.7, 6; + %dup/vec4; + %pushi/vec4 0, 0, 6; + %cmp/u; + %jmp/1 T_32.8, 6; + %vpi_call 3 202 "$display", "Error in ALU: Invalid opcode" {0 0 0}; + %jmp T_32.10; +T_32.0 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8960_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x1a03060_0, 0, 1; + %jmp T_32.10; +T_32.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8960_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x1a03060_0, 0, 1; + %jmp T_32.10; +T_32.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8960_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x1a03060_0, 0, 1; + %jmp T_32.10; +T_32.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8960_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x1a03060_0, 0, 1; + %jmp T_32.10; +T_32.4 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8960_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x1a03060_0, 0, 1; + %jmp T_32.10; +T_32.5 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8960_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x1a03060_0, 0, 1; + %jmp T_32.10; +T_32.6 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8960_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x1a03060_0, 0, 1; + %jmp T_32.10; +T_32.7 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8960_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x1a03060_0, 0, 1; + %jmp T_32.10; +T_32.8 ; + %load/vec4 v0x1a02b90_0; + %dup/vec4; + %pushi/vec4 8, 0, 6; + %cmp/u; + %jmp/1 T_32.11, 6; + %dup/vec4; + %pushi/vec4 32, 0, 6; + %cmp/u; + %jmp/1 T_32.12, 6; + %dup/vec4; + %pushi/vec4 34, 0, 6; + %cmp/u; + %jmp/1 T_32.13, 6; + %dup/vec4; + %pushi/vec4 42, 0, 6; + %cmp/u; + %jmp/1 T_32.14, 6; + %vpi_call 3 198 "$display", "Error in ALU: Invalid funct" {0 0 0}; + %jmp T_32.16; +T_32.11 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8960_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x1a03060_0, 0, 1; + %jmp T_32.16; +T_32.12 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8960_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x1a03060_0, 0, 1; + %jmp T_32.16; +T_32.13 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x19d8960_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x1a03060_0, 0, 1; + %jmp T_32.16; +T_32.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x19d8960_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x1a03060_0, 0, 1; + %jmp T_32.16; +T_32.16 ; + %pop/vec4 1; + %jmp T_32.10; +T_32.10 ; + %pop/vec4 1; + %jmp T_32; + .thread T_32, $push; + .scope S_0x189e4c0; +T_33 ; + %vpi_call 2 19 "$display", "TESTING BASIC GATES" {0 0 0}; + %pushi/vec4 14, 0, 6; + %store/vec4 v0x1a03c10_0, 0, 6; + %pushi/vec4 8, 0, 6; + %store/vec4 v0x1a03b70_0, 0, 6; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 6, 0, 32; + %jmp/0xz T_33.0, 4; + %vpi_call 2 24 "$display", "XOR Test Failed - res: %b%b%b%b", &PV, &PV, &PV, &PV {0 0 0}; +T_33.0 ; + %vpi_call 2 26 "$display", "TESTING ADD" {0 0 0}; + %pushi/vec4 8, 0, 6; + %store/vec4 v0x1a03c10_0, 0, 6; + %pushi/vec4 8, 0, 6; + %store/vec4 v0x1a03b70_0, 0, 6; + %pushi/vec4 7000, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 14000, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 21000, 0, 32; + %jmp/0xz T_33.2, 4; + %vpi_call 2 30 "$display", "p + p = p TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.2 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.4, 4; + %vpi_call 2 31 "$display", "p + p = p OVERFLOW FAILED" {0 0 0}; +T_33.4 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.6, 4; + %vpi_call 2 32 "$display", "p + p = p CARRYOUT FAILED" {0 0 0}; +T_33.6 ; + %pushi/vec4 2147483647, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 14000, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 2147497647, 0, 32; + %jmp/0xz T_33.8, 4; + %vpi_call 2 34 "$display", "p + p = n TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.8 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.10, 4; + %vpi_call 2 35 "$display", "p + p = n OVERFLOW FAILED" {0 0 0}; +T_33.10 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.12, 4; + %vpi_call 2 36 "$display", "p + p = n CARRYOUT FAILED" {0 0 0}; +T_33.12 ; + %load/vec4 v0x1a04050_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.14, 4; + %vpi_call 2 37 "$display", "ZERO FAILED - was not 0 part 1" {0 0 0}; +T_33.14 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 87000, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 87000, 0, 32; + %jmp/0xz T_33.16, 4; + %vpi_call 2 39 "$display", "0 + p = p TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.16 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.18, 4; + %vpi_call 2 40 "$display", "0 + p = p OVERFLOW FAILED" {0 0 0}; +T_33.18 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.20, 4; + %vpi_call 2 41 "$display", "0 + p = p CARRYOUT FAILED" {0 0 0}; +T_33.20 ; + %load/vec4 v0x1a04050_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.22, 4; + %vpi_call 2 42 "$display", "ZERO FAILED - was not 0 part 2" {0 0 0}; +T_33.22 ; + %pushi/vec4 3657483652, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 2997483652, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 2360000008, 0, 32; + %jmp/0xz T_33.24, 4; + %vpi_call 2 44 "$display", "n + n = n TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.24 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.26, 4; + %vpi_call 2 45 "$display", "n + n = n OVERFLOW FAILED" {0 0 0}; +T_33.26 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.28, 4; + %vpi_call 2 46 "$display", "n + n = n CARRYOUT FAILED" {0 0 0}; +T_33.28 ; + %load/vec4 v0x1a04050_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.30, 4; + %vpi_call 2 47 "$display", "ZERO FAILED - was not 0 part 3" {0 0 0}; +T_33.30 ; + %pushi/vec4 0, 0, 6; + %store/vec4 v0x1a03c10_0, 0, 6; + %pushi/vec4 32, 0, 6; + %store/vec4 v0x1a03b70_0, 0, 6; + %pushi/vec4 2147483652, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 2147483652, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 8, 0, 32; + %jmp/0xz T_33.32, 4; + %vpi_call 2 52 "$display", "n + n = p TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.32 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.34, 4; + %vpi_call 2 53 "$display", "n + n = p OVERFLOW FAILED" {0 0 0}; +T_33.34 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.36, 4; + %vpi_call 2 54 "$display", "n + n = p CARRYOUT FAILED" {0 0 0}; +T_33.36 ; + %load/vec4 v0x1a04050_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.38, 4; + %vpi_call 2 55 "$display", "ZERO FAILED - was not 0 part 4" {0 0 0}; +T_33.38 ; + %pushi/vec4 3657483652, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 637483644, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.40, 4; + %vpi_call 2 57 "$display", "n + p = 0 TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.40 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.42, 4; + %vpi_call 2 58 "$display", "n + p = 0 OVERFLOW FAILED" {0 0 0}; +T_33.42 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.44, 4; + %vpi_call 2 59 "$display", "n + p = 0 CARRYOUT FAILED" {0 0 0}; +T_33.44 ; + %load/vec4 v0x1a04050_0; + %pad/u 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.46, 4; + %vpi_call 2 60 "$display", "ZERO FAILED - was 0" {0 0 0}; +T_33.46 ; + %pushi/vec4 3657483652, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 637483645, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.48, 4; + %vpi_call 2 62 "$display", "n + p = p TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.48 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.50, 4; + %vpi_call 2 63 "$display", "n + p = p OVERFLOW FAILED" {0 0 0}; +T_33.50 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.52, 4; + %vpi_call 2 64 "$display", "n + p = p CARRYOUT FAILED" {0 0 0}; +T_33.52 ; + %load/vec4 v0x1a04050_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.54, 4; + %vpi_call 2 65 "$display", "ZERO FAILED - was not 0 part 5" {0 0 0}; +T_33.54 ; + %pushi/vec4 3657483652, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 637483643, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 4294967295, 0, 32; + %jmp/0xz T_33.56, 4; + %vpi_call 2 67 "$display", "n + p = n TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.56 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.58, 4; + %vpi_call 2 68 "$display", "n + p = n OVERFLOW FAILED" {0 0 0}; +T_33.58 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.60, 4; + %vpi_call 2 69 "$display", "n + p = n CARRYOUT FAILED" {0 0 0}; +T_33.60 ; + %vpi_call 2 72 "$display", "TESTING SUBTRACT" {0 0 0}; + %pushi/vec4 0, 0, 6; + %store/vec4 v0x1a03c10_0, 0, 6; + %pushi/vec4 34, 0, 6; + %store/vec4 v0x1a03b70_0, 0, 6; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 637483644, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 3657483652, 0, 32; + %jmp/0xz T_33.62, 4; + %vpi_call 2 76 "$display", "0 - p = n TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.62 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.64, 4; + %vpi_call 2 77 "$display", "0 - p = n OVERFLOW FAILED" {0 0 0}; +T_33.64 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.66, 4; + %vpi_call 2 78 "$display", "0 - p = n CARRYOUT FAILED" {0 0 0}; +T_33.66 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 3657483652, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 637483644, 0, 32; + %jmp/0xz T_33.68, 4; + %vpi_call 2 80 "$display", "0 - n = p TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.68 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.70, 4; + %vpi_call 2 81 "$display", "0 - n = p OVERFLOW FAILED" {0 0 0}; +T_33.70 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.72, 4; + %vpi_call 2 82 "$display", "0 - n = p CARRYOUT FAILED" {0 0 0}; +T_33.72 ; + %pushi/vec4 3657483652, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 3657483652, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.74, 4; + %vpi_call 2 84 "$display", "n - n = 0 TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.74 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.76, 4; + %vpi_call 2 85 "$display", "n - n = 0 OVERFLOW FAILED" {0 0 0}; +T_33.76 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.78, 4; + %vpi_call 2 86 "$display", "n - n = 0 CARRYOUT FAILED" {0 0 0}; +T_33.78 ; + %load/vec4 v0x1a04050_0; + %pad/u 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.80, 4; + %vpi_call 2 87 "$display", "ZERO FAILED - was 0 part 1" {0 0 0}; +T_33.80 ; + %pushi/vec4 4, 0, 6; + %store/vec4 v0x1a03c10_0, 0, 6; + %pushi/vec4 8, 0, 6; + %store/vec4 v0x1a03b70_0, 0, 6; + %pushi/vec4 637483644, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 637483644, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.82, 4; + %vpi_call 2 92 "$display", "p - p = 0 TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.82 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.84, 4; + %vpi_call 2 93 "$display", "p - p = 0 OVERFLOW FAILED" {0 0 0}; +T_33.84 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.86, 4; + %vpi_call 2 94 "$display", "p - p = 0 CARRYOUT FAILED" {0 0 0}; +T_33.86 ; + %load/vec4 v0x1a04050_0; + %pad/u 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.88, 4; + %vpi_call 2 95 "$display", "ZERO FAILED - was 0 part 2" {0 0 0}; +T_33.88 ; + %pushi/vec4 436258181, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 236258181, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 200000000, 0, 32; + %jmp/0xz T_33.90, 4; + %vpi_call 2 97 "$display", "p - p = p TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.90 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.92, 4; + %vpi_call 2 98 "$display", "p - p = p OVERFLOW FAILED" {0 0 0}; +T_33.92 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.94, 4; + %vpi_call 2 99 "$display", "p - p = p CARRYOUT FAILED" {0 0 0}; +T_33.94 ; + %load/vec4 v0x1a04050_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.96, 4; + %vpi_call 2 100 "$display", "ZERO FAILED - was not 0" {0 0 0}; +T_33.96 ; + %pushi/vec4 436258181, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 2013265920, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 2717959557, 0, 32; + %jmp/0xz T_33.98, 4; + %vpi_call 2 102 "$display", "p - p = n TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.98 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.100, 4; + %vpi_call 2 103 "$display", "p - p = n OVERFLOW FAILED" {0 0 0}; +T_33.100 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.102, 4; + %vpi_call 2 104 "$display", "p - p = n CARRYOUT FAILED" {0 0 0}; +T_33.102 ; + %pushi/vec4 3657483652, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 3657483653, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 4294967295, 0, 32; + %jmp/0xz T_33.104, 4; + %vpi_call 2 106 "$display", "n - n = n TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.104 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.106, 4; + %vpi_call 2 107 "$display", "n - n = n OVERFLOW FAILED" {0 0 0}; +T_33.106 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.108, 4; + %vpi_call 2 108 "$display", "n - n = n CARRYOUT FAILED" {0 0 0}; +T_33.108 ; + %pushi/vec4 5, 0, 6; + %store/vec4 v0x1a03c10_0, 0, 6; + %pushi/vec4 8, 0, 6; + %store/vec4 v0x1a03b70_0, 0, 6; + %pushi/vec4 3657483652, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 3657483651, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.110, 4; + %vpi_call 2 113 "$display", "n - n = p TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.110 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.112, 4; + %vpi_call 2 114 "$display", "n - n = p OVERFLOW FAILED" {0 0 0}; +T_33.112 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.114, 4; + %vpi_call 2 115 "$display", "n - n = p CARRYOUT FAILED" {0 0 0}; +T_33.114 ; + %pushi/vec4 7000, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 4294953296, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 21000, 0, 32; + %jmp/0xz T_33.116, 4; + %vpi_call 2 117 "$display", "p - n = p TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.116 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.118, 4; + %vpi_call 2 118 "$display", "p - n = p OVERFLOW FAILED" {0 0 0}; +T_33.118 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.120, 4; + %vpi_call 2 119 "$display", "p - n = p CARRYOUT FAILED" {0 0 0}; +T_33.120 ; + %pushi/vec4 2147483647, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 4294953296, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 2147497647, 0, 32; + %jmp/0xz T_33.122, 4; + %vpi_call 2 121 "$display", "p - n = n TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.122 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.124, 4; + %vpi_call 2 122 "$display", "p - n = n OVERFLOW FAILED" {0 0 0}; +T_33.124 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.126, 4; + %vpi_call 2 123 "$display", "p - n = n CARRYOUT FAILED" {0 0 0}; +T_33.126 ; + %pushi/vec4 3657483652, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 1297483644, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 2360000008, 0, 32; + %jmp/0xz T_33.128, 4; + %vpi_call 2 125 "$display", "n - p = n TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.128 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.130, 4; + %vpi_call 2 126 "$display", "n - p = n OVERFLOW FAILED" {0 0 0}; +T_33.130 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.132, 4; + %vpi_call 2 127 "$display", "n - p = n CARRYOUT FAILED" {0 0 0}; +T_33.132 ; + %pushi/vec4 2147483652, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 2147483644, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 8, 0, 32; + %jmp/0xz T_33.134, 4; + %vpi_call 2 129 "$display", "n - p = p TEST FAILED - res: %d", v0x1a03f60_0 {0 0 0}; +T_33.134 ; + %load/vec4 v0x1a03e70_0; + %pad/u 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.136, 4; + %vpi_call 2 130 "$display", "n - p = p OVERFLOW FAILED" {0 0 0}; +T_33.136 ; + %load/vec4 v0x1a03a80_0; + %pad/u 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.138, 4; + %vpi_call 2 131 "$display", "n - p = p CARRYOUT FAILED" {0 0 0}; +T_33.138 ; + %vpi_call 2 133 "$display", "TESTING SLT" {0 0 0}; + %pushi/vec4 0, 0, 6; + %store/vec4 v0x1a03c10_0, 0, 6; + %pushi/vec4 42, 0, 6; + %store/vec4 v0x1a03b70_0, 0, 6; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 1000, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.140, 4; + %vpi_call 2 137 "$display", "0 < p TEST FAILED - res: %b", v0x1a03f60_0 {0 0 0}; +T_33.140 ; + %pushi/vec4 1, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.142, 4; + %vpi_call 2 139 "$display", "p not < 0 TEST FAILED - res: %b", v0x1a03f60_0 {0 0 0}; +T_33.142 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 3657483652, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.144, 4; + %vpi_call 2 141 "$display", "0 not < n TEST FAILED - res: %b", v0x1a03f60_0 {0 0 0}; +T_33.144 ; + %pushi/vec4 3657483652, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.146, 4; + %vpi_call 2 143 "$display", "n < 0 TEST FAILED - res: %b %b", v0x1a03f60_0, v0x1a03e70_0 {0 0 0}; +T_33.146 ; + %pushi/vec4 1000, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 2000, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.148, 4; + %vpi_call 2 145 "$display", "p < p TEST FAILED" {0 0 0}; +T_33.148 ; + %pushi/vec4 2000, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 1000, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.150, 4; + %vpi_call 2 147 "$display", "p not < p TEST FAILED" {0 0 0}; +T_33.150 ; + %pushi/vec4 2360000008, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 3657483652, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.152, 4; + %vpi_call 2 149 "$display", "n < n TEST FAILED" {0 0 0}; +T_33.152 ; + %pushi/vec4 3657483652, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 2360000008, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.154, 4; + %vpi_call 2 151 "$display", "n not < n TEST FAILED %b", v0x1a03f60_0 {0 0 0}; +T_33.154 ; + %pushi/vec4 3657483652, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 1000, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 10000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.156, 4; + %vpi_call 2 153 "$display", "n < p TEST FAILED - res: %b, %b", v0x1a03f60_0, v0x1a03e70_0 {0 0 0}; +T_33.156 ; + %load/vec4 v0x1a04050_0; + %pad/u 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.158, 4; + %vpi_call 2 154 "$display", "ZERO FAILED - was not 1" {0 0 0}; +T_33.158 ; + %pushi/vec4 1000, 0, 32; + %store/vec4 v0x1a03ce0_0, 0, 32; + %pushi/vec4 3657483652, 0, 32; + %store/vec4 v0x1a03dd0_0, 0, 32; + %delay 4000000, 0; + %load/vec4 v0x1a03f60_0; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_33.160, 4; + %vpi_call 2 156 "$display", "p not < n TEST FAILED" {0 0 0}; +T_33.160 ; + %load/vec4 v0x1a04050_0; + %pad/u 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_33.162, 4; + %vpi_call 2 157 "$display", "ZERO FAILED - was 0 %b %b ", v0x1a04050_0, v0x1a03f60_0 {0 0 0}; +T_33.162 ; + %vpi_call 2 159 "$display", "Testing Finished" {0 0 0}; + %end; + .thread T_33; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "alu.t.v"; + "./alu.v"; diff --git a/asmtest/ellis_pfenninger/README.md b/asmtest/ellis_pfenninger/README.md new file mode 100644 index 0000000..aea803b --- /dev/null +++ b/asmtest/ellis_pfenninger/README.md @@ -0,0 +1,5 @@ +# divide.asm +This test divides the number stored in $a0 (default 52) by the value stored in $a1 (default 5). It stores the quotient in $v0 (default 10) and the remainder in $v1 (default 2). + +# verybasicstacktest.asm +This is a very basic test to test pushing and popping items onto/from the stack. It stores two values into $t0 and $t1 (default 0x42 and 0x17, respectively), pushes them onto the stack, does a quick XORI test to simulate a separate function running (stores 0xAA in $t4, then XORs it with 0xFF, resulting in 0x55 stored in $t4), then pops the two values off of the stack into $t2 and $t3 (which should end up as 0x42 and 0x17, respectively). \ No newline at end of file diff --git a/asmtest/ellis_pfenninger/divide.asm b/asmtest/ellis_pfenninger/divide.asm new file mode 100644 index 0000000..cbdd8b2 --- /dev/null +++ b/asmtest/ellis_pfenninger/divide.asm @@ -0,0 +1,39 @@ +# Division (inefficiently) +# Divides the number in $a0 by $a1 +# Stores quotient in $v0, remainder in $v1 + +# Initialize values with functions we have implemented +addi $a0 $zero 52 +addi $a1 $zero 5 + +jal divide +j end + +divide: +# Check that $a0 isn't less than $a1 +slt $t2 $a0 $a1 +bne $t2 $zero except_end + +#Initialize registers +add $t0 $zero $a0 +addi $t1 $zero 0 + +loop: +sub $t0 $t0 $a1 +addi $t1 $t1 1 + +#If running subtraction isn't done, loop +slt $t2 $t0 $a1 +beq $t2 $zero loop + +add $v0 $zero $t1 +add $v1 $zero $t0 +jr $ra + +except_end: +addi $v0 $zero 0 +add $v1 $zero $a0 +jr $ra + +end: +j end \ No newline at end of file diff --git a/asmtest/ellis_pfenninger/verybasicstacktest b/asmtest/ellis_pfenninger/verybasicstacktest new file mode 100644 index 0000000..6b96355 --- /dev/null +++ b/asmtest/ellis_pfenninger/verybasicstacktest @@ -0,0 +1,23 @@ +# Initialize stack pointer +addi $sp $zero 0x3ffc + +# Initialize values to save and load +addi $t0 $zero 0x42 +addi $t1 $zero 0x17 + +# Push two values onto the stack +addi $sp $sp -8 +sw $t0 4($sp) +sw $t1 0($sp) + +# Do a real quick validation of XORI to simulate a function +addi $t4 $zero 0xAA +xori $t4 $t4 0xFF #$t4 should change to 55 + +# Pop values back off into different registers +lw $t2 4($sp) +lw $t3 0($sp) +addi $sp $sp 8 + +end: +j end #jump trap to halt execution \ No newline at end of file diff --git a/datamemory.v b/datamemory.v new file mode 100644 index 0000000..18a7dcf --- /dev/null +++ b/datamemory.v @@ -0,0 +1,33 @@ +// Reused given code from Lab 2 + +//------------------------------------------------------------------------ +// Data Memory +// Positive edge triggered +// dataOut always has the value mem[address] +// If writeEnable is true, writes dataIn to mem[address] +//------------------------------------------------------------------------ + +module datamemory +#( + parameter addresswidth = 7, + parameter depth = 2**addresswidth, + parameter width = 32 +) +( + input clk, + output reg [width-1:0] dataOut, + input [addresswidth-1:0] address, + input writeEnable, + input [width-1:0] dataIn +); + + + reg [width-1:0] memory [depth-1:0]; + + always @(posedge clk) begin + if(writeEnable) + memory[address] <= dataIn; + dataOut <= memory[address]; + end + +endmodule diff --git a/file.dat b/file.dat new file mode 100644 index 0000000..3f38521 --- /dev/null +++ b/file.dat @@ -0,0 +1,1024 @@ +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/full_tests.sh b/full_tests.sh new file mode 100755 index 0000000..01b17b6 --- /dev/null +++ b/full_tests.sh @@ -0,0 +1,26 @@ +iverilog -o adder adder.t.v +iverilog -o alu alu.t.v +iverilog -o CPU CPU.t.v +iverilog -o memReg memReg.t.v +iverilog -o mux mux.t.v +iverilog -o regfile regfile.t.v +iverilog -o regWrLUT regWrLUT.t.v +iverilog -o signExtender signExtender.t.v + +./adder +./alu +./memReg +./mux +./regfile +./regWrLUT +./signExtender +./CPU +mem_text_fn=myprog.text +dump_fn=divide.vcd + +rm adder +rm alu +rm memReg +rm mux +rm regfile +rm regWrLUT +rm signExtender +rm CPU \ No newline at end of file diff --git a/memReg.t.v b/memReg.t.v new file mode 100644 index 0000000..b925ca7 --- /dev/null +++ b/memReg.t.v @@ -0,0 +1,88 @@ +`include "memReg.v" +`timescale 1 ns / 1 ps + +module testmemReg (); + reg clk; + reg[6:0] addressRW, addressRead, addressWrite; + reg[31:0] dataInRW, dataInWrite; + reg writeEnableRW, writeEnableWrite; + wire[31:0] dataOutRW, dataOutRead; + + memoryReg memReg(.clk(clk), + .dataOutRW(dataOutRW), + .dataOutRead(dataOutRead), + .addressRW(addressRW), + .addressRead(addressRead), + .addressWrite(addressWrite), + .writeEnableRW(writeEnableRW), + .writeEnableWrite(writeEnableWrite), + .dataInRW(dataInRW), + .dataInWrite(dataInWrite)); + + initial begin + $display("Starting memReg tests."); + + $display("Writing to two memory addresses"); + writeEnableWrite = 0; + addressRead = 9'b0000000; + dataInWrite = 31'b0; + + writeEnableRW=1; + addressRW=9'b1111111; + dataInRW=32'b11110000; + clk=0; #10 + clk=1; #10 //addressRW 1111111 should be written to + addressRW=9'b0000000; + dataInRW=32'b00001111; + clk=0; #10 + clk=1; #10 //addressRW 0000000 should now be written to + + $display("Reading from the two memory addresses"); //should not depend on the clock + writeEnableRW=0; + addressRW=9'b1111111; #10 + if (dataOutRW !== 32'b11110000) $display("Read test 1 failed - %b", dataOutRW); + addressRW=9'b0000000; #10 + if (dataOutRW !== 32'b00001111) $display("Read test 2 failed - %b", dataOutRW); + + $display("Writing to two memory addressRWes - with write disabled"); + writeEnableRW=0; + addressRW=9'b1111111; + dataInRW=32'b00001111; + clk=0; #10 + clk=1; #10 //addressRW 1111111 should be written to + addressRW=9'b0000000; + dataInRW=32'b11110000; + clk=0; #10 + clk=1; #10 //addressRW 0000000 should now be written to + + $display("Reading from the two memory addressRWes - make sure they didn't change"); //should not depend on the clock + writeEnableRW=0; + addressRW=9'b1111111; #10 + if (dataOutRW !== 32'b11110000) $display("Read test 1 failed - %b", dataOutRW); + addressRW=9'b0000000; #10 + if (dataOutRW !== 32'b00001111) $display("Read test 2 failed - %b", dataOutRW); + + + $display("Writing to two memory addresses at the same time"); + writeEnableRW = 1; + writeEnableWrite = 1; + dataInRW = 32'b1; + dataInWrite = 32'b10; + addressRW = 9'b1100000; + addressWrite = 9'b0011111; + clk = 0; #10 + clk = 1; #10 //register should now be written to + + $display("Reading from two memory addresses at the same time"); + writeEnableRW = 0; + writeEnableWrite = 0; + addressRW = 9'b0011111; + addressRead = 9'b1100000; #10 + if (dataOutRW !== 32'b10) $display("Read from two at once test 1 failed - %b", dataOutRW); + if (dataOutRead !== 32'b1) $display("Read from two at once test 2 failed - %b", dataOutRead); + + $display("memReg Testing Finished"); + + end + +endmodule // testmemReg \ No newline at end of file diff --git a/memReg.v b/memReg.v new file mode 100644 index 0000000..a6f05cd --- /dev/null +++ b/memReg.v @@ -0,0 +1,30 @@ +`timescale 1 ns / 1 ps + +module memoryReg +#( + parameter addresswidth = 12, + parameter depth = 4096, + parameter width = 32 +) +( + input clk, + output [width-1:0] dataOutRW, dataOutRead, + input [addresswidth-1:0] addressRW, addressRead, addressWrite, + input writeEnableRW, writeEnableWrite, + input [width-1:0] dataInRW, dataInWrite +); + + + reg [width-1:0] memory [depth-1:0]; + + always @(posedge clk) begin + if(writeEnableRW) + memory[addressRW] <= dataInRW; + if(writeEnableWrite) + memory[addressWrite] <= dataInWrite; + end + + assign dataOutRW = memory[addressRW]; + assign dataOutRead = memory[addressRead]; + +endmodule \ No newline at end of file diff --git a/mux.t.v b/mux.t.v new file mode 100644 index 0000000..dad580e --- /dev/null +++ b/mux.t.v @@ -0,0 +1,37 @@ +`include "mux.v" +`define DELAY 500 +`define WIDTH 32 +`define HALFWIDTH 16 + +module testMux(); + reg[`WIDTH-1:0] a; + reg[`WIDTH-1:0] b; + reg select; + wire[`WIDTH-1:0] out; + + mux #(`WIDTH) dut( + .input0(a), + .input1(b), + .sel(select), + .out(out)); + +initial begin + $display("Starting Mux Tests."); + + a = {`HALFWIDTH'b1111, `HALFWIDTH'b0}; + b = {`HALFWIDTH'b0, `HALFWIDTH'b1111};; + select = 0; + #`DELAY; + if(out !== a) + $display("Mux test failed; output != a when sel=0"); + + select = 1; + #`DELAY; + if(out !== b) + $display("Mux test failed; output != b when sel=1"); + + $display("Mux tests finished!"); + $display(); + +end // initial +endmodule // testMux \ No newline at end of file diff --git a/mux.v b/mux.v new file mode 100644 index 0000000..ee4f513 --- /dev/null +++ b/mux.v @@ -0,0 +1,15 @@ +module mux +#( + parameter data_width = 32 +) +( +output[data_width-1:0] out, +input sel, +input[data_width-1:0] input0, input1 +); + + wire[data_width-1:0] mux[1:0]; // Create a 2D array of wires + assign mux[0] = input0; // Connect the sources of the array + assign mux[1] = input1; + assign out = mux[sel]; // Connect the output of the array +endmodule \ No newline at end of file diff --git a/mux.vcd b/mux.vcd new file mode 100644 index 0000000..aa5fc34 --- /dev/null +++ b/mux.vcd @@ -0,0 +1,37 @@ +$date + Sat Nov 3 19:48:25 2018 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module testMux $end +$var wire 32 ! out [31:0] $end +$var reg 32 " a [31:0] $end +$var reg 32 # b [31:0] $end +$var reg 1 $ select $end +$scope module dut $end +$var wire 32 % input0 [31:0] $end +$var wire 32 & input1 [31:0] $end +$var wire 32 ' out [31:0] $end +$var wire 1 $ sel $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b11110000000000000000 ' +b1111 & +b11110000000000000000 % +0$ +b1111 # +b11110000000000000000 " +b11110000000000000000 ! +$end +#500 +b1111 ! +b1111 ' +1$ +#1000 diff --git a/myprog.text b/myprog.text new file mode 100644 index 0000000..a6f47c6 --- /dev/null +++ b/myprog.text @@ -0,0 +1,44 @@ +201d3ffc +20040004 +2005000a +0c000005 +0800002b +23bdfff4 +afbf0008 +afb00004 +afb10000 +00058820 +0c000015 +00028020 +00112020 +0c000015 +00028820 +02111020 +8fb10000 +8fb00004 +8fbf0008 +23bd000c +03e00008 +20010000 +14240002 +00001020 +03e00008 +20010001 +14240002 +00041020 +03e00008 +23bdfff8 +afbf0004 +afb00000 +00048020 +2084ffff +0c000015 +2204fffe +00028020 +0c000015 +00501020 +8fbf0004 +8fb00000 +23bd0008 +03e00008 +0800002b diff --git a/regWrLUT.t.v b/regWrLUT.t.v new file mode 100644 index 0000000..6af382f --- /dev/null +++ b/regWrLUT.t.v @@ -0,0 +1,94 @@ +`include "regWrLUT.v" + +module testRegWrLUT(); + reg[5:0] opcode; + reg[5:0] funct; + wire regwr; + + regWrLUT dut( + .opcode(opcode), + .funct(funct), + .regwr(regwr) + ); + + initial begin + // $dumpfile("LUT.vcd"); + // $dumpvars(); + $display("Starting RegWrLUT testing."); + + opcode = `LW_OP; + funct = 6'b111111; + #5; + if (regwr !== 1) + $display("Error in regWrLUT test: LW not asserting regwr."); + + opcode = `SW_OP; + funct = 6'b111111; + #5; + if (regwr !== 0) + $display("Error in regWrLUT test: SW asserting regwr."); + + opcode = `J_OP; + funct = 6'b111111; + #5; + if (regwr !== 0) + $display("Error in regWrLUT test: J asserting regwr."); + + opcode = `JAL_OP; + funct = `JR_FUNCT; + #5; + if (regwr !== 1) + $display("Error in regWrLUT test: JAL not asserting regwr."); + + opcode = `BEQ_OP; + funct = `JR_FUNCT; + #5; + if (regwr !== 0) + $display("Error in regWrLUT test: BEQ asserting regwr."); + + opcode = `BNE_OP; + funct = `JR_FUNCT; + #5; + if (regwr !== 0) + $display("Error in regWrLUT test: BNE asserting regwr."); + + opcode = `XORI_OP; + funct = `JR_FUNCT; + #5; + if (regwr !== 1) + $display("Error in regWrLUT test: XORI not asserting regwr."); + + opcode = `ADDI_OP; + funct = `JR_FUNCT; + #5; + if (regwr !== 1) + $display("Error in regWrLUT test: ADDI not asserting regwr."); + + opcode = `RTYPE_OP; + funct = `JR_FUNCT; + #5; + if (regwr !== 0) + $display("Error in regWrLUT test: JR asserting regwr."); + + opcode = `RTYPE_OP; + funct = `ADD_FUNCT; + #5; + if (regwr !== 1) + $display("Error in regWrLUT test: ADD not asserting regwr."); + + opcode = `RTYPE_OP; + funct = `SUB_FUNCT; + #5; + if (regwr !== 1) + $display("Error in regWrLUT test: SUB not asserting regwr."); + + opcode = `RTYPE_OP; + funct = `SLT_FUNCT; + #5; + if (regwr !== 1) + $display("Error in regWrLUT test: SLT not asserting regwr."); + + #5; + $display("regWrLUT tests finished!"); + end // initial +endmodule // testRegWrLUT \ No newline at end of file diff --git a/regWrLUT.v b/regWrLUT.v new file mode 100644 index 0000000..1e56797 --- /dev/null +++ b/regWrLUT.v @@ -0,0 +1,58 @@ +`define LW_OP 6'b100011 +`define SW_OP 6'b101011 +`define J_OP 6'b000010 +`define JAL_OP 6'b000011 +`define BEQ_OP 6'b000100 +`define BNE_OP 6'b000101 +`define XORI_OP 6'b001110 +`define ADDI_OP 6'b001000 +`define RTYPE_OP 6'b000000 + +`define JR_FUNCT 6'b001000 +`define ADD_FUNCT 6'b100000 +`define SUB_FUNCT 6'b100010 +`define SLT_FUNCT 6'b101010 + +module regWrLUT +/* +LUT module to determine RegWr +Inputs: +opcode: The first 6 bits of the binary command, which partly determines which operation the CPU will perform +funct; The last 6 bits of the binary command, which determines the res of the operation the CPU will perform + +Outpus: +regwr: Whether to enable register write for this cycle +*/ +( +output reg regwr, +input[5:0] opcode, +input[5:0] funct +); + +always @(opcode or funct) begin + case (opcode) + `LW_OP: regwr=1; //LW + `SW_OP: regwr=0; //SW + `J_OP: regwr=0; //J + `JAL_OP: regwr=1; //JAL + `BEQ_OP: regwr=0; //BEQ + `BNE_OP: regwr=0; //BNE + `XORI_OP: regwr=1; //XORI + `ADDI_OP: regwr=1; //ADDI + + `RTYPE_OP: begin + case (funct) + `JR_FUNCT: regwr = 0; //JR + `ADD_FUNCT: regwr = 1; //ADD + `SUB_FUNCT: regwr = 1; //SUB + `SLT_FUNCT: regwr = 1; //SLT + default: $display("Error in regWrLUT: Invalid funct"); + endcase + end + + default: $display("Error in regWrLUT: Invalid opcode"); + + + endcase +end +endmodule \ No newline at end of file diff --git a/regfile.t.v b/regfile.t.v new file mode 100644 index 0000000..559b391 --- /dev/null +++ b/regfile.t.v @@ -0,0 +1,229 @@ +//------------------------------------------------------------------------------ +// Test harness validates hw4testbench by connecting it to various functional +// or broken register files, and verifying that it correctly identifies each +//------------------------------------------------------------------------------ + +`include "regfile.v" + +module hw4testbenchharness(); + + wire[31:0] ReadData1; // Data from first register read + wire[31:0] ReadData2; // Data from second register read + wire[31:0] WriteData; // Data to write to register + wire[4:0] ReadRegister1; // Address of first register to read + wire[4:0] ReadRegister2; // Address of second register to read + wire[4:0] WriteRegister; // Address of register to write + wire RegWrite; // Enable writing of register when High + wire Clk; // Clock (Positive Edge Triggered) + + reg begintest; // Set High to begin testing register file + wire endtest; // Set High to signal test completion + wire dutpassed; // Indicates whether register file passed tests + + // Instantiate the register file being tested. DUT = Device Under Test + regfile DUT + ( + .ReadData1(ReadData1), + .ReadData2(ReadData2), + .WriteData(WriteData), + .ReadRegister1(ReadRegister1), + .ReadRegister2(ReadRegister2), + .WriteRegister(WriteRegister), + .wEnable(RegWrite), + .Clk(Clk) + ); + + // Instantiate test bench to test the DUT + hw4testbench tester + ( + .begintest(begintest), + .endtest(endtest), + .dutpassed(dutpassed), + .ReadData1(ReadData1), + .ReadData2(ReadData2), + .WriteData(WriteData), + .ReadRegister1(ReadRegister1), + .ReadRegister2(ReadRegister2), + .WriteRegister(WriteRegister), + .RegWrite(RegWrite), + .Clk(Clk) + ); + + // Test harness asserts 'begintest' for 1000 time steps, starting at time 10 + initial begin + $display("Starting Regfile Tests."); + begintest=0; + #10; + begintest=1; + #1000; + end + + // Display test results ('dutpassed' signal) once 'endtest' goes high + always @(posedge endtest) begin + $display("Regfile tests passed?: %b", dutpassed); + $display(); + end + +endmodule + + +//------------------------------------------------------------------------------ +// Your HW4 test bench +// Generates signals to drive register file and passes them back up one +// layer to the test harness. This lets us plug in various working and +// broken register files to test. +// +// Once 'begintest' is asserted, begin testing the register file. +// Once your test is conclusive, set 'dutpassed' appropriately and then +// raise 'endtest'. +//------------------------------------------------------------------------------ + +module hw4testbench +( +// Test bench driver signal connections +input begintest, // Triggers start of testing +output reg endtest, // Raise once test completes +output reg dutpassed, // Signal test result + +// Register File DUT connections +input[31:0] ReadData1, +input[31:0] ReadData2, +output reg[31:0] WriteData, +output reg[4:0] ReadRegister1, +output reg[4:0] ReadRegister2, +output reg[4:0] WriteRegister, +output reg RegWrite, +output reg Clk +); + + // Initialize register driver signals + initial begin + WriteData=32'd0; + ReadRegister1=5'd0; + ReadRegister2=5'd0; + WriteRegister=5'd0; + RegWrite=0; + Clk=0; + end + + // Once 'begintest' is asserted, start running test cases + always @(posedge begintest) begin + endtest = 0; + dutpassed = 1; + #10 + + // Test Case 1: + // Write '42' to register 2, verify with Read Ports 1 and 2 + WriteRegister = 5'd2; + WriteData = 32'd42; + RegWrite = 1; + ReadRegister1 = 5'd2; + ReadRegister2 = 5'd2; + #5 Clk=1; #5 Clk=0; // Generate single clock pulse + + // Verify expectations and report test result + if((ReadData1 !== 42) || (ReadData2 !== 42)) begin + dutpassed = 0; // Set to 'false' on failure + $display("Regfile Test Case 1 Failed: Didn't write value and read back"); + end + + // Test Case 2: + // Write '15' to register 2, verify with Read Ports 1 and 2 + WriteRegister = 5'd2; + WriteData = 32'd15; + RegWrite = 1; + ReadRegister1 = 5'd2; + ReadRegister2 = 5'd2; + #5 Clk=1; #5 Clk=0; + + if((ReadData1 !== 15) || (ReadData2 !== 15)) begin + dutpassed = 0; + $display("Regfile Test Case 2 Failed: Didn't write value and read back"); + end + + // Test Case 3: + // Write '42' to register 12, then disable port writing, + // then attempt to write '12' to register 12 + // (Fails if writing is always enabled) + WriteRegister = 5'd12; + WriteData = 32'd42; + RegWrite = 1; + ReadRegister1 = 5'd12; + ReadRegister2 = 5'd12; + #5 Clk=1; #5 Clk=0; + RegWrite = 0; + WriteData = 32'd12; + #5 Clk=1; #5 Clk=0; + + if((ReadData1 !== 42) || (ReadData2 !== 42)) begin + dutpassed = 0; + $display("Regfile Test Case 3 Failed: Low RegWrite didn't disable write"); + end + + // Test Case 4: + // Write '42' to register 12, then + // write '40' to register 11 + // (Fails if all ports are always written to) + // (Also Fails if either read register reads the wrong register + // which covers test case #5) + WriteRegister = 5'd12; + WriteData = 32'd42; + RegWrite=1; + ReadRegister1 = 5'd12; + ReadRegister2 = 5'd11; + #5 Clk=1; #5 Clk=0; + WriteData = 32'd40; + WriteRegister = 5'd11; + #5 Clk=1; #5 Clk=0; + + if((ReadData1 !== 42) || (ReadData2 !== 40)) begin + dutpassed = 0; + $display("Regfile Test Case 4 Failed: Separate registers not written to and read from."); + end + + // Test Case 5: + // Write '42' to register 0 + // (Fails if register 0 isn't always 0) + WriteRegister = 5'd0; + WriteData = 32'd42; + RegWrite=1; + ReadRegister1 = 5'd0; + ReadRegister2 = 5'd0; + #5 Clk=1; #5 Clk=0; + + if((ReadData1 !== 0) || (ReadData2 !== 0)) begin + dutpassed = 0; + $display("Regfile Test Case 5 Failed: Zero register not always 0."); + end + + // Test Case 6: + // Write '42' to register 12, read it using both data reads + // Then change data read port to 0 without clocking + // Fails if the read port has to be clocked to update + WriteRegister = 5'd12; + WriteData = 32'd42; + RegWrite=1; + ReadRegister1 = 5'd12; + ReadRegister2 = 5'd12; + #5 Clk=1; #5 Clk=0; + + if((ReadData1 !== 42) || (ReadData2 !== 42)) begin + dutpassed = 0; + $display("Regfile Test Case 6 Failed: Didn't write value and read back."); + end + + ReadRegister1 = 5'd0; + ReadRegister2 = 5'd0; + #5; + + if((ReadData1 !== 0) || (ReadData2 !== 0)) begin + dutpassed = 0; + $display("Regfile Test Case 6 Failed: Register has to clock to update outputs."); + end + // All done! Wait a moment and signal test completion. + #5 + endtest = 1; + +end + +endmodule diff --git a/regfile.v b/regfile.v new file mode 100644 index 0000000..dbe7251 --- /dev/null +++ b/regfile.v @@ -0,0 +1,209 @@ +//Copied from HW4. Compiled all of the submodules into this file, as we won't use them +//in our top level CPU + +//------------------------------------------------------------------------------ +// MIPS register file +// width: 32 bits +// depth: 32 words (reg[0] is static zero register) +// 2 asynchronous read ports +// 1 synchronous, positive edge triggered write port +//------------------------------------------------------------------------------ +`timescale 1 ns / 1 ps + +module regfile +( +output[31:0] ReadData1, // Contents of first register read +output[31:0] ReadData2, // Contents of second register read +input[31:0] WriteData, // Contents to write to register +input[4:0] ReadRegister1, // Address of first register to read +input[4:0] ReadRegister2, // Address of second register to read +input[4:0] WriteRegister, // Address of register to write +input wEnable, // Enable writing of register when High +input Clk // Clock (Positive Edge Triggered) +); + wire[31:0] decoder_out; + wire[31:0] reg_out[31:0]; + + decoder1to32 decoder(.out(decoder_out),.enable(wEnable),.address(WriteRegister)); + + register32zero reg0(.d(WriteData),.q(reg_out[0]),.wrenable(decoder_out[0]),.clk(Clk)); + + genvar i; + generate + for(i = 1; i < 32; i = i+1) + begin:genblock + register32 reg32( + .d(WriteData), + .q(reg_out[i]), + .wrenable(decoder_out[i]), + .clk(Clk)); + end + endgenerate + + mux32to1by32 mux1( + .out(ReadData1), + .address(ReadRegister1), + .input0( reg_out[0]), + .input1( reg_out[1]), + .input2( reg_out[2]), + .input3( reg_out[3]), + .input4( reg_out[4]), + .input5( reg_out[5]), + .input6( reg_out[6]), + .input7( reg_out[7]), + .input8( reg_out[8]), + .input9( reg_out[9]), + .input10(reg_out[10]), + .input11(reg_out[11]), + .input12(reg_out[12]), + .input13(reg_out[13]), + .input14(reg_out[14]), + .input15(reg_out[15]), + .input16(reg_out[16]), + .input17(reg_out[17]), + .input18(reg_out[18]), + .input19(reg_out[19]), + .input20(reg_out[20]), + .input21(reg_out[21]), + .input22(reg_out[22]), + .input23(reg_out[23]), + .input24(reg_out[24]), + .input25(reg_out[25]), + .input26(reg_out[26]), + .input27(reg_out[27]), + .input28(reg_out[28]), + .input29(reg_out[29]), + .input30(reg_out[30]), + .input31(reg_out[31])); + + mux32to1by32 mux2( + .out(ReadData2), + .address(ReadRegister2), + .input0( reg_out[0]), + .input1( reg_out[1]), + .input2( reg_out[2]), + .input3( reg_out[3]), + .input4( reg_out[4]), + .input5( reg_out[5]), + .input6( reg_out[6]), + .input7( reg_out[7]), + .input8( reg_out[8]), + .input9( reg_out[9]), + .input10(reg_out[10]), + .input11(reg_out[11]), + .input12(reg_out[12]), + .input13(reg_out[13]), + .input14(reg_out[14]), + .input15(reg_out[15]), + .input16(reg_out[16]), + .input17(reg_out[17]), + .input18(reg_out[18]), + .input19(reg_out[19]), + .input20(reg_out[20]), + .input21(reg_out[21]), + .input22(reg_out[22]), + .input23(reg_out[23]), + .input24(reg_out[24]), + .input25(reg_out[25]), + .input26(reg_out[26]), + .input27(reg_out[27]), + .input28(reg_out[28]), + .input29(reg_out[29]), + .input30(reg_out[30]), + .input31(reg_out[31])); + +endmodule + +// 32 bit decoder with enable signal +// enable=0: all output bits are 0 +// enable=1: out[address] is 1, all other outputs are 0 +module decoder1to32 +( +output[31:0] out, +input enable, +input[4:0] address +); + + assign out = enable<