From 80edbd866522fd4b925670a4d08a7b740457d90a Mon Sep 17 00:00:00 2001 From: skhi Date: Thu, 24 Nov 2016 20:42:47 +0100 Subject: [PATCH 1/2] Added board registers (pll, io delay) --- .DS_Store | Bin 0 -> 6148 bytes PixelFECInterface/dat/address_table.xml | 4 +++ .../include/PixelPh1FECInterface.h | 33 +++++++++++------- .../src/common/PixelPh1FECInterface.cc | 31 ++++++++++++++++ 4 files changed, 55 insertions(+), 13 deletions(-) create mode 100644 .DS_Store diff --git a/.DS_Store b/.DS_Store new file mode 100644 index 0000000000000000000000000000000000000000..0ac5640ab40d1d0614de0a621521c74175d28db4 GIT binary patch literal 6148 zcmeHK%Sr=55Ukc50$$?H~M)SE^vi@Qhhk#+*4fR3GdjB z_%Gb=@qk<0Vf(h(_q*r*F>gA2l(JGl3P=GdAO)nrFBI_JOPil0DoOzvna~C=4(Fh3Wvm?Gaq!Keg<3@nH2bI1-<~j&KFAn literal 0 HcmV?d00001 diff --git a/PixelFECInterface/dat/address_table.xml b/PixelFECInterface/dat/address_table.xml index dbfe0f0..884ea8a 100644 --- a/PixelFECInterface/dat/address_table.xml +++ b/PixelFECInterface/dat/address_table.xml @@ -278,6 +278,10 @@ + + + + diff --git a/PixelFECInterface/include/PixelPh1FECInterface.h b/PixelFECInterface/include/PixelPh1FECInterface.h index 126cb3f..06d3361 100644 --- a/PixelFECInterface/include/PixelPh1FECInterface.h +++ b/PixelFECInterface/include/PixelPh1FECInterface.h @@ -20,13 +20,17 @@ class PixelPh1FECInterface: public pos::PixelFECConfigInterface { public: - PixelPh1FECInterface(RegManager* const RegManagerPtr, const char* boardid); - - bool hasclock(); - bool clocklost(); - void resetttc(); - void resetclocklost(); - + PixelPh1FECInterface(RegManager* const RegManagerPtr, const char* boardid); + + bool hasclock(); + bool clocklost(); + void resetttc(); + void resetclocklost(); + void resetpll(); + void ttcdelayinc(); + void ttcdelaydec(); + void readdelay(); + int senddata(const int mfec, const int fecchannel); int injectrstroc(const int mfec, const int bitstate); int injecttrigger(const int mfec, const int bitstate); @@ -43,8 +47,11 @@ class PixelPh1FECInterface: public pos::PixelFECConfigInterface { int getversion(const int mfec, unsigned long *data); int getversion(unsigned long *data); int getStatus(void); + + + unsigned getGeneral(); - + int writeCSregister(int mfec, int fecchannel, int cscommand); void mfecbusy(int mfec, int fecchannel, unsigned int *cs1,unsigned int *cs2); @@ -205,21 +212,21 @@ class PixelPh1FECInterface: public pos::PixelFECConfigInterface { unsigned char mask, const bool buffermode = false); - void setAllDAC(const pos::PixelHdwAddress& theROC, + void setAllDAC(const pos::PixelHdwAddress& theROC, const std::vector& dacs, const bool buffermode = false); // from wolfram int testFiberEnable(const int mfec, const int enable); int testFiber(const int mfec, const int channel, int* rda, int * rck); - + unsigned int flipByte(unsigned int input); - + private: typedef uhal::ValWord valword; typedef uhal::ValVector valvec; RegManager * const pRegManager; - + const std::string board_id; // ordering mfecs to match designations on vme card @@ -243,7 +250,7 @@ class PixelPh1FECInterface: public pos::PixelFECConfigInterface { //int qbuflastport[9][3]; int fecdebug; - + std::vector d25_trimloadtest; }; diff --git a/PixelFECInterface/src/common/PixelPh1FECInterface.cc b/PixelFECInterface/src/common/PixelPh1FECInterface.cc index aed0b72..973baf7 100644 --- a/PixelFECInterface/src/common/PixelPh1FECInterface.cc +++ b/PixelFECInterface/src/common/PixelPh1FECInterface.cc @@ -91,6 +91,36 @@ void PixelPh1FECInterface::resetclocklost() { pRegManager->WriteReg("Board0.RstTTCLostLHC", 0); } +//----------------------------------------------------------------------- +void PixelPh1FECInterface::resetpll(){ + + pRegManager->WriteReg("Board0.PLLrst", 1); + usleep(1000); + pRegManager->WriteReg("Board0.PLLrst", 0); +} + +//----------------------------------------------------------------------- +void PixelPh1FECInterface::ttcdelayinc(){ + + pRegManager->WriteReg("Board0.IODelayInc", 3); + readdelay(); +} + +//----------------------------------------------------------------------- +void PixelPh1FECInterface::ttcdelaydec(){ + + pRegManager->WriteReg("Board0.IODelayDec", 1); + readdelay(); +} + +//----------------------------------------------------------------------- +void PixelPh1FECInterface::readdelay(){ + valword value; + value = pRegManager->ReadReg("Board0.IODelay"); + cout <<" The current io ttc delay setting is: " < Date: Thu, 24 Nov 2016 21:08:44 +0100 Subject: [PATCH 2/2] Added board registers (pll, io delay) + added ttc reset to constructor --- PixelFECInterface/src/common/PixelPh1FECInterface.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/PixelFECInterface/src/common/PixelPh1FECInterface.cc b/PixelFECInterface/src/common/PixelPh1FECInterface.cc index 973baf7..69c2f98 100644 --- a/PixelFECInterface/src/common/PixelPh1FECInterface.cc +++ b/PixelFECInterface/src/common/PixelPh1FECInterface.cc @@ -59,7 +59,7 @@ PixelPh1FECInterface::PixelPh1FECInterface(RegManager * const RegManagerPtr, pRegManager->WriteReg("ctrl.ttc_xpoint_A_out3", 0); usleep(100); - //resetttc(); + resetttc(); usleep(100); if (!hasclock() || clocklost()) { std::cerr << "hits go in wrong bx after clock lost until you reload firmware / power cycle\n"; @@ -103,6 +103,7 @@ void PixelPh1FECInterface::resetpll(){ void PixelPh1FECInterface::ttcdelayinc(){ pRegManager->WriteReg("Board0.IODelayInc", 3); + resetttc(); readdelay(); } @@ -110,6 +111,7 @@ void PixelPh1FECInterface::ttcdelayinc(){ void PixelPh1FECInterface::ttcdelaydec(){ pRegManager->WriteReg("Board0.IODelayDec", 1); + resetttc(); readdelay(); }