[Question] How to go about 128-bit loads/stores

[e820]

Hi there, as outlined in the title I'm a bit confused as to what the canonical way to perform quad-word accesses is. Regular __int128 (same behavior with mode(TI)) causes access tearing even with volatile, resulting in two ld/sd instructions being generated. Using inline assembly to force an lq/sq however seems to produce broken code.

For reference, I tried the following:

typedef unsigned __int128 u128;

void
sq(uintptr_t at, u128 val)
{
	asm volatile (
		"sq	%0, 0(%1)\n\t"
		:: "r" (val), "r" (at)
		: "memory"
	);
}

int
main()
{
	u128 n = ((u128)0xaaaa'bbbb'cccc'dddd << 64) | 0xaaaa'bbbb'cccc'dddd;

	sq(0x1000'6000, n);
}

Which results in the following assembly being emitted:

00000000 <main>:
   0:	3c020000 	lui	v0,0x0
   4:	24420000 	addiu	v0,v0,0
   8:	dc440000 	ld	a0,0(v0)
   c:	dc450008 	ld	a1,8(v0)
  10:	3c021000 	lui	v0,0x1000
  14:	24426000 	addiu	v0,v0,24576
  18:	7c440000 	sq	a0,0(v0)
  1c:	03e00008 	jr	ra
  20:	00001025 	move	v0,zero
  24:	00000000 	nop

[rickgaiser]

sq/lq need 16byte alignment.

Note that I'm working on improving gcc with ALL features:

• 128bit support
• MMI SIMD with autovectorization
• VU0 SIMD with autovectorization

You can find a functional test branch here:
https://gitlab.com/ps2max/toolchain/gcc/-/tree/fjtrujy?ref_type=heads