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207716e
initial project proposal added
LoganSweet Nov 17, 2017
da53d74
filetype changed
LoganSweet Nov 17, 2017
2937c0e
Update ProjectProposal.md
LoganSweet Nov 17, 2017
53ae4a5
pseudocode for Main algorithm
mjakus Nov 26, 2017
3e2be80
working on addroundkey
mjakus Nov 26, 2017
e78527d
folder for testing added, working on 2d arrays
LoganSweet Nov 26, 2017
6360750
addign some examples from online. still getting sorry message
LoganSweet Nov 26, 2017
736175f
sources added
LoganSweet Nov 26, 2017
94f292a
will this all explode?
mjakus Nov 26, 2017
c5dcaa5
Merge branch 'master' of https://github.com/LoganSweet/FinalProject
mjakus Nov 26, 2017
495567d
did this explode?
mjakus Nov 26, 2017
92046b1
resolving debacles
LoganSweet Nov 26, 2017
a729831
updated proposal to have all requirements
LoganSweet Nov 26, 2017
1c61390
tiny edit in case you pull
mjakus Nov 28, 2017
9c4d681
working on add round key
mjakus Nov 28, 2017
ad6a035
AddRoundKey seems to work just fine. Having problems assigning values…
mjakus Nov 29, 2017
f912a94
making progress but having ShiftRows-related problems
mjakus Nov 29, 2017
d7c0ac1
making moves on Shift Rows, having questions about what's a reg vs wi…
mjakus Nov 29, 2017
6b09ef5
making edits to shift rows
mjakus Nov 30, 2017
74ab094
investigating nonblocking assignments in ShiftRows
mjakus Nov 30, 2017
5ebee25
making progress on ShiftRows
mjakus Nov 30, 2017
d460653
working on mixcolumns but on paper. macros still not working
mjakus Nov 30, 2017
811048e
got shiftrows working, having brain indexing problem with addroundkey
mjakus Nov 30, 2017
34c061e
mixing some columns
mjakus Nov 30, 2017
3b6244c
ShiftRows with 4x4 matrix (each entry only 1 bit tho) working!
mjakus Nov 30, 2017
cdbe412
working on mixing those columns
mjakus Nov 30, 2017
d6749dc
making progress on mixcolumns, can no longer think
mjakus Dec 1, 2017
9213394
working on mixcol
mjakus Dec 1, 2017
d3b4d01
almost done with mix columns
mjakus Dec 2, 2017
2f31f03
made edits to mix col and they were wrong so I took them back :(
mjakus Dec 2, 2017
cb835a3
MixColumns is fully functional!
mjakus Dec 2, 2017
1006142
haven't really changed anything but that's fine
mjakus Dec 2, 2017
855deeb
shift rows is fully functional!
mjakus Dec 3, 2017
94de73a
starting on key expansion
mjakus Dec 3, 2017
6261fb9
adding in-progress Galois Field files
LoganSweet Dec 3, 2017
b0bef6f
organize addition file, delete redundant file
LoganSweet Dec 3, 2017
1efa4ae
wrong answers but no errors in v3
LoganSweet Dec 3, 2017
8217128
commit since I have a SCOPE meeting
LoganSweet Dec 3, 2017
1356593
can logan count in binary? who knowsgit status
LoganSweet Dec 5, 2017
a276b72
Logan only could partially count in binary, but the same is true for …
mjakus Dec 5, 2017
05708cf
filled in rest of sbox, something not working
mjakus Dec 5, 2017
3e9849a
sbox still confused
mjakus Dec 5, 2017
f770d9b
sbox is fully functional!
mjakus Dec 5, 2017
42c13da
most updated
mjakus Dec 5, 2017
dd5d555
SubBytes fully functional
mjakus Dec 5, 2017
6557eea
key expansion in progress
mjakus Dec 5, 2017
e653458
keyexpansion is fully functional!
mjakus Dec 5, 2017
6dbcd21
working on MainAlgorithm
mjakus Dec 5, 2017
f3242e7
on a mission to get this done, but going to DD first
mjakus Dec 6, 2017
a26ee1d
Inverse Mix Columns is on its way
mjakus Dec 6, 2017
3f6ef26
working on inverse sbox
mjakus Dec 6, 2017
77e6de4
getting close!
mjakus Dec 6, 2017
0bc343d
trying to put encryption together, having conceptual problems with if…
mjakus Dec 7, 2017
14a5808
feel surprisingly good. something must be wrong
mjakus Dec 7, 2017
a15084c
working on adding DFF
mjakus Dec 7, 2017
7518016
oh your circuit went to sleep
mjakus Dec 7, 2017
4fe6c83
working on decryption, have questions for Ben about timing. classic
mjakus Dec 8, 2017
9712d24
have a no errors system, but the results aren't correct
mjakus Dec 8, 2017
fc8b294
what's the best way to do key expansion on decryption
mjakus Dec 8, 2017
686ba41
making things more accurate, one tiny step at a time
mjakus Dec 9, 2017
2faea87
Same general timing problem as with CPU, but much less impactful
mjakus Dec 11, 2017
b9527f6
fixed error in inv key expansion
mjakus Dec 11, 2017
2e093b3
formatting
mjakus Dec 11, 2017
b80c00e
small error in mux --> big errors elsewhere.
mjakus Dec 11, 2017
3050679
need to fix round E / mux. currently it expands the key one too many …
mjakus Dec 11, 2017
827762c
working on brute forcing it - need to validate that everything actual…
mjakus Dec 12, 2017
9c5b151
Fixed Inverse Shift Rows
mjakus Dec 12, 2017
d3c4787
fixing errors in encryption decryption
mjakus Dec 12, 2017
8bca629
fixing errors in encryption decryption
mjakus Dec 12, 2017
46b2908
The key gets totally encrypted and decrypted and comes back out correct!
mjakus Dec 12, 2017
6c07f38
The key gets totally encrypted and decrypted and comes back out correct!
mjakus Dec 12, 2017
b3a18bb
Pretty sure it's an error in the S-Box or inverse S-Box
mjakus Dec 12, 2017
4906fae
Final report uploaded
LoganSweet Dec 12, 2017
01001cc
Delete AES_FinalReport.pdf
LoganSweet Mar 12, 2018
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125 changes: 125 additions & 0 deletions ARK
Original file line number Diff line number Diff line change
@@ -0,0 +1,125 @@
#! /usr/local/bin/vvp
:ivl_version "10.1 (stable)" "(v10_1-95-g9486187)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "system";
:vpi_module "vhdl_sys";
:vpi_module "v2005_math";
:vpi_module "va_math";
S_0x22fcf10 .scope module, "testARK" "testARK" 2 54;
.timescale 0 0;
v0x2318d90_0 .net "ao", 7 0, L_0x231a5f0; 1 drivers
v0x2318e90_0 .var "rk", 7 0;
v0x2318f90_0 .var "s", 7 0;
S_0x22fd090 .scope module, "test1" "AddRoundKey" 2 60, 2 5 0, S_0x22fcf10;
.timescale 0 0;
.port_info 0 /INPUT 8 "inarray"
.port_info 1 /INPUT 8 "keyarray"
.port_info 2 /OUTPUT 8 "outarray"
P_0x22f1180 .param/l "elements" 0 2 17, +C4<00000000000000000000000000000010>;
v0x2318260_0 .net *"_s0", 0 0, L_0x23190c0; 1 drivers
v0x2318360_0 .net *"_s12", 0 0, L_0x23199d0; 1 drivers
v0x2318440_0 .net *"_s16", 0 0, L_0x2319c20; 1 drivers
v0x2318530_0 .net *"_s20", 0 0, L_0x2319f00; 1 drivers
v0x2318610_0 .net *"_s24", 0 0, L_0x231a1a0; 1 drivers
v0x2318740_0 .net *"_s28", 0 0, L_0x231a130; 1 drivers
v0x2318820_0 .net *"_s4", 0 0, L_0x23193f0; 1 drivers
v0x2318900_0 .net *"_s8", 0 0, L_0x2319640; 1 drivers
v0x23189e0_0 .net "inarray", 7 0, v0x2318e90_0; 1 drivers
v0x2318b30_0 .net "keyarray", 7 0, v0x2318f90_0; 1 drivers
v0x2318c20_0 .net "outarray", 7 0, L_0x231a5f0; alias, 1 drivers
L_0x23191c0 .part v0x2318e90_0, 0, 1;
L_0x23192b0 .part v0x2318f90_0, 0, 1;
L_0x2319460 .part v0x2318e90_0, 1, 1;
L_0x2319550 .part v0x2318f90_0, 1, 1;
L_0x23196e0 .part v0x2318e90_0, 2, 1;
L_0x2319860 .part v0x2318f90_0, 2, 1;
L_0x2319a40 .part v0x2318e90_0, 3, 1;
L_0x2319ae0 .part v0x2318f90_0, 3, 1;
L_0x2319cc0 .part v0x2318e90_0, 4, 1;
L_0x2319db0 .part v0x2318f90_0, 4, 1;
L_0x2319fa0 .part v0x2318e90_0, 5, 1;
L_0x231a040 .part v0x2318f90_0, 5, 1;
L_0x231a240 .part v0x2318e90_0, 6, 1;
L_0x231a440 .part v0x2318f90_0, 6, 1;
LS_0x231a5f0_0_0 .concat8 [ 1 1 1 1], L_0x23190c0, L_0x23193f0, L_0x2319640, L_0x23199d0;
LS_0x231a5f0_0_4 .concat8 [ 1 1 1 1], L_0x2319c20, L_0x2319f00, L_0x231a1a0, L_0x231a130;
L_0x231a5f0 .concat8 [ 4 4 0 0], LS_0x231a5f0_0_0, LS_0x231a5f0_0_4;
L_0x231a9b0 .part v0x2318e90_0, 7, 1;
L_0x231aaa0 .part v0x2318f90_0, 7, 1;
S_0x22c5d90 .scope generate, "genblk1[0]" "genblk1[0]" 2 30, 2 30 0, S_0x22fd090;
.timescale 0 0;
P_0x22c5f60 .param/l "i" 0 2 30, +C4<00>;
S_0x22f1c30 .scope generate, "genblk2[0]" "genblk2[0]" 2 31, 2 31 0, S_0x22c5d90;
.timescale 0 0;
P_0x22f1e00 .param/l "j" 0 2 31, +C4<00>;
L_0x23190c0 .functor XOR 1, L_0x23191c0, L_0x23192b0, C4<0>, C4<0>;
v0x22f1ea0_0 .net *"_s1", 0 0, L_0x23191c0; 1 drivers
v0x2315910_0 .net *"_s2", 0 0, L_0x23192b0; 1 drivers
S_0x23159f0 .scope generate, "genblk2[1]" "genblk2[1]" 2 31, 2 31 0, S_0x22c5d90;
.timescale 0 0;
P_0x2315c00 .param/l "j" 0 2 31, +C4<01>;
L_0x23193f0 .functor XOR 1, L_0x2319460, L_0x2319550, C4<0>, C4<0>;
v0x2315cc0_0 .net *"_s1", 0 0, L_0x2319460; 1 drivers
v0x2315da0_0 .net *"_s2", 0 0, L_0x2319550; 1 drivers
S_0x2315e80 .scope generate, "genblk1[1]" "genblk1[1]" 2 30, 2 30 0, S_0x22fd090;
.timescale 0 0;
P_0x2316090 .param/l "i" 0 2 30, +C4<01>;
S_0x2316150 .scope generate, "genblk2[0]" "genblk2[0]" 2 31, 2 31 0, S_0x2315e80;
.timescale 0 0;
P_0x2316340 .param/l "j" 0 2 31, +C4<00>;
L_0x2319640 .functor XOR 1, L_0x23196e0, L_0x2319860, C4<0>, C4<0>;
v0x2316420_0 .net *"_s1", 0 0, L_0x23196e0; 1 drivers
v0x2316500_0 .net *"_s2", 0 0, L_0x2319860; 1 drivers
S_0x23165e0 .scope generate, "genblk2[1]" "genblk2[1]" 2 31, 2 31 0, S_0x2315e80;
.timescale 0 0;
P_0x23167f0 .param/l "j" 0 2 31, +C4<01>;
L_0x23199d0 .functor XOR 1, L_0x2319a40, L_0x2319ae0, C4<0>, C4<0>;
v0x23168b0_0 .net *"_s1", 0 0, L_0x2319a40; 1 drivers
v0x2316990_0 .net *"_s2", 0 0, L_0x2319ae0; 1 drivers
S_0x2316a70 .scope generate, "genblk1[2]" "genblk1[2]" 2 30, 2 30 0, S_0x22fd090;
.timescale 0 0;
P_0x2316cb0 .param/l "i" 0 2 30, +C4<010>;
S_0x2316d50 .scope generate, "genblk2[0]" "genblk2[0]" 2 31, 2 31 0, S_0x2316a70;
.timescale 0 0;
P_0x2316f40 .param/l "j" 0 2 31, +C4<00>;
L_0x2319c20 .functor XOR 1, L_0x2319cc0, L_0x2319db0, C4<0>, C4<0>;
v0x2317020_0 .net *"_s1", 0 0, L_0x2319cc0; 1 drivers
v0x2317100_0 .net *"_s2", 0 0, L_0x2319db0; 1 drivers
S_0x23171e0 .scope generate, "genblk2[1]" "genblk2[1]" 2 31, 2 31 0, S_0x2316a70;
.timescale 0 0;
P_0x23173f0 .param/l "j" 0 2 31, +C4<01>;
L_0x2319f00 .functor XOR 1, L_0x2319fa0, L_0x231a040, C4<0>, C4<0>;
v0x23174b0_0 .net *"_s1", 0 0, L_0x2319fa0; 1 drivers
v0x2317590_0 .net *"_s2", 0 0, L_0x231a040; 1 drivers
S_0x2317670 .scope generate, "genblk1[3]" "genblk1[3]" 2 30, 2 30 0, S_0x22fd090;
.timescale 0 0;
P_0x2317880 .param/l "i" 0 2 30, +C4<011>;
S_0x2317940 .scope generate, "genblk2[0]" "genblk2[0]" 2 31, 2 31 0, S_0x2317670;
.timescale 0 0;
P_0x2317b30 .param/l "j" 0 2 31, +C4<00>;
L_0x231a1a0 .functor XOR 1, L_0x231a240, L_0x231a440, C4<0>, C4<0>;
v0x2317c10_0 .net *"_s1", 0 0, L_0x231a240; 1 drivers
v0x2317cf0_0 .net *"_s2", 0 0, L_0x231a440; 1 drivers
S_0x2317dd0 .scope generate, "genblk2[1]" "genblk2[1]" 2 31, 2 31 0, S_0x2317670;
.timescale 0 0;
P_0x2317fe0 .param/l "j" 0 2 31, +C4<01>;
L_0x231a130 .functor XOR 1, L_0x231a9b0, L_0x231aaa0, C4<0>, C4<0>;
v0x23180a0_0 .net *"_s1", 0 0, L_0x231a9b0; 1 drivers
v0x2318180_0 .net *"_s2", 0 0, L_0x231aaa0; 1 drivers
.scope S_0x22fcf10;
T_0 ;
%vpi_call 2 64 "$display", "AOut | RK | S" {0 0 0};
%pushi/vec4 31, 0, 8;
%store/vec4 v0x2318e90_0, 0, 8;
%pushi/vec4 251, 0, 8;
%store/vec4 v0x2318f90_0, 0, 8;
%delay 20, 0;
%vpi_call 2 66 "$display", "%b | %b | %b", v0x2318d90_0, v0x2318e90_0, v0x2318f90_0 {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 3;
"N/A";
"<interactive>";
"AddRoundKey.v";
45 changes: 45 additions & 0 deletions AddRoundKey.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,45 @@
// it actually makes no sense to use macros on ARK, so we won't!
//`define STATE(r,c) inarray[(dimension*dimension-1)-((dimension*(c-1))+(r-1))]
//`define ROUNDKEY(r,c) keyarray[(dimension*dimension-1)-((dimension*(c-1))+(r-1))]
//`define OUT(r,c) outarray[(dimension*dimension-1)-((dimension*(c-1))+(r-1))]

module AddRoundKey(
// each byte (entry) of the state is combined with a block of the round key using bitwise xor
input [127:0] inarray,
input [127:0] keyarray,
output [127:0] outarray
);

//parameter dimension = 4;

genvar entry;
generate
for (entry = 0; entry < 128; entry = entry+1) begin
xor(outarray[entry], inarray[entry], keyarray[entry]);
end
endgenerate


endmodule


module testARK();

reg [127:0] rk;
reg [127:0] s;
wire [127:0] ao;

AddRoundKey test1(rk, s, ao);

initial begin

$display("AOut | RK | S");
rk = 128'h2A ; s = 128'h19
; #20
$display("%b ", ao);



end

endmodule
94 changes: 94 additions & 0 deletions BruteForceAES.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,94 @@
RoundA 1
KeyIn = 123
StateIn = 101110011111
iterate = 1
KeyOut = 01100010011000110110001101100011011000100110001101100011011000110110001001100011011000110110001101100010011111000010011001100011
StateOut = 01100010011000110110001101100011011000100110001101100011011000110110001001100011011000110110001101100010011111000010110111111100

RoundA 2
KeyIn = 01100010011000110110001101100011011000100110001101100011011000110110001001100011011000110110001101100010011111000010011001100011
StateIn = 01100010011000110110001101100011011000100110001101100011011000110110001001100011011000110110001101100010011111000010110111111100
iterate = 2
KeyOut =
11111001111110111111101110101010111110011111101111111011101010101111100111111011111110111010101000010010111101111111101110101010
StateOut =10011011100110001001100011001001100110111001100010011000110010011001101110011000100110001100100101110000100010111101011001010110

RoundB
KeyIn = 11111001111110111111101110101010111110011111101111111011101010101111100111111011111110111010101000010010111101111111101110101010
Statein = 10011011100110001001100011001001100110111001100010011000110010011001101110011000100110001100100101110000100010111101011001010110
iterate = 3

KeyOut = 00001011000011111010110010011001000010110000111110101100100110010000101100001111101011001001100101101100000011111010110011001001
StateOut = 00011111010010011110101000101000000111110100100101011010010001000001111100110010111010100100010000111101010010011110101000010100


Decrypt!

FIRST - ARK KeyOut and StateOut from RoundB
--> Key is same
StateOut = 00010100010001100100011010110001000101000100011011110110110111010001010000111101010001101101110101010001010001100100011011011101



THEN ROUND C
KeyIn = 00001011000011111010110010011001000010110000111110101100100110010000101100001111101011001001100101101100000011111010110011001001
StateIn =
00010100010001100100011010110001000101000100011011110110110111010001010000111101010001101101110101010001010001100100011011011101
iterate = 2
KeyOut = 11111001111110111111101110101010111110011111101111111011101010101111100111111011111110111010101000010010111101111111101110101010
StateOut =
01101101011010100110111001101000110010111101100111001011010101000110110101101010011011100110100000110010101101101111101100111100



Round C2
KeyIn =
11111001111110111111101110101010111110011111101111111011101010101111100111111011111110111010101000010010111101111111101110101010
StateIn = 01101101011010100110111001101000110010111101100111001011010101000110110101101010011011100110100000110010101101101111101100111100
iterate = 1
KeyOut = 01100010011000110110001101100011011000100110001101100011011000110110001001100011011000110110001101100010011111000010011001100011

StateOut =
00100100011000010010110100010111100011111001111110000111000000110110101110000010011110101110000010111100000010000001100010100000


Round D - will we get it???
KeyIn = 01100010011000110110001101100011011000100110001101100011011000110110001001100011011000110110001101100010011111000010011001100011
StateIn = 00100100011000010010110100010111100011111001111110000111000000110110101110000010011110101110000010111100000010000001100010100000
iterate = 1

KeyOut = 123!
StateOut = :(





NEW TRY
ARK
Round B
ARK
Round D - does it work?

ARK - KeyIn = 123, StateIn = ABC
Output = 101110011111

RoundB - KeyIn = 123, StateIn = 101110011111
KeyOut = 01100010011000110110001101100011011000100110001101100011011000110110001001100011011000110110001101100010011111000010011001100011
StateOut = 00000001000000000000000010111000000000010000000001001000000000000000000100000000000000000000000000000001000111110100010100000000

ARK -
Key = 01100010011000110110001101100011011000100110001101100011011000110110001001100011011000110110001101100010011111000010011001100011
StateIn =
00000001000000000000000010111000000000010000000001001000000000000000000100000000000000000000000000000001000111110100010100000000

StateOut =
01100011011000110110001111011011011000110110001100101011011000110110001101100011011000110110001101100011011000110110001101100011

RoundD






18 changes: 18 additions & 0 deletions DFF128.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,18 @@

module DFF
(
output reg [size-1:0] q,
input [size-1:0] d,
input clk
);


parameter size = 128;

always @(posedge clk) begin
q <= d;
end

endmodule


84 changes: 84 additions & 0 deletions Decrypt.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,84 @@
`include "RoundC.v"
//`include "RoundA.v"
`include "Encrypt.v"

module Decrypt(
input [127:0] SecretKey,
input [127:0] CipheredText,
input clk,
output [127:0] DecryptedText,
output [127:0] OriginalKey
);

wire [127:0] NewState;
wire [127:0] NewRoundKey;
wire [1:0] Ctrl;
wire OUTCtrl;
wire [127:0] RoundAStateOut;
wire [127:0] RoundBStateOut;
wire [127:0] RoundFStateOut;
wire [127:0] RoundAKeyOut;
wire [127:0] RoundBKeyOut;
wire [127:0] RoundFKeyOut;

wire [127:0] MuxKeyOut;
wire [127:0] MuxStateOut;

wire [7:0] newiterate;


DFF flipflopKey(NewRoundKey, MuxKeyOut, clk); // out, in, clk
DFF flipflopState(NewState, MuxStateOut, clk); // out, in, clk


InvFSM controls(clk, Ctrl, OUTCtrl, newiterate);

mux RKmux(Ctrl, RoundAKeyOut, RoundBKeyOut, SecretKey, RoundFKeyOut, MuxKeyOut); // control, inA, inB, initial key, out
mux SMmux(Ctrl, RoundAStateOut, RoundBStateOut, CipheredText, RoundFStateOut, MuxStateOut);

RoundC Invoptions1_9(NewRoundKey, NewState, newiterate, RoundAKeyOut, RoundAStateOut);
RoundD Invoption10(NewRoundKey, NewState, newiterate, RoundBKeyOut, RoundBStateOut);
RoundF Invoption0(NewRoundKey, NewState, RoundFStateOut, RoundFKeyOut);


smallmux OUTmux(OUTCtrl, MuxStateOut, DecryptedText);
smallmux OUTkeymux(OUTCtrl, MuxKeyOut, OriginalKey);

endmodule

module testDecrypt();


reg [127:0] SecretKey;
reg [127:0] CipherText;
reg clk;
wire [127:0] PlainText;
wire [127:0] OrigKey;

Decrypt testing(SecretKey, CipherText, clk, PlainText, OrigKey);

initial clk=0;
always #10 clk=!clk;

initial begin

$dumpfile("decrypt.vcd");
$dumpvars();

SecretKey = 128'h5701D4E05701D4E05701D4E057DAD4E0; CipherText = 128'hCDF27FDACDF29F4CCD3A7F4C60297F4C; #500

//SecretKey = 128'h7715D9597715D9597715D9597731D959; CipherText = 128'h23ECBEB923EC4DAF2323BEAFBC8BEAF; #500
$display("%b ", PlainText);

$finish;
end
endmodule









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