completed homework 2

adder.t.v

@@ -6,9 +6,38 @@ module testFullAdder();
     reg a, b, carryin;
     wire sum, carryout;
 
-    behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    structuralFullAdder adder (sum, carryout, a, b, carryin);
 
     initial begin
-        // Your test code here
+	$dumpfile("adder.vcd");
+	$dumpvars();
+
+	$display("|   input   ||expected|| actual |");
+        $display("| a | b |cin||sum|cout||sum|cout|");
+	a=0; b=0; carryin=0; #1000
+        $display("| %b | %b | %b || 0 | 0  || %b | %b  |",
+		a, b, carryin, sum, carryout);
+	a=1; b=0; carryin=0; #1000
+        $display("| %b | %b | %b || 1 | 0  || %b | %b  |",
+		a, b, carryin, sum, carryout);
+	a=0; b=1; carryin=0; #1000
+        $display("| %b | %b | %b || 1 | 0  || %b | %b  |",
+		a, b, carryin, sum, carryout);
+	a=1; b=1; carryin=0; #1000
+        $display("| %b | %b | %b || 0 | 1  || %b | %b  |",
+		a, b, carryin, sum, carryout);
+
+	a=0; b=0; carryin=1; #1000
+        $display("| %b | %b | %b || 1 | 0  || %b | %b  |",
+		a, b, carryin, sum, carryout);
+	a=1; b=0; carryin=1; #1000
+        $display("| %b | %b | %b || 0 | 1  || %b | %b  |",
+		a, b, carryin, sum, carryout);
+	a=0; b=1; carryin=1; #1000
+        $display("| %b | %b | %b || 0 | 1  || %b | %b  |",
+		a, b, carryin, sum, carryout);
+	a=1; b=1; carryin=1; #1000
+        $display("| %b | %b | %b || 1 | 1  || %b | %b  |",
+		a, b, carryin, sum, carryout);
     end
 endmodule

adder.v

@@ -1,4 +1,8 @@
 // Adder circuit
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+`define XOR xor #50
 
 module behavioralFullAdder
 (
@@ -20,5 +24,20 @@ module structuralFullAdder
     input b, 
     input carryin
 );
-    // Your adder code here
+    //wire axorb;
+    wire ab;
+    //`XOR aXORb(axorb, a, b);
+    `AND aANDb(ab, a, b);
+    //wire axorbc;
+    //`AND aXORbc(axorbc, axorb, carryin);
+    //`XOR aXORbXORc(sum, axorb, carryin);
+    //`OR abORaXORbc(carryout, ab, axorbc);
+    wire bc;
+    wire ac;
+    `AND bANDc(bc, b, carryin);
+    `AND aANDc(ac, a, carryin);
+
+    `OR cout(carryout, ab, bc, ac);
+    `XOR sumout(sum, a, b, carryin);
+
 endmodule

decoder.t.v

@@ -2,15 +2,17 @@
 `timescale 1 ns / 1 ps
 `include "decoder.v"
 
-module testDecoder (); 
+module testDecoder ();
     reg addr0, addr1;
     reg enable;
     wire out0,out1,out2,out3;
 
-    behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
+    structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
     //structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
 
     initial begin
+    $dumpfile("decoder.vcd");
+    $dumpvars();
     $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
     enable=0;addr0=0;addr1=0; #1000 
     $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);

decoder.v

@@ -1,4 +1,6 @@
 // Decoder circuit
+`define AND and #50
+`define NOT not #50
 
 module behavioralDecoder
 (
@@ -17,6 +19,13 @@ module structuralDecoder
     input address0, address1,
     input enable
 );
-    // Your decoder code here
+wire nA0, nA1;
+`NOT notA0(nA0, address0);
+`NOT notA1(nA1, address1);
+`AND outzero(out0, nA1, nA0, enable);
+`AND outzero(out1, nA1, address0, enable);
+`AND outzero(out2, address1, nA0, enable);
+`AND outzero(out3, address1, address0, enable);
+
 endmodule
 

multiplexer.t.v

@@ -3,5 +3,47 @@
 `include "multiplexer.v"
 
 module testMultiplexer ();
-  // Your test code here
+  reg addr0, addr1;
+  reg in0, in1, in2, in3;
+  wire out;
+  input A;
+
+  structuralMultiplexer multiplexer (out, addr0, addr1, in0, in1, in2, in3);
+
+  initial begin
+  $dumpfile("multiplexer.vcd");
+  $dumpvars();
+
+  $display("|    input s    ||  select   |expected|actual|");
+  $display("|in0|in1|in2|in3||addr1|addr0|| out  || out  |");
+  $display("+---+---+---+---++-----+-----++------++------+");
+  in0=0;
+  addr0=0; addr1=0; #1000
+  $display("| %b | %b | %b | %b ||  %b  |  %b  || in0  ||  %b   |",
+	in0, in1,  in2, in3, addr1, addr0, out);
+  in0=1; #1000
+  $display("| %b | %b | %b | %b ||  %b  |  %b  || in0  ||  %b   |",
+	in0, in1,  in2, in3, addr1, addr0, out);
+  in1=0;in0=1'dx;
+  addr0=1; addr1=0; #1000
+  $display("| %b | %b | %b | %b ||  %b  |  %b  || in1  ||  %b   |",
+	in0, in1,  in2, in3, addr1, addr0, out);
+  in1=1; #1000
+  $display("| %b | %b | %b | %b ||  %b  |  %b  || in1  ||  %b   |",
+	in0, in1,  in2, in3, addr1, addr0, out);
+  in2=0;in1=1'dx;
+  addr0=0; addr1=1; #1000
+  $display("| %b | %b | %b | %b ||  %b  |  %b  || in2  ||  %b   |",
+	in0, in1,  in2, in3, addr1, addr0, out);
+  in2=1; #1000
+  $display("| %b | %b | %b | %b ||  %b  |  %b  || in2  ||  %b   |",
+	in0, in1,  in2, in3, addr1, addr0, out);
+  in3=0;in2=1'dx;
+  addr0=1; addr1=1; #1000
+  $display("| %b | %b | %b | %b ||  %b  |  %b  || in3  ||  %b   |",
+	in0, in1,  in2, in3, addr1, addr0, out);
+  in3=1; #1000
+  $display("| %b | %b | %b | %b ||  %b  |  %b  || in3  ||  %b   |",
+	in0, in1,  in2, in3, addr1, addr0, out);
+  end
 endmodule

multiplexer.v

@@ -1,4 +1,7 @@
 // Multiplexer circuit
+`define AND and #50
+`define NOT not #50
+`define OR or #50
 
 module behavioralMultiplexer
 (
@@ -19,6 +22,15 @@ module structuralMultiplexer
     input address0, address1,
     input in0, in1, in2, in3
 );
-    // Your multiplexer code here
+    wire nA0, nA1;
+    wire out0, out1, out2, out3;
+    `NOT notA0(nA0, address0);
+    `NOT notA1(nA1, address1);
+    `AND outzero(out0, nA1, nA0, in0);
+    `AND outone(out1, nA1, address0, in1);
+    `AND outtwo(out2, address1, nA0, in2);
+    `AND outthree(out3, address1, address0, in3);
+    `OR outfinal(out, out0, out1, out2, out3);
+
 endmodule
 

writeup.md

@@ -0,0 +1,38 @@
+# Homework 2 Writeup
+Rocco DiVerdi
+
+### Adder
+
+The adder has three inputs (a0, a1, and cin) and two outputs (sum and cout). The output for sum is the ones digit of the sum of a, b, and cin, and the output for s is the "tens" digit of the sum. The test shown below demonstrates my working verilog code through a truth table.
+
+![adder truth table](adderTest.png)
+
+The gate propogation delays are shown here:
+
+![adder wave propogation](adderWave.png)
+
+The adder reaches its final state after a maximum of two gate delays (100 ns).
+
+### Multiplexer
+
+The functionality of the four input multiplexer is shown in the truth table below:
+
+![multiplexer truth table](multiplexerTest.png)
+
+The gate propogation delays are shown here:
+
+![multiplexer wave propogation](multiplexerWave.png)
+
+The multiplexer reaches its final state after a maximum of two gate delays (150 ns).
+
+### Decoder
+
+The four output enabled decoder test is shown below
+
+![decoder truth table](decoderTest.png)
+
+The gate propogation delays are shown here:
+
+![decoder wave propogation](decoderWave.png)
+
+The decoder reaches its final state after two gate delays (100 ns).