Ariana Homework 2 Submission

adder.t.v

@@ -6,9 +6,29 @@ module testFullAdder();
     reg a, b, carryin;
     wire sum, carryout;
 
-    behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    // behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    structuralFullAdder adder (sum, carryout, a, b, carryin); // Swap after testing
 
     initial begin
-        // Your test code here
+    $dumpfile("adder.vcd");
+    $dumpvars();
+    $display("A B Cin | Cout S | Expected Output");
+    a=0;b=0;carryin=0; #1000
+    $display("%b %b  %b  |   %b  %b | Both false, total = 0", a, b, carryin, carryout, sum);
+    a=1;b=0;carryin=0; #1000
+    $display("%b %b  %b  |   %b  %b | S only,     total = 1", a, b, carryin, carryout, sum);
+    a=0;b=1;carryin=0; #1000
+    $display("%b %b  %b  |   %b  %b | S only,     total = 1", a, b, carryin, carryout, sum);
+    a=0;b=0;carryin=1; #1000
+    $display("%b %b  %b  |   %b  %b | S only,     total = 1", a, b, carryin, carryout, sum);
+    a=1;b=1;carryin=0; #1000
+    $display("%b %b  %b  |   %b  %b | Cout only,  total = 2", a, b, carryin, carryout, sum);
+    a=1;b=0;carryin=1; #1000
+    $display("%b %b  %b  |   %b  %b | Cout only,  total = 2", a, b, carryin, carryout, sum);
+    a=0;b=1;carryin=1; #1000
+    $display("%b %b  %b  |   %b  %b | Cout only,  total = 2", a, b, carryin, carryout, sum);
+    a=1;b=1;carryin=1; #1000
+    $display("%b %b  %b  |   %b  %b | Both true,  total = 3", a, b, carryin, carryout, sum);
+    $finish();
     end
 endmodule

adder.v

@@ -1,5 +1,9 @@
 // Adder circuit
 
+`define AND and #50
+`define XOR xor #50
+`define OR or #50
+
 module behavioralFullAdder
 (
     output sum, 
@@ -20,5 +24,15 @@ module structuralFullAdder
     input b, 
     input carryin
 );
-    // Your adder code here
+    wire cout1;
+    wire cout2;
+    wire sumAB;
+
+    `XOR AxorB(sumAB, a, b);
+    `XOR sumABxorCin(sum, sumAB, carryin);
+
+    `AND AandB(cout1, a, b);
+    `AND sumABandCin(cout2, sumAB, carryin);
+
+    `OR orcarries(carryout, cout1, cout2);
 endmodule

decoder.t.v

@@ -7,10 +7,12 @@ module testDecoder ();
     reg enable;
     wire out0,out1,out2,out3;
 
-    behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
-    //structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
+    // behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
+    structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
 
     initial begin
+    $dumpfile("decoder.vcd");
+    $dumpvars();
     $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
     enable=0;addr0=0;addr1=0; #1000 
     $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
@@ -28,6 +30,7 @@ module testDecoder ();
     $display("%b  %b  %b |  %b  %b  %b  %b | O2 Only", enable, addr0, addr1, out0, out1, out2, out3);
     enable=1;addr0=1;addr1=1; #1000 
     $display("%b  %b  %b |  %b  %b  %b  %b | O3 Only", enable, addr0, addr1, out0, out1, out2, out3);
+    $finish();
     end
 
 endmodule

decoder.v

@@ -1,5 +1,8 @@
 // Decoder circuit
 
+`define AND and #50
+`define NOT not #50
+
 module behavioralDecoder
 (
     output out0, out1, out2, out3,
@@ -17,6 +20,26 @@ module structuralDecoder
     input address0, address1,
     input enable
 );
-    // Your decoder code here
+
+    wire nA0;
+    wire nA1;
+    wire nA0andnA1;
+    wire A0andnA1;
+    wire nA0andA1;
+    wire A0andA1;
+
+    `NOT A0inv(nA0, address0);
+    `NOT A1inv(nA1, address1);
+
+    `AND andgate00(nA0andnA1, nA0, nA1);
+    `AND andgate01(A0andnA1, address0, nA1);
+    `AND andgate02(nA0andA1, nA0, address1);
+    `AND andgate03(A0andA1, address0, address1);
+
+    `AND andgateout0(out0, enable, nA0andnA1);
+    `AND andgateout1(out1, enable, A0andnA1);
+    `AND andgateout2(out2, enable, nA0andA1);
+    `AND andgateout3(out3, enable, A0andA1);
+
 endmodule
 

multiplexer.t.v

@@ -3,5 +3,36 @@
 `include "multiplexer.v"
 
 module testMultiplexer ();
-  // Your test code here
+  reg address0, address1;
+  reg in0, in1, in2, in3;
+  wire out;
+
+  // behavioralMultiplexer multiplexer (out, address0, address1, in0, in1, in2, in3);
+  structuralMultiplexer multiplexer (out, address0, address1, in0, in1, in2, in3);
+
+  initial begin
+    $dumpfile("multiplexer.vcd");
+    $dumpvars();
+
+    // The inputs that are not expected to be selected as the output so not need to be defined.
+    // It is only necessary to test that the relevant inputs are reflected correctly at the output.
+    $display("A0 A1 In0 In1 In2 In3 | Out | Expected Output");
+    address0=0;address1=0;in0=1'b1;in1=1'bx;in2=1'bx;in3=1'bx; #1000
+    $display("%b  %b   %b   %b   %b   %b  |  %b  | 1", address0, address1, in0, in1, in2, in3, out);
+    address0=1;address1=0;in0=1'bx;in1=1'b1;in2=1'bx;in3=1'bx; #1000
+    $display("%b  %b   %b   %b   %b   %b  |  %b  | 1", address0, address1, in0, in1, in2, in3, out);
+    address0=0;address1=1;in0=1'bx;in1=1'bx;in2=1'b1;in3=1'bx; #1000
+    $display("%b  %b   %b   %b   %b   %b  |  %b  | 1", address0, address1, in0, in1, in2, in3, out);
+    address0=1;address1=1;in0=1'bx;in1=1'bx;in2=1'bx;in3=1'b1; #1000
+    $display("%b  %b   %b   %b   %b   %b  |  %b  | 1", address0, address1, in0, in1, in2, in3, out);
+    address0=0;address1=0;in0=1'b0;in1=1'bx;in2=1'bx;in3=1'bx; #1000
+    $display("%b  %b   %b   %b   %b   %b  |  %b  | 0", address0, address1, in0, in1, in2, in3, out);
+    address0=1;address1=0;in0=1'bx;in1=1'b0;in2=1'bx;in3=1'bx; #1000
+    $display("%b  %b   %b   %b   %b   %b  |  %b  | 0", address0, address1, in0, in1, in2, in3, out);
+    address0=0;address1=1;in0=1'bx;in1=1'bx;in2=1'b0;in3=1'bx; #1000
+    $display("%b  %b   %b   %b   %b   %b  |  %b  | 0", address0, address1, in0, in1, in2, in3, out);
+    address0=1;address1=1;in0=1'bx;in1=1'bx;in2=1'bx;in3=1'b0; #1000
+    $display("%b  %b   %b   %b   %b   %b  |  %b  | 0", address0, address1, in0, in1, in2, in3, out);
+    $finish();
+  end
 endmodule

multiplexer.v

@@ -1,5 +1,9 @@
 // Multiplexer circuit
 
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+
 module behavioralMultiplexer
 (
     output out,
@@ -19,6 +23,37 @@ module structuralMultiplexer
     input address0, address1,
     input in0, in1, in2, in3
 );
-    // Your multiplexer code here
+    wire nA0;
+    wire nA1;
+
+    wire isenabled0;
+    wire isenabled1;
+    wire isenabled2;
+    wire isenabled3;
+
+    wire enablein0;
+    wire enablein1;
+    wire enablein2;
+    wire enablein3;
+
+    wire out01;
+    wire out23;
+
+    `NOT A0inv(nA0, address0);
+    `NOT A1inv(nA1, address1);
+
+    `AND nA0andnA1(isenabled0, nA0, nA1);
+    `AND A0andnA1(isenabled1, address0, nA1);
+    `AND nA0andA1(isenabled2, nA0, address1);
+    `AND A0andA1(isenabled3, address0, address1);
+
+    `AND choose0(enablein0, isenabled0, in0);
+    `AND choose1(enablein1, isenabled1, in1);
+    `AND choose2(enablein2, isenabled2, in2);
+    `AND choose3(enablein3, isenabled3, in3);
+
+    `OR in0orin1(out01, enablein0, enablein1);
+    `OR in2orin3(out23, enablein2, enablein3);
+    `OR finalout(out, out01, out23);
 endmodule