Prava and Ariana Lab0 Submission

adder.t.v

@@ -0,0 +1,55 @@
+// Adder testbench
+`timescale 1 ns / 1 ps
+`include "adder.v"
+
+// Test a subset of the possible 2^8 inputs of the adder.
+module testFullAdder4bit();
+    reg [3:0] a;
+    reg [3:0] b;
+    wire [3:0] sum;
+    wire carryout, overflow;
+
+    FullAdder4bit adder (sum[3:0], carryout, overflow, a[3:0], b[3:0]);
+
+    initial begin
+    $dumpfile("adder.vcd");
+    $dumpvars();
+
+    // The 16 chosen test cases that match the inputs to the FPGA board.
+    $display(" A    B   | Cout Overflow   S  | Expected Output");
+    a='b0000;b='b0000; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 0 S: 0000 ", a, b, carryout, overflow, sum);
+    a='b1111;b='b1111; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 1 Overflow: 0 S: 1110 ", a, b, carryout, overflow, sum);
+    a='b1111;b='b0000; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 0 S: 1111 ", a, b, carryout, overflow, sum);
+    a='b0010;b='b0100; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 0 S: 0110 ", a, b, carryout, overflow, sum);
+    a='b1110;b='b1100; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 1 Overflow: 0 S: 1010 ", a, b, carryout, overflow, sum);
+    a='b0010;b='b1100; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 0 S: 1110 ", a, b, carryout, overflow, sum);
+    a='b0101;b='b0011; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 1 S: 1000 ", a, b, carryout, overflow, sum);
+    a='b1110;b='b0100; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 1 Overflow: 0 S: 0010 ", a, b, carryout, overflow, sum);
+    a='b1000;b='b0001; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 0 S: 1001 ", a, b, carryout, overflow, sum);
+    a='b0101;b='b0010; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 0 S: 0111 ", a, b, carryout, overflow, sum);
+    a='b1001;b='b1110; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 1 Overflow: 1 S: 0111 ", a, b, carryout, overflow, sum);
+    a='b1101;b='b1011; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 1 Overflow: 0 S: 1000 ", a, b, carryout, overflow, sum);
+    a='b0111;b='b0011; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 1 S: 1010 ", a, b, carryout, overflow, sum);
+    a='b1100;b='b1011; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 1 Overflow: 1 S: 0111 ", a, b, carryout, overflow, sum);
+    a='b0101;b='b0100; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 1 S: 1001 ", a, b, carryout, overflow, sum);
+    a='b0110;b='b0100; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 1 S: 1010 ", a, b, carryout, overflow, sum);
+
+    $finish();
+    end
+endmodule

adder.v

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+`define AND and #50
+`define XOR xor #50
+`define OR or #50
+
+// Implementation of a 1-bit full adder.
+module FullAdder1bit
+(
+    output sum, 
+    output carryout,
+    input a, 
+    input b, 
+    input carryin
+);
+    wire cout1;
+    wire cout2;
+    wire sumAB;
+
+    `XOR AxorB(sumAB, a, b);
+    `XOR sumABxorCin(sum, sumAB, carryin);
+
+    `AND AandB(cout1, a, b);
+    `AND sumABandCin(cout2, sumAB, carryin);
+
+    `OR orcarries(carryout, cout1, cout2);
+endmodule
+
+// Implementation of a 4-bit full adder. Four 1-bit full adders
+// are linked together in order to add 4-bit inputs. Each 1-bit 
+// adder outputs a single bit of the sum, and the carry out of 
+// each adder becomes the carryin input of the adder for the 
+// next significant bit.
+module FullAdder4bit
+(
+  output[3:0] sum,  // 2's complement sum of a and b
+  output carryout,  // Carry out of the summation of a and b
+  output overflow,  // True if the calculation resulted in an overflow
+  input[3:0] a,     // First operand in 2's complement format
+  input[3:0] b      // Second operand in 2's complement format
+);
+    wire carryout0;
+    wire carryout1;
+    wire carryout2;
+
+    // The carry in of this adder is always set to 0.
+    FullAdder1bit adder0 (sum[0], carryout0, a[0], b[0], 1'b0);
+
+    FullAdder1bit adder1 (sum[1], carryout1, a[1], b[1], carryout0);
+
+    FullAdder1bit adder2 (sum[2], carryout2, a[2], b[2], carryout1);
+
+    FullAdder1bit adder3 (sum[3], carryout, a[3], b[3], carryout2);
+
+    // An overflow occurs when the final carryout is not equal to the 
+    // carryin of the most significant bit.
+    `XOR oveflowdetection(overflow, carryout, carryout2);
+
+endmodule