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Done #12

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1a73867
init
ChrisssAring Sep 26, 2017
897c3fb
printing code works
Sep 26, 2017
23a4339
zybo_masster.xdc
Sep 26, 2017
77af8aa
finished testing and adder code
Sep 26, 2017
592fb78
added carryout2
Sep 26, 2017
d34c947
comments
ChrisssAring Sep 28, 2017
fc29ffb
finished tester
Sep 28, 2017
23b828c
merge complete
Sep 28, 2017
edd6236
done
Sep 28, 2017
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302 changes: 302 additions & 0 deletions 4badder
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Original file line number Diff line number Diff line change
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#! /usr/local/bin/vvp
:ivl_version "11.0 (devel)" "(s20150603-477-gc855b89)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "system";
:vpi_module "vhdl_sys";
:vpi_module "vhdl_textio";
:vpi_module "v2005_math";
:vpi_module "va_math";
S_0x2720c40 .scope module, "test4BitFullAdder" "test4BitFullAdder" 2 4;
.timescale -9 -12;
v0x2751770_0 .var "a", 3 0;
v0x2751850_0 .var "b", 3 0;
v0x27518f0_0 .net "carryout", 0 0, L_0x2753de0; 1 drivers
v0x27519e0_0 .net "carryout2", 0 0, L_0x2753490; 1 drivers
v0x2751a80_0 .net "overflow", 0 0, L_0x2754370; 1 drivers
v0x2751b70_0 .net "sum", 3 0, L_0x2753f40; 1 drivers
S_0x271f1f0 .scope module, "adder" "FullAdder4bit" 2 12, 3 27 0, S_0x2720c40;
.timescale -9 -12;
.port_info 0 /OUTPUT 4 "sum"
.port_info 1 /OUTPUT 1 "carryout"
.port_info 2 /OUTPUT 1 "carryout2"
.port_info 3 /OUTPUT 1 "overflow"
.port_info 4 /INPUT 4 "a"
.port_info 5 /INPUT 4 "b"
L_0x2754370/d .functor XOR 1, L_0x2753490, L_0x2753de0, C4<0>, C4<0>;
L_0x2754370 .delay 1 (50000,50000,50000) L_0x2754370/d;
v0x2750f40_0 .net "a", 3 0, v0x2751770_0; 1 drivers
v0x2751040_0 .net "b", 3 0, v0x2751850_0; 1 drivers
v0x2751120_0 .net "carryout", 0 0, L_0x2753de0; alias, 1 drivers
v0x27511f0_0 .net "carryout0", 0 0, L_0x2752240; 1 drivers
v0x27512e0_0 .net "carryout1", 0 0, L_0x2752bb0; 1 drivers
v0x2751420_0 .net "carryout2", 0 0, L_0x2753490; alias, 1 drivers
v0x2751510_0 .net "overflow", 0 0, L_0x2754370; alias, 1 drivers
v0x27515b0_0 .net "sum", 3 0, L_0x2753f40; alias, 1 drivers
L_0x27523f0 .part v0x2751770_0, 0, 1;
L_0x2752550 .part v0x2751850_0, 0, 1;
L_0x2752d10 .part v0x2751770_0, 1, 1;
L_0x2752e70 .part v0x2751850_0, 1, 1;
L_0x2753630 .part v0x2751770_0, 2, 1;
L_0x2753820 .part v0x2751850_0, 2, 1;
L_0x2753f40 .concat8 [ 1 1 1 1], L_0x2751d30, L_0x27526b0, L_0x2752f90, L_0x27539c0;
L_0x27541e0 .part v0x2751770_0, 3, 1;
L_0x27542d0 .part v0x2751850_0, 3, 1;
S_0x271c0b0 .scope module, "a0" "structFullAdder" 3 39, 3 8 0, S_0x271f1f0;
.timescale -9 -12;
.port_info 0 /OUTPUT 1 "sum"
.port_info 1 /OUTPUT 1 "carryout"
.port_info 2 /INPUT 1 "a"
.port_info 3 /INPUT 1 "b"
.port_info 4 /INPUT 1 "carryin"
L_0x2751c10/d .functor XOR 1, L_0x27523f0, L_0x2752550, C4<0>, C4<0>;
L_0x2751c10 .delay 1 (50000,50000,50000) L_0x2751c10/d;
L_0x7f2d2c679018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x2751d30/d .functor XOR 1, L_0x2751c10, L_0x7f2d2c679018, C4<0>, C4<0>;
L_0x2751d30 .delay 1 (50000,50000,50000) L_0x2751d30/d;
L_0x2751ee0/d .functor AND 1, L_0x27523f0, L_0x2752550, C4<1>, C4<1>;
L_0x2751ee0 .delay 1 (50000,50000,50000) L_0x2751ee0/d;
L_0x27520e0/d .functor AND 1, L_0x2751c10, L_0x7f2d2c679018, C4<1>, C4<1>;
L_0x27520e0 .delay 1 (50000,50000,50000) L_0x27520e0/d;
L_0x2752240/d .functor OR 1, L_0x27520e0, L_0x2751ee0, C4<0>, C4<0>;
L_0x2752240 .delay 1 (50000,50000,50000) L_0x2752240/d;
v0x2720970_0 .net "AandB", 0 0, L_0x2751ee0; 1 drivers
v0x274eca0_0 .net "AxorB", 0 0, L_0x2751c10; 1 drivers
v0x274ed60_0 .net "AxorBandCarryIn", 0 0, L_0x27520e0; 1 drivers
v0x274ee30_0 .net "a", 0 0, L_0x27523f0; 1 drivers
v0x274eef0_0 .net "b", 0 0, L_0x2752550; 1 drivers
v0x274f000_0 .net "carryin", 0 0, L_0x7f2d2c679018; 1 drivers
v0x274f0c0_0 .net "carryout", 0 0, L_0x2752240; alias, 1 drivers
v0x274f180_0 .net "sum", 0 0, L_0x2751d30; 1 drivers
S_0x274f2e0 .scope module, "a1" "structFullAdder" 3 40, 3 8 0, S_0x271f1f0;
.timescale -9 -12;
.port_info 0 /OUTPUT 1 "sum"
.port_info 1 /OUTPUT 1 "carryout"
.port_info 2 /INPUT 1 "a"
.port_info 3 /INPUT 1 "b"
.port_info 4 /INPUT 1 "carryin"
L_0x2752640/d .functor XOR 1, L_0x2752d10, L_0x2752e70, C4<0>, C4<0>;
L_0x2752640 .delay 1 (50000,50000,50000) L_0x2752640/d;
L_0x27526b0/d .functor XOR 1, L_0x2752640, L_0x2752240, C4<0>, C4<0>;
L_0x27526b0 .delay 1 (50000,50000,50000) L_0x27526b0/d;
L_0x27528a0/d .functor AND 1, L_0x2752d10, L_0x2752e70, C4<1>, C4<1>;
L_0x27528a0 .delay 1 (50000,50000,50000) L_0x27528a0/d;
L_0x2752a50/d .functor AND 1, L_0x2752640, L_0x2752240, C4<1>, C4<1>;
L_0x2752a50 .delay 1 (50000,50000,50000) L_0x2752a50/d;
L_0x2752bb0/d .functor OR 1, L_0x2752a50, L_0x27528a0, C4<0>, C4<0>;
L_0x2752bb0 .delay 1 (50000,50000,50000) L_0x2752bb0/d;
v0x274f560_0 .net "AandB", 0 0, L_0x27528a0; 1 drivers
v0x274f620_0 .net "AxorB", 0 0, L_0x2752640; 1 drivers
v0x274f6e0_0 .net "AxorBandCarryIn", 0 0, L_0x2752a50; 1 drivers
v0x274f7b0_0 .net "a", 0 0, L_0x2752d10; 1 drivers
v0x274f870_0 .net "b", 0 0, L_0x2752e70; 1 drivers
v0x274f980_0 .net "carryin", 0 0, L_0x2752240; alias, 1 drivers
v0x274fa20_0 .net "carryout", 0 0, L_0x2752bb0; alias, 1 drivers
v0x274fac0_0 .net "sum", 0 0, L_0x27526b0; 1 drivers
S_0x274fc50 .scope module, "a2" "structFullAdder" 3 41, 3 8 0, S_0x271f1f0;
.timescale -9 -12;
.port_info 0 /OUTPUT 1 "sum"
.port_info 1 /OUTPUT 1 "carryout"
.port_info 2 /INPUT 1 "a"
.port_info 3 /INPUT 1 "b"
.port_info 4 /INPUT 1 "carryin"
L_0x2752db0/d .functor XOR 1, L_0x2753630, L_0x2753820, C4<0>, C4<0>;
L_0x2752db0 .delay 1 (50000,50000,50000) L_0x2752db0/d;
L_0x2752f90/d .functor XOR 1, L_0x2752db0, L_0x2752bb0, C4<0>, C4<0>;
L_0x2752f90 .delay 1 (50000,50000,50000) L_0x2752f90/d;
L_0x2753180/d .functor AND 1, L_0x2753630, L_0x2753820, C4<1>, C4<1>;
L_0x2753180 .delay 1 (50000,50000,50000) L_0x2753180/d;
L_0x2753330/d .functor AND 1, L_0x2752db0, L_0x2752bb0, C4<1>, C4<1>;
L_0x2753330 .delay 1 (50000,50000,50000) L_0x2753330/d;
L_0x2753490/d .functor OR 1, L_0x2753330, L_0x2753180, C4<0>, C4<0>;
L_0x2753490 .delay 1 (50000,50000,50000) L_0x2753490/d;
v0x274fee0_0 .net "AandB", 0 0, L_0x2753180; 1 drivers
v0x274ffa0_0 .net "AxorB", 0 0, L_0x2752db0; 1 drivers
v0x2750060_0 .net "AxorBandCarryIn", 0 0, L_0x2753330; 1 drivers
v0x2750130_0 .net "a", 0 0, L_0x2753630; 1 drivers
v0x27501f0_0 .net "b", 0 0, L_0x2753820; 1 drivers
v0x2750300_0 .net "carryin", 0 0, L_0x2752bb0; alias, 1 drivers
v0x27503a0_0 .net "carryout", 0 0, L_0x2753490; alias, 1 drivers
v0x2750440_0 .net "sum", 0 0, L_0x2752f90; 1 drivers
S_0x27505d0 .scope module, "a3" "structFullAdder" 3 42, 3 8 0, S_0x271f1f0;
.timescale -9 -12;
.port_info 0 /OUTPUT 1 "sum"
.port_info 1 /OUTPUT 1 "carryout"
.port_info 2 /INPUT 1 "a"
.port_info 3 /INPUT 1 "b"
.port_info 4 /INPUT 1 "carryin"
L_0x2753950/d .functor XOR 1, L_0x27541e0, L_0x27542d0, C4<0>, C4<0>;
L_0x2753950 .delay 1 (50000,50000,50000) L_0x2753950/d;
L_0x27539c0/d .functor XOR 1, L_0x2753950, L_0x2753490, C4<0>, C4<0>;
L_0x27539c0 .delay 1 (50000,50000,50000) L_0x27539c0/d;
L_0x2753ad0/d .functor AND 1, L_0x27541e0, L_0x27542d0, C4<1>, C4<1>;
L_0x2753ad0 .delay 1 (50000,50000,50000) L_0x2753ad0/d;
L_0x2753c80/d .functor AND 1, L_0x2753950, L_0x2753490, C4<1>, C4<1>;
L_0x2753c80 .delay 1 (50000,50000,50000) L_0x2753c80/d;
L_0x2753de0/d .functor OR 1, L_0x2753c80, L_0x2753ad0, C4<0>, C4<0>;
L_0x2753de0 .delay 1 (50000,50000,50000) L_0x2753de0/d;
v0x2750830_0 .net "AandB", 0 0, L_0x2753ad0; 1 drivers
v0x2750910_0 .net "AxorB", 0 0, L_0x2753950; 1 drivers
v0x27509d0_0 .net "AxorBandCarryIn", 0 0, L_0x2753c80; 1 drivers
v0x2750aa0_0 .net "a", 0 0, L_0x27541e0; 1 drivers
v0x2750b60_0 .net "b", 0 0, L_0x27542d0; 1 drivers
v0x2750c70_0 .net "carryin", 0 0, L_0x2753490; alias, 1 drivers
v0x2750d10_0 .net "carryout", 0 0, L_0x2753de0; alias, 1 drivers
v0x2750db0_0 .net "sum", 0 0, L_0x27539c0; 1 drivers
.scope S_0x2720c40;
T_0 ;
%vpi_call 2 15 "$dumpfile", "fulladder.vcd" {0 0 0};
%vpi_call 2 16 "$dumpvars", 32'sb00000000000000000000000000000000, v0x2751770_0, v0x2751850_0, v0x2751b70_0, v0x27518f0_0, v0x27519e0_0, v0x2751a80_0 {0 0 0};
%vpi_call 2 19 "$display", " a | b | S C2 | COut | OverFlow | Sum | ECout | EOvrflow" {0 0 0};
%pushi/vec4 0, 0, 4;
%store/vec4 v0x2751770_0, 0, 4;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x2751850_0, 0, 4;
%delay 1000000, 0;
%load/vec4 v0x2751770_0;
%load/vec4 v0x2751850_0;
%load/vec4 v0x2751b70_0;
%vpi_call 2 23 "$display", " %d | %d | %d %b | %b | %b | 0 | 0 | 0 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0};
%pushi/vec4 15, 0, 4;
%store/vec4 v0x2751770_0, 0, 4;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x2751850_0, 0, 4;
%delay 1000000, 0;
%load/vec4 v0x2751770_0;
%load/vec4 v0x2751850_0;
%load/vec4 v0x2751b70_0;
%vpi_call 2 27 "$display", " %d | %d | %d %b | %b | %b | -2 | 1 | 0 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0};
%pushi/vec4 1, 0, 4;
%store/vec4 v0x2751770_0, 0, 4;
%pushi/vec4 1, 0, 4;
%store/vec4 v0x2751850_0, 0, 4;
%delay 1000000, 0;
%load/vec4 v0x2751770_0;
%load/vec4 v0x2751850_0;
%load/vec4 v0x2751b70_0;
%vpi_call 2 31 "$display", " %d | %d | %d %b | %b | %b | 2 | 0 | 0 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0};
%pushi/vec4 7, 0, 4;
%store/vec4 v0x2751770_0, 0, 4;
%pushi/vec4 9, 0, 4;
%store/vec4 v0x2751850_0, 0, 4;
%delay 1000000, 0;
%load/vec4 v0x2751770_0;
%load/vec4 v0x2751850_0;
%load/vec4 v0x2751b70_0;
%vpi_call 2 35 "$display", " %d | %d | %d %b | %b | %b | 0 | 1 | 0 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0};
%pushi/vec4 6, 0, 4;
%store/vec4 v0x2751770_0, 0, 4;
%pushi/vec4 14, 0, 4;
%store/vec4 v0x2751850_0, 0, 4;
%delay 1000000, 0;
%load/vec4 v0x2751770_0;
%load/vec4 v0x2751850_0;
%load/vec4 v0x2751b70_0;
%vpi_call 2 39 "$display", " %d | %d | %d %b | %b | %b | 4 | 1 | 0 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0};
%pushi/vec4 6, 0, 4;
%store/vec4 v0x2751770_0, 0, 4;
%pushi/vec4 5, 0, 4;
%store/vec4 v0x2751850_0, 0, 4;
%delay 1000000, 0;
%load/vec4 v0x2751770_0;
%load/vec4 v0x2751850_0;
%load/vec4 v0x2751b70_0;
%vpi_call 2 43 "$display", " %d | %d | %d %b | %b | %b |11(-5)| 0 | 1 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0};
%pushi/vec4 5, 0, 4;
%store/vec4 v0x2751770_0, 0, 4;
%pushi/vec4 9, 0, 4;
%store/vec4 v0x2751850_0, 0, 4;
%delay 1000000, 0;
%load/vec4 v0x2751770_0;
%load/vec4 v0x2751850_0;
%load/vec4 v0x2751b70_0;
%vpi_call 2 47 "$display", " %d | %d | %d %b | %b | %b | -2 | 0 | 0 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0};
%pushi/vec4 7, 0, 4;
%store/vec4 v0x2751770_0, 0, 4;
%pushi/vec4 3, 0, 4;
%store/vec4 v0x2751850_0, 0, 4;
%delay 1000000, 0;
%load/vec4 v0x2751770_0;
%load/vec4 v0x2751850_0;
%load/vec4 v0x2751b70_0;
%vpi_call 2 51 "$display", " %d | %d | %d %b | %b | %b |10(-6)| 0 | 1 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0};
%pushi/vec4 11, 0, 4;
%store/vec4 v0x2751770_0, 0, 4;
%pushi/vec4 11, 0, 4;
%store/vec4 v0x2751850_0, 0, 4;
%delay 1000000, 0;
%load/vec4 v0x2751770_0;
%load/vec4 v0x2751850_0;
%load/vec4 v0x2751b70_0;
%vpi_call 2 55 "$display", " %d | %d | %d %b | %b | %b |-10(6)| 1 | 1 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0};
%pushi/vec4 8, 0, 4;
%store/vec4 v0x2751770_0, 0, 4;
%pushi/vec4 8, 0, 4;
%store/vec4 v0x2751850_0, 0, 4;
%delay 1000000, 0;
%load/vec4 v0x2751770_0;
%load/vec4 v0x2751850_0;
%load/vec4 v0x2751b70_0;
%vpi_call 2 59 "$display", " %d | %d | %d %b | %b | %b |-16(0)| 1 | 1 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0};
%pushi/vec4 7, 0, 4;
%store/vec4 v0x2751770_0, 0, 4;
%pushi/vec4 8, 0, 4;
%store/vec4 v0x2751850_0, 0, 4;
%delay 1000000, 0;
%load/vec4 v0x2751770_0;
%load/vec4 v0x2751850_0;
%load/vec4 v0x2751b70_0;
%vpi_call 2 63 "$display", " %d | %d | %d %b | %b | %b | -1 | 0 | 0 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0};
%pushi/vec4 7, 0, 4;
%store/vec4 v0x2751770_0, 0, 4;
%pushi/vec4 7, 0, 4;
%store/vec4 v0x2751850_0, 0, 4;
%delay 1000000, 0;
%load/vec4 v0x2751770_0;
%load/vec4 v0x2751850_0;
%load/vec4 v0x2751b70_0;
%vpi_call 2 67 "$display", " %d | %d | %d %b | %b | %b |14(-2)| 0 | 1 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0};
%pushi/vec4 5, 0, 4;
%store/vec4 v0x2751770_0, 0, 4;
%pushi/vec4 2, 0, 4;
%store/vec4 v0x2751850_0, 0, 4;
%delay 1000000, 0;
%load/vec4 v0x2751770_0;
%load/vec4 v0x2751850_0;
%load/vec4 v0x2751b70_0;
%vpi_call 2 71 "$display", " %d | %d | %d %b | %b | %b | 7 | 0 | 0 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0};
%pushi/vec4 5, 0, 4;
%store/vec4 v0x2751770_0, 0, 4;
%pushi/vec4 3, 0, 4;
%store/vec4 v0x2751850_0, 0, 4;
%delay 1000000, 0;
%load/vec4 v0x2751770_0;
%load/vec4 v0x2751850_0;
%load/vec4 v0x2751b70_0;
%vpi_call 2 75 "$display", " %d | %d | %d %b | %b | %b |8(-8) | 0 | 1 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0};
%pushi/vec4 11, 0, 4;
%store/vec4 v0x2751770_0, 0, 4;
%pushi/vec4 13, 0, 4;
%store/vec4 v0x2751850_0, 0, 4;
%delay 1000000, 0;
%load/vec4 v0x2751770_0;
%load/vec4 v0x2751850_0;
%load/vec4 v0x2751b70_0;
%vpi_call 2 79 "$display", " %d | %d | %d %b | %b | %b | -8 | 1 | 0 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0};
%pushi/vec4 11, 0, 4;
%store/vec4 v0x2751770_0, 0, 4;
%pushi/vec4 12, 0, 4;
%store/vec4 v0x2751850_0, 0, 4;
%delay 1000000, 0;
%load/vec4 v0x2751770_0;
%load/vec4 v0x2751850_0;
%load/vec4 v0x2751b70_0;
%vpi_call 2 83 "$display", " %d | %d | %d %b | %b | %b |-9(7) | 1 | 1 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"adder.t.v";
"./adder.v";
33 changes: 33 additions & 0 deletions 4bitFullAdder.v
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`timescale 1 ns / 1 ps
`include "adder.v"

module test4BitFullAdder();
reg[3:0] a;
reg[3:0] b;
wire[3:0] sum;
wire carryout;
wire overflow;
integer i;
integer j;

FullAdder4bit adder(sum, carryout, overflow, a, b);

initial begin
$dumpfile("fulladder.vcd");
$dumpvars(0, a[3:0], b[3:0], sum[3:0], carryout, overflow);

$display(" a | b | S | COut | OverFlow");
for(i = -8; i < 8; i = i + 1)
begin
for(j = -8; j < 8; j = j + 1)
begin

a = i;
b = j;
#1000
$display(" %d | %d | %d | %b | %b ", $signed(a), $signed(b), $signed(sum), carryout, overflow);
end
end

end
endmodule
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