Kaitlyn & Serena Lab 0 Submission

Lab0Report.md

@@ -0,0 +1,63 @@
+# Lab 0 Report
+
+### Kaitlyn Keil and Serena Chen
+
+
+## Timing
+
+![](waveform.png)
+
+This is our waveform of all 16 test cases.
+
+![](waveform_1change.png)
+
+This is our waveform for one test case, as marked by the markers. No matter the inputs, it will always take 
+350 time units to propogate (given a constant 50 time units per gate). This is significantly faster than if we had decided to use AND gates, such as was demonstrated in class. Instead, we used XOR gates to minimize the steps to completion.
+
+## Verilog Tests
+
+![](truth_table_l1.png)
+
+This is the output for our test cases. We tried to test as many edge cases as possible, such as large negatives, large positives, adding negatives and positives, adding 0s and 1s, and various overflow scenarios. We started with the four cases in the in-class slides as a sanity check and to examine different overflow cases. From there, we went with a few base cases (0000+0000, 1111+1111) and other cases that seemed like they could cause issues (1111+0001, leading to (1)0000). The rest we filled with a variety of random cases.
+
+In terms of test cases failure, throughout the process of building the four bit adder, we had one failure, and that was due to the test case being incorrect (we checked on paper!).
+
+
+## FPGA Results
+
+![](a.jpg)
+![](b.jpg)
+
+We chose to represent the second item on our truth table (truth table above):
+
+a: 0101
+
+b: 0011
+
+expected sum: 1000
+
+expected overflow: 1
+
+expected carryout: 0
+
+The above pictures show a and b.
+
+![](sum.jpg)
+
+This shows the sum for a and b. As we expect, it is 1000.
+
+![](overflow_cout.jpg)
+
+This shows the values for overflow and carryout, in that order. As we expect, overflow is 1 and carryout is 0.
+
+We also ran our other tests from the truth table on the FPGA, and they were successful.
+
+## Vivado Resources
+
+![](timing.png)
+
+Vivado's analysis of the circuit timing aligns with our waveform above--if each time unit is 0.01 ns, then the worst case will be 3500 ns.
+
+![](summary_utils.png)
+
+The resources show that we have used very few look up tables and flip flops, and that most of the resources being utilized is in IO (buttons, switches, etc.).

adder.t.v

@@ -0,0 +1,49 @@
+// Adder testbench
+`timescale 1 ns / 1 ps
+`include "adder.v"
+
+module testFullAdder4bit();
+	reg[3:0] a, b; // Set up the buses
+	wire[3:0] sum;
+	wire carryout, overflow;
+
+	FullAdder4bit mut (sum, carryout, overflow, a, b);
+
+	initial begin
+		$dumpfile("fourbit_trace.vcd"); // Create a file to view waveforms
+    	$dumpvars;
+		$display("    A    B |    S Cout Over | Expected");
+		a=4'b0000; b=4'b0000; #1000
+		$display(" %b %b | %b    %b    %b | 0000 0 0", a, b , sum, carryout, overflow);
+		a=4'b0101; b=4'b0011; #1000
+		$display(" %b %b | %b    %b    %b | 1000 0 1", a, b , sum, carryout, overflow);
+		a=4'b1001; b=4'b1110; #1000
+		$display(" %b %b | %b    %b    %b | 0111 1 1", a, b , sum, carryout, overflow);
+		a=4'b0101; b=4'b0010; #1000
+		$display(" %b %b | %b    %b    %b | 0111 0 0", a, b , sum, carryout, overflow);
+		a=4'b1101; b=4'b1011; #1000
+		$display(" %b %b | %b    %b    %b | 1000 1 0", a, b , sum, carryout, overflow);
+		a=4'b1111; b=4'b1111; #1000
+		$display(" %b %b | %b    %b    %b | 1110 1 0", a, b , sum, carryout, overflow);
+		a=4'b1001; b=4'b0110; #1000
+		$display(" %b %b | %b    %b    %b | 1111 0 0", a, b , sum, carryout, overflow);
+		a=4'b1111; b=4'b0000; #1000
+		$display(" %b %b | %b    %b    %b | 1111 0 0", a, b , sum, carryout, overflow);
+		a=4'b1111; b=4'b0001; #1000
+		$display(" %b %b | %b    %b    %b | 0000 1 0", a, b , sum, carryout, overflow);
+		a=4'b0111; b=4'b0001; #1000
+		$display(" %b %b | %b    %b    %b | 1000 0 1", a, b , sum, carryout, overflow);
+		a=4'b0001; b=4'b0111; #1000
+		$display(" %b %b | %b    %b    %b | 1000 0 1", a, b , sum, carryout, overflow);
+		a=4'b0110; b=4'b0110; #1000
+		$display(" %b %b | %b    %b    %b | 1100 0 1", a, b , sum, carryout, overflow);
+		a=4'b1001; b=4'b1001; #1000
+		$display(" %b %b | %b    %b    %b | 0010 1 1", a, b , sum, carryout, overflow);
+		a=4'b1010; b=4'b0101; #1000
+		$display(" %b %b | %b    %b    %b | 1111 0 0", a, b , sum, carryout, overflow);
+		a=4'b1000; b=4'b1000; #1000
+		$display(" %b %b | %b    %b    %b | 0000 1 1", a, b , sum, carryout, overflow);
+		a=4'b0001; b=4'b0001; #1000
+		$display(" %b %b | %b    %b    %b | 0010 0 0", a, b , sum, carryout, overflow);
+	end
+endmodule

adder.v

@@ -0,0 +1,56 @@
+// Adder circuit
+
+// define gates with delays
+`define AND and #50
+`define OR or #50
+`define XOR xor #50
+`define NOT not #50
+
+module behavioralFullAdder // remainder from HW2
+(
+    output sum, 
+    output carryout,
+    input a, 
+    input b, 
+    input carryin
+);
+    // Uses concatenation operator and built-in '+'
+    assign {carryout, sum}=a+b+carryin;
+endmodule
+
+module structuralFullAdder // Full Adder using XOR gates
+(
+    output sum, // Single bit inputs and outputs
+    output carryout,
+    input a, 
+    input b, 
+    input carryin
+);
+
+    wire ab; // Calculate the sum
+    `XOR aXORb(ab, a, b);
+    `XOR abXORc(sum, ab, carryin);
+
+    wire aAndb, oneAndC; // Calculate the carryout (if it exists)
+    `AND aANDb(aAndb, a, b);
+    `AND aXORbANDc(oneAndC, ab, carryin);
+    `OR aorborc(carryout, aAndb, oneAndC);
+
+endmodule
+
+module FullAdder4bit
+(
+  output[3:0] sum, // 2's complement sum of a and b
+  output carryout, // Carry out of the summation of a and b
+  output overflow, // True if calc resulted in overflow
+  input[3:0] a,    // First operand in 2's complement format
+  input[3:0] b     // Second operand in 2's complement format
+);
+    wire carry0, carry1, carry2; // The only additional wires connect the FullAdder components, carryout to carryin.
+
+    structuralFullAdder add0 (sum[0], carry0, a[0], b[0], 0); // First adder will not have a carry in.
+    structuralFullAdder add1 (sum[1], carry1, a[1], b[1], carry0);
+    structuralFullAdder add2 (sum[2], carry2, a[2], b[2], carry1);
+    structuralFullAdder add3 (sum[3], carryout, a[3], b[3], carry2); // Final adder has the last carryout 
+    `XOR overflowCheck(overflow, carry2, carryout); // Returns 1 if there is overflow by comparing carryin and carryout of last adder
+endmodule

lab0_wrapper.v

@@ -25,6 +25,7 @@
 //--------------------------------------------------------------------------------
 
 `timescale 1ns / 1ps
+`include "adder.v"
 
 
 //--------------------------------------------------------------------------------