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Submission for Lab 0#7

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aehoppe wants to merge 18 commits intoCompArchFA17:masterfrom

Commits on Sep 26, 2017

Preliminary 4-bit adder implemented
Alexander
committed

Commits on Sep 27, 2017

implemented design, it does the work
Halliax
committed
Fleshed out outline for report and modified test bench
Alexander Hoppe
committed

Commits on Sep 28, 2017

updated results and vcd with worst case scenario
Halliax
committed
gate delay images
Halliax
committed
Drafted adder behavior section
Alexander Hoppe
committed
Merge branch 'master' of https://github.com/aehoppe/Lab0
Alexander Hoppe
committed
Added waveforms to writeup
Alexander Hoppe
committed
Added schematics of adders
Alexander Hoppe
committed
resized schematic images
Alexander Hoppe
committed
added test bench cases to writeup, test gif
Halliax
committed
fpga picture
Halliax
committed
Merge branch 'master' of https://github.com/aehoppe/Lab0
Halliax
committed
Added manual testing section
Alexander Hoppe
committed
Merge branch 'master' of https://github.com/aehoppe/Lab0
Alexander Hoppe
committed
Finished first draft with summary statistics section
Alexander Hoppe
committed
Reviewed writeup
Alexander Hoppe
committed

Commits on Oct 12, 2017

fixed bug I just noticed with some writeup images rendering
Halliax
committed