Submitting lab 0

adder.t.v

@@ -0,0 +1,50 @@
+// Adder testbench
+`timescale 1 ns / 1 ps
+`include "adder.v"
+
+module testFullAdder();
+    reg[3:0] a, b;
+    wire[3:0] sum;
+    wire carryout, overflow;
+
+    FullAdder4bit adder (sum, carryout, overflow, a, b);
+
+    initial begin
+	$dumpfile("adder.vcd");
+	$dumpvars();
+
+	$display("|   input     ||    expected    ||     actual     |");
+        $display("|  a   |  b   || sum  |cout|over|| sum  |cout|over|");
+	$display("positive numbers, no overflow:");
+	a=4'b0000; b=4'b0000; #1000
+        $display("| %b | %b || 0000 | 0  | 0  || %b | %b  | %b  |",
+		a, b, sum, carryout, overflow);
+	a=4'b0010; b=4'b0001; #1000
+        $display("| %b | %b || 0011 | 0  | 0  || %b | %b  | %b  |",
+		a, b, sum, carryout, overflow);
+	a=4'b0011; b=4'b0011; #1000
+        $display("| %b | %b || 0110 | 0  | 0  || %b | %b  | %b  |",
+		a, b, sum, carryout, overflow);
+	$display("negative numbers, no overflow");
+	a=4'b1111; b=4'b1111; #1000
+        $display("| %b | %b || 1110 | 1  | 0  || %b | %b  | %b  |",
+		a, b, sum, carryout, overflow);
+	a=4'b1110; b=4'b1011; #1000
+        $display("| %b | %b || 1001 | 1  | 0  || %b | %b  | %b  |",
+		a, b, sum, carryout, overflow);
+	$display("numbers with overflow");
+	a=4'b0101; b=4'b0011; #1000
+        $display("| %b | %b || 1000 | 0  | 1  || %b | %b  | %b  |",
+		a, b, sum, carryout, overflow);
+	a=4'b1011; b=4'b1100; #1000
+        $display("| %b | %b || 1000 | 1  | 1  || %b | %b  | %b  |",
+		a, b, sum, carryout, overflow);
+	$display("positive plus negative");
+	a=4'b1011; b=4'b0100; #1000
+        $display("| %b | %b || 1111 | 0  | 0  || %b | %b  | %b  |",
+		a, b, sum, carryout, overflow);
+	a=4'b1101; b=4'b0101; #1000
+        $display("| %b | %b || 0010 | 1  | 0  || %b | %b  | %b  |",
+		a, b, sum, carryout, overflow);
+    end
+endmodule

adder.v

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+`include "adder1.v"
+`define XOR xor #50
+`define XNOR xnor #50
+`define AND and #50
+
+module FullAdder4bit
+(
+  output[3:0] sum,  // 2's complement sum of a and b
+  output carryout,  // Carry out of the summation of a and b
+  output overflow,  // True if the calculation resulted in an overflow
+  input[3:0] a,     // First operand in 2's complement format
+  input[3:0] b      // Second operand in 2's complement format
+);
+    wire carry1, carry2, carry3;
+    wire finalbit, c;
+    // add the first bit with no carryin
+    oneBitAdder first (sum[0], carry1, a[0], b[0], 0);
+    // add second bit with carryout of first bit as carryin
+    oneBitAdder second (sum[1], carry2, a[1], b[1], carry1);
+    oneBitAdder third (sum[2], carry3, a[2], b[2], carry2); // repeat
+    oneBitAdder fourth (sum[3], carryout, a[3], b[3], carry3);
+
+    wire samesign, samecarry;
+    `XNOR signtest(samesign, a[3], b[3]); // test if inputs have same sign
+    `XOR carrytest(samecarry, carryout, sum[3]); // test if carryout=signbit
+    // overflow if signs are equal and carryout != signbit
+    `AND overflowtest(overflow, samesign, samecarry);
+
+endmodule

adder1.v

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+// Adder circuit
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+`define XOR xor #50
+
+module oneBitAdder
+(
+    output sum, 
+    output carryout,
+    input a, 
+    input b, 
+    input carryin
+);
+    wire ab;
+    wire bc;
+    wire ac;
+    // and together pairs of the three inputs
+    `AND aANDb(ab, a, b);
+    `AND bANDc(bc, b, carryin);
+    `AND aANDc(ac, a, carryin);
+
+    // if any set of two is true, there is a carryout
+    `OR cout(carryout, ab, bc, ac);
+    // the sum is just the three inputs XORed
+    `XOR sumout(sum, a, b, carryin);
+
+endmodule

report_with_gif.md

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+Here is the [link](https://docs.google.com/document/d/1BfObaH6k-D7BwtsVbR20D-WiawnhSjlH96COcq8jHgg/edit#heading=h.8s35myyhfxui) to the google docs with a video of FPGA working (gif instead of image).