Submit Henry and Toby Lab

WRITEUP.md

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+# Process
+We began by adapting verilog code for the full adder from homework 2 to create a four bit adder. After adding logic for overflow (XORing the MSB of the sum and the final carryout, then anding that with the xnor of the sign bits of both addends). Next we created a test suite to check that the implementation we had created was valid.
+After debugging the code used to generate the test suite for a while we were able to confirm that the output from the 4 bit adder matched the desired results.
+
+## Test Cases
+Instead of picking 16 test cases by hand we wrote a python program to exhaustively generate test cases. However, if we were to pick specific test cases we would probably pick ones that would overflow, and with positive and negative numbers, along with test cases that involve simpler operations to make sure normal operation is not overlooked.
+
+## Test Case Failures
+At first we had a faulty way of checking for overflow, which caused us to often identify overflow when adding a positive and negative number. When we anded our previous implementation with the xnor of the sign bits of the addend, that problem went away.
+
+# FPGA
+After fighting with Vivado for a while we were able to successfully upload the bitstream to the device. After that we tested the sum and flags by cycling through values on the FPGA and found that everything was operating as it was supposed to.
+## Timing
+![timing](https://github.com/TShapinsky/Lab0/blob/master/Timing.png?raw=true)
+## Power
+![Power](https://github.com/TShapinsky/Lab0/blob/master/Power.png?raw=true)
+## Utilization
+![utilization](https://github.com/TShapinsky/Lab0/blob/master/Utilization.png?raw=true)
+## DRC
+![DRC](https://github.com/TShapinsky/Lab0/blob/master/DRC.png?raw=true)
+
+
+# Waveforms
+
+![full_waveform](https://github.com/TShapinsky/Lab0/blob/master/full.png?raw=true)
+Waveform of all of our tests (all 2^8).
+![prop_delay](https://github.com/TShapinsky/Lab0/blob/master/prop_delay.png?raw=true)
+Waveform of a subsection of the tests showing the fluctuation between states after an input change.

adder.t.v

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+// define gates with delays
+`define AND and #50
+`define OR or #50
+`define XOR xor #50
+`define XNOR xnor #50
+
+// Adder testbench
+`timescale 1 ns / 1 ps
+`include "adder.v"
+
+module testFullAdder();
+    reg[3:0] a;
+    reg[3:0] b;
+    wire[3:0] sum;
+    wire carryout, overflow;
+
+    FullAdder4bit dut(sum, carryout, overflow, a, b);
+
+    initial begin
+    $dumpfile("adder.vcd");
+    $dumpvars(0, testFullAdder);
+    `include "test.v"
+    end
+endmodule

adder.v

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+// define gates with delays
+`define AND and #50
+`define OR or #50
+`define XOR xor #50
+`define XNOR xnor #50
+// Adder circuit
+
+module myHalfAdder(
+    output sum,
+    output carryout,
+    input a,
+    input b
+);
+    `XOR axorb(sum,a,b);
+    `AND aandb(carryout,a,b);
+endmodule
+
+module myFullAdder
+(
+    output sum,
+    output carryout,
+    input a,
+    input b,
+    input carryin
+);
+    wire s1;
+    wire c1;
+    wire c2;
+    myHalfAdder a1(s1,c1,a,b);
+    myHalfAdder a2(sum, c2, s1, carryin);
+    `OR (carryout, c1, c2);
+endmodule
+
+module FullAdder4bit
+(
+    output[3:0] sum,  // 2's complement sum of a and b
+    output carryout,  // Carry out of the summation of a and b
+    output overflow,  // True if the calculation resulted in an overflow
+    input[3:0] a,     // First operand in 2's complement format
+    input[3:0] b      // Second operand in 2's complement format
+);
+    wire c0;
+    wire c1;
+    wire c2;
+    wire w0;
+    wire w1;
+    myHalfAdder a0(sum[0], c0, a[0], b[0]);
+    myFullAdder a1(sum[1], c1, a[1], b[1], c0);
+    myFullAdder a2(sum[2], c2, a[2], b[2], c1);
+    myFullAdder a3(sum[3], carryout, a[3], b[3], c2);
+    `XOR(w0, sum[3], carryout);
+    `XNOR(w1, a[3], b[3]);
+    `AND(overflow, w0, w1);
+endmodule