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1eb52fd
1input Mux and and/nand in progress
LoganSweet Oct 6, 2017
f48615c
Fixed and/nand, added or/nor/xor
mjakus Oct 7, 2017
5c95cc1
AddSubSlt added but incomplete
LoganSweet Oct 7, 2017
f260248
full 1 bit attempted; failed
LoganSweet Oct 7, 2017
d88ff4b
Fixed adder/subtractor in bitslice
mjakus Oct 8, 2017
e733143
Worked on implementing 4 bit adder/subtractor
mjakus Oct 8, 2017
31c0ddd
Made four bit alu./test!
mjakus Oct 8, 2017
c798aeb
delete failed path
LoganSweet Oct 8, 2017
ab90137
Cleaned up code
mjakus Oct 9, 2017
93853f3
Making ALU test benches
mjakus Oct 9, 2017
a669e41
git debacle #1
LoganSweet Oct 10, 2017
48a73b3
git debacle #2
LoganSweet Oct 10, 2017
52f6c1b
added alu.v comments and formatting
LoganSweet Oct 10, 2017
f9a82a9
added top level module requirement scaffolding and note
LoganSweet Oct 10, 2017
ef7a3f0
Infinite git debacles
mjakus Oct 10, 2017
660ad20
Got zeros working
mjakus Oct 10, 2017
d0a7b7a
Added zeros test cases
mjakus Oct 10, 2017
c26a1fd
Added for timimg
mjakus Oct 10, 2017
7c670ec
Added for timimg part 2
mjakus Oct 10, 2017
25983a7
Maybe edits
mjakus Oct 10, 2017
9b0db36
Add VCD file
mjakus Oct 10, 2017
05282f1
Testing time
mjakus Oct 10, 2017
37ab443
Testing time
mjakus Oct 10, 2017
13ef3c9
Making moves re: SLT
mjakus Oct 10, 2017
dc52e1d
actually got slt working
mjakus Oct 10, 2017
a20b472
Maybe all that still needs to be done is commenting
mjakus Oct 11, 2017
daba44d
done with everything but cleanup/comments
mjakus Oct 11, 2017
79aa7c2
Cleaned &Done
mjakus Oct 12, 2017
4d4baa0
Lab Writeup Added
LoganSweet Oct 12, 2017
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Binary file added CompArch_Lab1_Jakus_Sweet.pdf
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174,756 changes: 174,756 additions & 0 deletions FullALU.vcd

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128 changes: 128 additions & 0 deletions OriginalTesting.t.v
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module testMultiplexer ();
wire AndNandOut;
reg A, B;
reg[2:0] Command;
//reg S;
wire OneBitFinalOut;
wire AddSubSLTSum, carryout, subtract; //overflow,
reg carryin;
wire OrNorXorOut;

//wire muxout;
//reg S0, S1;
//reg in0, in1, in2, in3;

wire Cmd0Start;
wire Cmd1Start;

wire nB;
wire BornB;
wire AxorB;
wire AandB;
wire CINandAxorB;

wire AnorB;
wire AorB;
wire AnandB;
wire nXor;
wire XorNor;

MiddleAddSubSLT testadd(AddSubSLTSum, carryout, subtract, A, B, Command, carryin);

AndNand newpotato(AndNandOut, A, B, Command);

OrNorXor ortest(OrNorXorOut, A, B, Command);

Bitslice yukongoldpotato(OneBitFinalOut, AddSubSLTSum, carryout, OrNorXorOut, AndNandOut, subtract, A, B, Command, carryin);


//FourInMux arbitrarypotato(muxout, S0, S1, in0, in1, in2, in3);

initial begin

// just the adder - proper behavior
$display("Adder/Subtractor");
$display("A B| Command | Output | Expected Output");
A=1;B=1;Command=3'b000; carryin = 0; #1000
$display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout);
A=1;B=1;Command=3'b001; carryin = 1; #1000
$display("%b %b | %b | %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout);

// testing subtraction
$display("One Bitslice Adder/Subtractor");
$display("A B| Command |Out|ExOut|Carryout");
A=1;B=1;Command=3'b000; carryin=0; #1000
$display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout);
A=1;B=0;Command=3'b000; carryin=0; #1000
$display("%b %b | %b | %b | 1 | %b", A, B, Command, OneBitFinalOut, carryout);
A=0;B=0;Command=3'b000; carryin=0; #1000
$display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout);

A=1;B=1;Command=3'b001; carryin=1; #1000
$display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout);
A=1;B=0;Command=3'b001; carryin=1; #1000
$display("%b %b | %b | %b | 1 | %b", A, B, Command, OneBitFinalOut, carryout);
A=0;B=0;Command=3'b001; carryin=1; #1000
$display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout);


//$display("A B| Command | Output | Expected Output- pure sadness");
//S0 = 1; S1 = 0; in0 = 1; in1 = 1; in2 = 0; in3 = 0; #1000
//$display("%b %b | %b %b %b %b | %b | 1", S0, S1, in0, in1, in2, in3, muxout);

// testing addition
$display("A B| Command | Output | Expected Output-sadness|Carryout");
A=1;B=1;Command=3'b000; carryin=0; #1000
$display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout);
A=1;B=0;Command=3'b000; carryin=0; #1000
$display("%b %b | %b | %b | 1 | %b", A, B, Command, OneBitFinalOut, carryout);
A=0;B=0;Command=3'b000; carryin=0; #1000
$display("%b %b | %b | %b | 0 | %b", A, B, Command, OneBitFinalOut, carryout);


// Exhaustively testing AND/NAND
$display("A B| Command | command0 Output | Expected Output - AND TESTS");
A=1;B=1;Command=3'b000; #1000
$display("%b %b | %b | %b %b | 1", A, B, Command, Command[0], AndNandOut);
A=1;B=1;Command=3'b001; #1000
$display("%b %b | %b | %b %b | 0", A, B, Command, Command[1], AndNandOut);
A=0;B=1;Command=3'b000; #1000
$display("%b %b | %b | %b %b | 0", A, B, Command, Command[0], AndNandOut);
A=1;B=0;Command=3'b001; #1000
$display("%b %b | %b | %b %b | 1", A, B, Command, Command[1], AndNandOut);


// Exhaustively testing OR/NOR/XOR
$display("A B | Command | Output | Expected Output - OR TESTS");
A=1; B=1; Command=3'b111; #1000
$display("%b %b | %b | %b | 1 - OR TEST", A, B, Command, OrNorXorOut);
A=1; B=0; Command=3'b111; #1000
$display("%b %b | %b | %b | 1 - OR TEST", A, B, Command, OrNorXorOut);
A=0; B=1; Command=3'b111; #1000
$display("%b %b | %b | %b | 1 - OR TEST", A, B, Command, OrNorXorOut);
A=0; B=0; Command=3'b111; #1000
$display("%b %b | %b | %b | 0 - OR TEST", A, B, Command, OrNorXorOut);


A=1; B=1; Command=3'b110; #1000
$display("%b %b | %b | %b | 0 - NOR TEST", A, B, Command, OrNorXorOut);
A=1; B=0; Command=3'b110; #1000
$display("%b %b | %b | %b | 0 - NOR TEST", A, B, Command, OrNorXorOut);
A=0; B=1; Command=3'b110; #1000
$display("%b %b | %b | %b | 0 - NOR TEST", A, B, Command, OrNorXorOut);
A=0; B=0; Command=3'b110; #1000
$display("%b %b | %b | %b | 1 - NOR TEST", A, B, Command, OrNorXorOut);

A=1; B=1; Command=3'b010; #1000
$display("%b %b | %b | %b | 0 - XOR TEST", A, B, Command, OrNorXorOut);
A=1; B=0; Command=3'b010; #1000
$display("%b %b | %b | %b | 1 - XOR TEST", A, B, Command, OrNorXorOut);
A=0; B=1; Command=3'b010; #1000
$display("%b %b | %b | %b | 1 - XOR TEST", A, B, Command, OrNorXorOut);
A=0; B=0; Command=3'b010; #1000
$display("%b %b | %b | %b | 0 - XOR TEST", A, B, Command, OrNorXorOut);

end

endmodule
165 changes: 0 additions & 165 deletions README.md

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