Submission for Lab 1

LUTs.v

@@ -0,0 +1,71 @@
+// defining command numbers
+`define ADD  3'd0
+`define SUB  3'd1
+`define XOR  3'd2
+`define SLT  3'd3
+`define AND  3'd4
+`define NAND 3'd5
+`define NOR  3'd6
+`define OR   3'd7
+
+// implementing a control logic LUT to determine ALU operation
+module ALUcontrolLUT
+(
+output reg[2:0] 	muxindex,
+output reg	invertB,
+output reg	othercontrolsignal,
+input[2:0]	ALUcommand
+);
+
+  always @(ALUcommand) begin
+    case (ALUcommand)
+      `ADD:  begin muxindex = 0; invertB=0; othercontrolsignal = 0; end
+      `SUB:  begin muxindex = 0; invertB=1; othercontrolsignal = 0; end
+      `XOR:  begin muxindex = 1; invertB=0; othercontrolsignal = 0; end
+      `SLT:  begin muxindex = 2; invertB=0; othercontrolsignal = 0; end
+      `AND:  begin muxindex = 3; invertB=0; othercontrolsignal = 0; end
+      `NAND: begin muxindex = 3; invertB=0; othercontrolsignal = 1; end
+      `NOR:  begin muxindex = 4; invertB=0; othercontrolsignal = 1; end
+      `OR:   begin muxindex = 4; invertB=0; othercontrolsignal = 0; end
+    endcase
+  end
+endmodule
+
+`define ADD/SUB 3'd0
+`define XOR 3'd1
+`define SLT 3'd2
+`define AND/NAND 3'd3
+`define NOR/OR 3'd4
+
+module ALUoutputLUT
+(
+input[2:0] muxindex,
+input invertB,
+input othercontrolsignal,
+output[31:0] result,
+output carryout,
+output overflow,
+output zero
+);
+wire resAddsub[31:0];
+wire resXor[31:0];
+wire resSlt[31:0];
+wire resAndnand[31:0];
+wire resNoror[31:0];
+
+32bit_addsub dut (resAddsub, carryout, zero, overflow, operandA, operandB, invertB);
+32bit_xor dut (resXor, carryout, zero, overflow, operandA, operandB);
+32bit_slt dut (resSlt, carryout, zero, overflow, operandA, operandB);
+32bit_andnand dut (resAndnand, carryout, zero, overflow, operandA, operandB, othercontrolsignal);
+32bit_andnand dut (resNoror, carryout, zero, overflow, operandA, operandB, othercontrolsignal);
+
+  always @(muxindex) begin
+    case(muxindex)
+      `ADD/SUB: begin result = resAddsub; end
+      `XOR: begin result = ; end
+      `SLT: begin result = ; end
+      `AND/NAND: begin result = ; end
+      `NOR/OR: begin result = ; end
+    endcase
+  end
+endmodule

alu.t.v

@@ -0,0 +1,135 @@
+// ALU testbench
+`include "alu.v"
+
+module testalu ();
+reg[31:0] operandA;
+reg[31:0] operandB;
+reg[2:0] command;
+
+wire[31:0] result;
+wire carryout;
+wire zero;
+wire overflow;
+
+ ALU alu(result, carryout, zero, overflow, operandA, operandB, command);
+
+  initial begin
+    $dumpfile("alu.vcd");
+    $dumpvars();
+    // add test cases
+    $display("Add test cases");
+    // Case 1: Inputs consist of all 0s.
+    operandA = 32'b00000000000000000000000000000000; operandB = 32'b00000000000000000000000000000000; command = 3'b000; #1500
+    if (result !== 32'b00000000000000000000000000000000) $display("Add test case 1 result failed.\nExpected result: %b\tActual result: %b", 32'd0, result);
+    if (carryout !== 0) $display("Add test case 1 Cout failed\nExpected Cout: %b\tActual Cout: %b", 1'b0, carryout);
+    if (overflow !== 0) $display("Add test case 1 Overflow failed\nExpected Overflow: %b\tActual Overflow: %b", 1'b0, overflow);
+    if (zero !== 1) $display("Add test case 1 Zero failed\nExpected Zero: %b\tActual Zero: %b",  1'b1, zero);
+
+    // Case 2: Inputs consist of all 1s.
+    operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; command = 3'b000; #1500
+    if (result != 32'b11111111111111111111111111111110) $display("Add test case 2 result failed.\nExpected result: %b\tActual result: %b", 32'b11111111111111111111111111111110, result);
+    if (carryout !== 1) $display("Add test case 2 Cout failed\nExpected Cout: %b\tActual Cout: %b", 1'b1, carryout);
+    if (overflow !== 0) $display("Add test case 2 Overflow failed\nExpected Overflow: %b\tActual Overflow: %b", 1'b0, overflow);
+    if (zero !== 0) $display("Add test case 2 Zero failed\nExpected Zero: %b\tActual Zero: %b",  1'b0, zero);
+
+    // Case 3: Overflow and Carryout.
+    operandA = 32'b10000011111111111111111111111111; operandB = 32'b10111111111111111111111111111111; command = 3'b000; #1500
+    if (result != 32'b01000011111111111111111111111110) $display("Add test case 3 result failed.\nExpected result: %b\tActual result: %b", 32'b01000011111111111111111111111110, result);
+    if (carryout !== 1) $display("Add test case 3 Cout failed\nExpected Cout: %b\tActual Cout: %b", 1'b1, carryout);
+    if (overflow !== 1) $display("Add test case Overflow failed\nExpected Overflow: %b\tActual Overflow: %b", 1'b1, overflow);
+    if (zero !== 0) $display("Add test case Zero failed\nExpected Zero: %b\tActual Zero: %b",  1'b0, zero);
+
+    // Case 4: Overflow only.
+    operandA = 32'b01000000000000000000000000001110; operandB = 32'b01000000000000000000000000001100; command = 3'b000; #1500
+    if (result != 32'b10000000000000000000000000011010) $display("Add test case 4 result failed.\nExpected result: %b\tActual result: %b", 32'b10000000000000000000000000011010, result);
+    if (carryout !== 0) $display("Add test case 4 Cout failed\nExpected Cout: %b\tActual Cout: %b", 1'b1, carryout);
+    if (overflow !== 1) $display("Add test case 4 Overflow failed\nExpected Overflow: %b\tActual Overflow: %b", 1'b1, overflow);
+    if (zero !== 0) $display("Add test case 4 Zero failed\nExpected Zero: %b\tActual Zero: %b",  1'b0, zero);
+
+    // subtract test cases
+    $display("Subtract test cases");
+    // Case 1: All zeros
+    operandA = 32'b00000000000000000000000000000000; operandB = 32'b00000000000000000000000000000000; command = 3'b001; #1500
+    if (result !== 32'b00000000000000000000000000000000) $display("Subtract test case 1 result failed.\nExpected result: %b\tActual result: %b", 32'd0, result);
+    if (carryout !== 0) $display("Subtract test case 1 Cout failed\nExpected Cout: %b\tActual Cout: %b", 1'b1, carryout);
+    if (overflow !== 1) $display("Subtract test case 1 Overflow failed\nExpected Overflow: %b\tActual Overflow: %b", 1'b0, overflow);
+    if (zero !== 1) $display("Subtract test case 1 Zero failed\nExpected Zero: %b\tActual Zero: %b",  1'b1, zero);
+
+    // Case 2: Subtract a negative number
+    operandA = 32'b00000000000000000000000000000000; operandB = 32'b11111111111111111111111111111111; command = 3'b001; #1500
+    if (result !== 32'b00000000000000000000000000000001) $display("Subtract test case 2 result failed.\nExpected result: %b\tActual result: %b", 32'b00000000000000000000000000000001, result);
+    if (carryout !== 0) $display("Subtract test case 2 Cout failed\nExpected Cout: %b\tActual Cout: %b", 1'b0, carryout);
+    if (overflow !== 0) $display("Subtract test case 2 Overflow failed\nExpected Overflow: %b\tActual Overflow: %b", 1'b0, overflow);
+    if (zero !== 0) $display("Subtract test case 2 Zero failed\nExpected Zero: %b\tActual Zero: %b",  1'b0, zero);
+
+    // Case 3: Subtract a positive number
+    operandA = 32'b00000000000000000000000000000000; operandB = 32'b00011111111111111111111111111111; command = 3'b001; #1500
+    if (result !== 32'b11100000000000000000000000000001) $display("Subtract test case 2 result failed.\nExpected result: %b\tActual result: %b", 32'b11100000000000000000000000000001, result);
+    if (carryout !== 0) $display("Subtract test case 2 Cout failed\nExpected Cout: %b\tActual Cout: %b", 1'b0, carryout);
+    if (overflow !== 0) $display("Subtract test case 2 Overflow failed\nExpected Overflow: %b\tActual Overflow: %b", 1'b0, overflow);
+    if (zero !== 0) $display("Subtract test case 2 Zero failed\nExpected Zero: %b\tActual Zero: %b",  1'b0, zero);
+
+    // Xor test cases
+    // two inputs the same; two inputs totally different; two inputs with some bits corresponding
+    operandA = 32'b01010101010101010101010101010101; operandB = 32'b01010101010101010101010101010101; command = 3'b010; #1500
+    if (result !== 32'b00000000000000000000000000000000) $display("Xor test case 1 (inputs same) failed");
+    operandA = 32'b01010101010101010101010101010101; operandB = 32'b10101010101010101010101010101010; command = 3'b010; #1500
+    if (result !== 32'b11111111111111111111111111111111) $display("Xor test case 2 (inputs different) failed");
+    operandA = 32'b01010101010101010101010101010101; operandB = 32'b01011010010110100101101001011010; command = 3'b010; #1500
+    if (result !== 32'b00001111000011110000111100001111) $display("Xor test case 3 (inputs somewhat corresponding) failed");
+
+    // SLT test cases
+    // inputs greater than, less than, equal to; for positive, negatives, and combinations of each
+    operandA = 32'd5000; operandB = 32'd100; command = 3'b011; #1500
+    if (result !== 32'b00000000000000000000000000000000) $display("SLT test case 1 (postive greater) failed");
+    operandA = 32'd50; operandB = 32'd100; command = 3'b011; #1500
+    if (result !== 32'b00000000000000000000000000000001) $display("SLT test case 1 (postive less) failed");
+    operandA = 32'd100; operandB = 32'd100; command = 3'b011; #1500
+    if (result !== 32'b00000000000000000000000000000000) $display("SLT test case 3 (postive equal) failed");
+    operandA = -32'd5000; operandB = -32'd100; command = 3'b011; #1500
+    if (result !== 32'b00000000000000000000000000000001) $display("SLT test case 4 (negative less) failed");
+    operandA = -32'd100; operandB = -32'd5000; command = 3'b011; #1500
+    if (result !== 32'b00000000000000000000000000000000) $display("SLT test case 5 (negative greater) failed");
+    operandA = -32'd100; operandB = 32'd100; command = 3'b011; #1500
+    if (result !== 32'b00000000000000000000000000000001) $display("SLT test case 6 (negative and positive) failed");
+    operandA = 32'd100; operandB = -32'd100; command = 3'b011; #1500
+    if (result !== 32'b00000000000000000000000000000000) $display("SLT test case 7 (positive and negative) failed");
+
+    // And test cases
+    // two inputs exactly the same; two inputs totally different; two inputs with some bits corresponding
+    operandA = 32'b01010101010101010101010101010101; operandB = 32'b01010101010101010101010101010101; command = 3'b100; #1500
+    if (result !== 32'b01010101010101010101010101010101) $display("And test case 1 (inputs same) failed");
+    operandA = 32'b01010101010101010101010101010101; operandB = 32'b10101010101010101010101010101010; command = 3'b100; #1500
+    if (result !== 32'b00000000000000000000000000000000) $display("And test case 2 (inputs different) failed");
+    operandA = 32'b01010101010101010101010101010101; operandB = 32'b01011010010110100101101001011010; command = 3'b100; #1500
+    if (result !== 32'b01010000010100000101000001010000) $display("And test case 3 (inputs somewhat corresponding) failed");
+
+    // Nand test cases
+    // two inputs exactly the same; two inputs totally different; two inputs with some bits corresponding
+    operandA = 32'b01010101010101010101010101010101; operandB = 32'b01010101010101010101010101010101; command = 3'b101; #1500
+    if (result !== 32'b10101010101010101010101010101010) $display("Nand test case 1 (inputs same) failed");
+    operandA = 32'b01010101010101010101010101010101; operandB = 32'b10101010101010101010101010101010; command = 3'b101; #1500
+    if (result !== 32'b11111111111111111111111111111111) $display("Nand test case 2 (inputs different) failed");
+    operandA = 32'b01010101010101010101010101010101; operandB = 32'b01011010010110100101101001011010; command = 3'b101; #1500
+    if (result !== 32'b10101111101011111010111110101111) $displayb("Nand test case 3 (inputs somewhat corresponding) failed");
+
+    // Nor test cases
+    // two inputs exactly the same; two inputs totally different; two inputs with some bits corresponding
+    operandA = 32'b01010101010101010101010101010101; operandB = 32'b01010101010101010101010101010101; command = 3'b111; #1500
+    if (result !== 32'b10101010101010101010101010101010) $display("Nor test case 1 (inputs same) failed");
+    operandA = 32'b01010101010101010101010101010101; operandB = 32'b10101010101010101010101010101010; command = 3'b111; #1500
+    if (result !== 32'b00000000000000000000000000000000) $display("Nor test case 2 (inputs different) failed");
+    operandA = 32'b01010101010101010101010101010101; operandB = 32'b01011010010110100101101001011010; command = 3'b111; #1500
+    if (result !== 32'b10100000101000001010000010100000) $display("Nor test case 3 (inputs somewhat corresponding) failed");
+
+    // Or test cases
+    // two inputs exactly the same; two inputs totally different; two inputs with some bits corresponding
+    operandA = 32'b01010101010101010101010101010101; operandB = 32'b01010101010101010101010101010101; command = 3'b110; #1500
+    if (result !== 32'b01010101010101010101010101010101) $display("Or test case 1 (inputs same) failed");
+    operandA = 32'b01010101010101010101010101010101; operandB = 32'b10101010101010101010101010101010; command = 3'b110; #1500
+    if (result !== 32'b11111111111111111111111111111111) $display("Or test case 2 (inputs different) failed");
+    operandA = 32'b01010101010101010101010101010101; operandB = 32'b01011010010110100101101001011010; command = 3'b110; #1500
+    if (result !== 32'b01011111010111110101111101011111) $display("Or test case 3 (inputs somewhat corresponding) failed");
+    $finish();
+end
+endmodule // testalu

alu.v

@@ -0,0 +1,128 @@
+// Implementation of an ALU that performs addition, subtraction, XOR, SLT, OR, NOR, NAND, and AND operations.
+
+`include "operations.v"
+
+// Definine command numbers
+`define CADD  3'd0
+`define CSUB  3'd1
+`define CXOR  3'd2
+`define CSLT  3'd3
+`define CAND  3'd4
+`define CNAND 3'd5
+`define CNOR  3'd6
+`define COR   3'd7
+
+// Implementation of a control logic LUT to determine ALU operation.
+module ALUcontrolLUT
+(
+output reg[2:0] 	muxindex,
+output reg	invertB,
+output reg	othercontrolsignal,
+input[2:0]	ALUcommand
+);
+
+  always @(ALUcommand) begin
+    case (ALUcommand)
+      `CADD:  begin muxindex = 0; invertB=0; othercontrolsignal = 0; end
+      `CSUB:  begin muxindex = 0; invertB=1; othercontrolsignal = 0; end
+      `CXOR:  begin muxindex = 1; invertB=0; othercontrolsignal = 0; end
+      `CSLT:  begin muxindex = 2; invertB=0; othercontrolsignal = 0; end
+      `CAND:  begin muxindex = 3; invertB=0; othercontrolsignal = 0; end
+      `CNAND: begin muxindex = 3; invertB=0; othercontrolsignal = 1; end
+      `CNOR:  begin muxindex = 4; invertB=0; othercontrolsignal = 1; end
+      `COR:   begin muxindex = 4; invertB=0; othercontrolsignal = 0; end
+    endcase
+  end
+endmodule
+
+// Define macros for second LUT.
+`define MADDSUB 3'd0
+`define MXOR 3'd1
+`define MSLT 3'd2
+`define MANDNAND 3'd3
+`define MNOROR 3'd4
+
+// Decide which operation results to output based on the results of the index 
+// generated by the control LUT.
+module ALUoutputLUT
+(
+input[31:0] operandA,
+input[31:0] operandB,
+input[2:0] muxindex,
+input invertB,
+input othercontrolsignal,
+output reg[31:0] result,
+output reg carryout,
+output reg zero,
+output reg overflow
+);
+
+// The results of each module.
+wire[31:0] resAddsub;
+wire[31:0] resXor;
+wire[31:0] resSlt;
+wire[31:0] resAndnand;
+wire[31:0] resNoror;
+
+// The carryout flags of each module.
+wire carryoutAddSub;
+wire carryoutXor;
+wire carryoutSLT;
+wire carryoutAND;
+wire carryoutOR;
+
+// The zero flags of each module.
+wire zeroAddSub;
+wire zeroXor;
+wire zeroSLT;
+wire zeroAND;
+wire zeroOR;
+
+// The overflow flags of each module.
+wire overflowAddSub;
+wire overflowXor;
+wire overflowSLT;
+wire overflowAND;
+wire overflowOR;
+
+AddSub #1000 dut0 (resAddsub, carryoutAddSub, zeroAddSub, overflowAddSub, operandA, operandB, invertB);
+alu32bitxor dut1 (resXor, carryoutXor, zeroXor, overflowXor, operandA, operandB);
+alu32bitslt dut2 (resSlt, carryoutSLT, zeroSLT, overflowSLT, operandA, operandB);
+alu32bitandn dut3 (resAndnand, carryoutAND, zeroAND, overflowAND, operandA, operandB, othercontrolsignal);
+NOROR dut4 (resNoror, carryoutOR, zeroOR, overflowOR, operandA, operandB, othercontrolsignal);
+
+// The LUT behaves as a set of muxes that choose each bit of the result and each flag based on the muxindex 
+// it is passed as an address.
+always @(muxindex or resAddsub or resXor or resSlt or resAndnand or resNoror) begin
+ case(muxindex)
+    `MADDSUB: begin  result = resAddsub;   carryout = carryoutAddSub;  zero = zeroAddSub;  overflow = overflowAddSub; end
+    `MXOR: begin     result = resXor;      carryout = carryoutXor;     zero = zeroXor;     overflow = overflowXor; end
+    `MSLT: begin     result = resSlt;      carryout = carryoutSLT;     zero = zeroSLT;     overflow = overflowSLT; end
+    `MANDNAND: begin result = resAndnand;  carryout = carryoutAND;     zero = zeroAND;     overflow = overflowAND; end
+    `MNOROR: begin   result = resNoror;    carryout = carryoutOR;      zero = zeroOR;      overflow = overflowOR; end
+  endcase
+end
+
+endmodule
+
+// Implementation of the ALU in it's entirety.
+module ALU
+(
+output[31:0]  result,
+output        carryout,
+output        zero,
+output        overflow,
+input[31:0]   operandA,
+input[31:0]   operandB,
+input[2:0]    command
+);
+
+wire[2:0]   muxindex;
+wire  invertB;
+wire othercontrolsignal;
+
+ALUcontrolLUT controlLookup (muxindex, invertB, othercontrolsignal, command);
+
+ALUoutputLUT outputLookup (operandA, operandB, muxindex, invertB, othercontrolsignal, result, carryout, zero, overflow);
+
+endmodule