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595651b
Finished the work plan
bwerth Oct 4, 2017
346a166
single alu test bench
wiltang Oct 7, 2017
7b2b9b9
Finished Single Bit ALU
bwerth Oct 11, 2017
4bf8853
Fixed the Test Bench
bwerth Oct 11, 2017
62fab5d
Changed the module call
bwerth Oct 11, 2017
30e8e51
Finished
bwerth Oct 11, 2017
3fdd5c7
Clarified Things
bwerth Oct 11, 2017
42cadc4
Made the single bit test bench a little bit more user friendly
bwerth Oct 11, 2017
6d3691b
full alu
wiltang Oct 11, 2017
9835302
merged alu_single_bit.v
wiltang Oct 11, 2017
1f8ddc3
alu.v
wiltang Oct 11, 2017
10ad6ab
Delete alusingle.t.v
bwerth Oct 11, 2017
064766d
updated alu.v
wiltang Oct 12, 2017
5a56e5b
alu.v updated
wiltang Oct 12, 2017
6ff0a08
Finished the test bench
bwerth Oct 12, 2017
155dfbc
Updated Lab1 w/many errors
wiltang Oct 12, 2017
008546e
Merge branch 'master' of https://github.com/bwerth/Lab1
bwerth Oct 12, 2017
a6a5061
Down to three errors
bwerth Oct 12, 2017
8c10d6c
updated alu.v + test bench
wiltang Oct 12, 2017
6158866
Test Bench Worked
bwerth Oct 12, 2017
848d478
Changes were made
bwerth Oct 13, 2017
b9354fc
merging alu.v
wiltang Oct 13, 2017
85ad590
merging alu.v
wiltang Oct 13, 2017
163e26f
Logic gates and zero finished
bwerth Oct 13, 2017
0303da1
slt sub
wiltang Oct 13, 2017
90d1dec
Merge branch 'master' of https://github.com/bwerth/Lab1
bwerth Oct 13, 2017
9c54b0e
problems w/ carryout
wiltang Oct 13, 2017
eee5349
Finished
bwerth Oct 13, 2017
075a3f9
timing delays added
wiltang Oct 13, 2017
ac33205
Finished
bwerth Oct 13, 2017
5ca5a03
Photos
bwerth Oct 13, 2017
ec594ef
report
wiltang Oct 13, 2017
86fa8fa
report
wiltang Oct 13, 2017
3b759b1
report
wiltang Oct 13, 2017
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108 changes: 108 additions & 0 deletions alu.t.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,108 @@
`include "alu.v"

module testALU ();
reg [31:0] operandA, operandB;
reg [2:0] command;
reg [9:0] numBroken = 0;
wire [31:0] result;
wire carryout, ofl, zero;

ALU testALU(.result (result), .carryout (carryout), .overflow (ofl), .zero (zero), .operandA (operandA), .operandB (operandB), .command (command));

task checkTestCase;
input [31:0] expectedResult;
input expectedCarryout, expectedOfl, expectedZero;

begin
$display("Testing command %b, operandA %b, and operandB %b", command, operandA, operandB);
if (result == expectedResult) begin
$display("Test Passed, result is %b, carryout is %b, ofl is %b, and zero is %b", result, carryout, ofl, zero);
end else begin
numBroken = numBroken + 1;
$display("ERROR: Expected %b for result, %b for carryout, %b for ofl, and %b for zero, but actual output was %b, actual carryout was %b, actual ofl was %b, and actual zero is %b", expectedResult, expectedCarryout, expectedOfl, expectedZero, result, carryout, ofl, zero);
end
end
endtask

initial begin

//Add
command = 0; operandA = 0; operandB = 0; #2900
checkTestCase(0, 0, 0, 1);
command = 0; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; #2910
checkTestCase(32'b11111111111111111111111111111110, 1, 0, 0);
command = 0; operandA = 32'b10000000000000000000000000000001; operandB = 32'b01111111111111111111111111111111; #2910
checkTestCase(0, 1, 0, 1);
command = 0; operandA = 32'b10000000000000000000000000000000; operandB = 32'b10000000000000000000000000000000; #2910
checkTestCase(0, 1, 1, 1);
command = 0; operandA = 32'b11010101010101010101011010101010; operandB = 32'b00000001111111111111111101101010; #2910
checkTestCase(32'b11010111010101010101011000010100, 0, 0, 0);

//Sub
command = 1; operandA = 0; operandB = 0; #5800
checkTestCase(0, 0, 0, 1);
command = 1; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000001; #5810
checkTestCase(32'b11111111111111111111111111111110, 1, 0, 0);
command = 1; operandA = 32'b10000000000000000000000000000001; operandB = 32'b10000000000000000000000000000001; #5810
checkTestCase(0, 1, 0, 1);
command = 1; operandA = 32'b10000000000000000000000000000000; operandB = 32'b10000000000000000000000000000000; #5810
checkTestCase(0, 1, 1, 1);
command = 1; operandA = 32'b11010101010101010101011010101010; operandB = 32'b11111110000000000000000010010101; #5810
checkTestCase(32'b11010111010101010101011000010101, 0, 0, 0);

//XOR
command = 2; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; #80
checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0);
command = 2; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; #80
checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1);
command = 2; operandA = 32'b00101010101010101010111010111101; operandB = 32'b00001010101010110101010010110101; #80
checkTestCase(32'b00100000000000011111101000001000, 0, 0, 0);

//SLT
command = 3; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; #5850
checkTestCase(32'b11111111111111111111111111111111, 0, 0, 1);
command = 3; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; #5850
checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1);
command = 3; operandA = 32'b00000000000000000000000000000000; operandB = 32'b11111111111111111111111111111111; #5850
checkTestCase(32'b00000000000000000000000000000000, 0, 0, 0);

//AND
command = 4; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; #40
checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1);
command = 4; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; #40
checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0);
command = 4; operandA = 32'b00000000000000111111111111111111; operandB = 32'b01000100000101011101110111011011; #40
checkTestCase(32'b00000000000000011101110111011011, 0, 0, 0);

//NAND
command = 5; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; #50
checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0);
command = 5; operandA = 32'b11111111111111111111111111111111; operandB = 32'b11111111111111111111111111111111; #50
checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1);
command = 5; operandA = 32'b00000000000000111111111111111111; operandB = 32'b01000100000101011101110111011011; #50
checkTestCase(32'b11111111111111100010001000100100, 0, 0, 0);

//NOR
command = 6; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; #50
checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1);
command = 6; operandA = 32'b00000000000000000000000000000000; operandB = 32'b00000000000000000000000000000000; #50
checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0);
command = 6; operandA = 32'b00000000000000111111111111111111; operandB = 32'b01000100000101011101110111011011; #50
checkTestCase(32'b10111011111010000000000000000000, 0, 0, 0);

//OR
command = 7; operandA = 32'b11111111111111111111111111111111; operandB = 32'b00000000000000000000000000000000; #40
checkTestCase(32'b11111111111111111111111111111111, 0, 0, 0);
command = 7; operandA = 32'b00000000000000000000000000000000; operandB = 32'b00000000000000000000000000000000; #40
checkTestCase(32'b00000000000000000000000000000000, 0, 0, 1);
command = 7; operandA = 32'b00000000000000111111111111111111; operandB = 32'b01000100000101011101110111011011; #40
checkTestCase(32'b01000100000101111111111111111111, 0, 0, 0);

$display("%d test cases failed", numBroken);

end
endmodule




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