Added work plan

3bitMux.t.v

@@ -0,0 +1,31 @@
+`define NANDgate nand #10
+`define ANDgate and #20
+`define NORgate nor #10
+`define ORgate  or  #20
+`define NOTgate not #10
+`define XORgate xor #30
+
+`timescale 1 ns / 1 ps
+`include "3bitMux.v"
+
+module test3BitMux ();
+    reg[2:0] addr;
+    reg[7:0] inputs;
+    wire out;
+
+    threeBitMux mux (out, addr, inputs);
+
+    initial begin
+    $display("addr inputs | Output");
+    addr=3'b000;inputs=8'b00010000; #1000
+    $display("%b    %b | %b", addr, inputs, out);
+    addr=3'b000;inputs=8'b10000001; #1000
+    $display("%b    %b | %b", addr, inputs, out);
+    addr=3'b000;inputs=8'b00000000; #1000
+    $display("%b    %b | %b", addr, inputs, out);
+    addr=3'b011;inputs=8'b01000001; #1000
+    $display("%b    %b | %b", addr, inputs, out);
+    addr=3'b010;inputs=8'b00001101; #1000
+    $display("%b    %b | %b", addr, inputs, out);
+    end
+endmodule

3bitMux.v

@@ -0,0 +1,23 @@
+`include "multiplexer.v"
+
+module threeBitMux
+(
+    output out,
+    input[2:0] addr,
+    input[7:0] inputs
+);
+
+    wire result1;
+    wire nS2;
+    wire result2;
+    wire andResult1;
+    wire andResult2;
+
+    structuralMultiplexer mux1(result1, addr[0], addr[1], inputs[0], inputs[1], inputs[2], inputs[3]);
+    structuralMultiplexer mux2(result2, addr[0], addr[1], inputs[4], inputs[5], inputs[6], inputs[7]); 
+
+    `NOTgate invS2(nS2, addr[2]);
+    `ANDgate and1(andResult1, result1, nS2);
+    `ANDgate and2(andResult2, result2, addr[2]);
+    `ORgate or1(out, andResult1, andResult2);
+endmodule

adder.v

@@ -0,0 +1,30 @@
+module fullAdder1bit
+(
+    output sum, 
+    output carryout,
+    input a, 
+    input b, 
+    input carryin
+);
+    wire axorb;
+    wire nCarryIn;
+    wire notaxorb;
+    wire sumWire0;
+    wire sumWire1;
+
+    `XORgate abxorgate(axorb, a, b);
+    `ANDgate andgate0(sumWire0, axorb, nCarryIn);
+    `NOTgate invCarryIn(nCarryIn, carryin);
+    `NOTgate invaxorb(notaxorb, axorb);
+    `ANDgate andgate1(sumWire1, carryin, notaxorb);
+    `ORgate orgate0(sum, sumWire0, sumWire1);
+
+    wire aandb;
+    wire aorb;
+    wire carryOutWire;
+
+    `ANDgate abandgate(aandb, a, b);
+    `ORgate orgate1(aorb, a, b);
+    `ANDgate andgate2(carryOutWire, carryin, aorb);
+    `ORgate orgate2(carryout, aandb, carryOutWire);
+endmodule

alu.t.v

@@ -0,0 +1,107 @@
+`timescale 1 ns / 1 ps
+
+`include "alu.v"
+
+module testALU();
+    reg [31:0] a;
+    reg [31:0] b;
+    reg [2:0] c;
+    wire [31:0] result;
+    wire carryout;
+    wire zero;
+    wire overflow;
+
+    ALU alu (result, carryout, zero, overflow, a, b, c);
+
+    initial begin
+    $display("testing ADD");
+
+    $display("operandA operandB command |              result             carryout zero overflow| expected outputs");
+
+    a=32'h00000002;b=32'h00000001;c=``ADD; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 00000000000000000000000000000011  0  0  0", a, b, c, result, carryout, zero, overflow);
+
+    a=32'hFFFFFFFF;b=32'hFFFFFFFF;c=``ADD; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 11111111111111111111111111111110  1  0  0", a, b, c, result, carryout, zero, overflow);
+
+    a=32'h00000000;b=32'h00000000;c=`ADD; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 00000000000000000000000000000000  0  1  0", a, b, c, result, carryout, zero, overflow);
+
+    a=32'h7FFFFFFF;b=32'h00000001;c=`ADD; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 10000000000000000000000000000000  0  0  1", a, b, c, result, carryout, zero, overflow);
+
+    $display("testing SUB");
+
+    a=32'h00000003;b=32'h00000001;c=`SUB; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 00000000000000000000000000000010  1  0  0", a, b, c, result, carryout, zero, overflow);
+
+    a=32'h80000000;b=32'h00000001;c=`SUB; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 01111111111111111111111111111111  1  0  1", a, b, c, result, carryout, zero, overflow);
+
+    a=32'h00000000;b=32'h00000000;c=`SUB; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 00000000000000000000000000000000  1  1  0", a, b, c, result, carryout, zero, overflow);
+
+    a=32'hFFFFFFFF;b=32'hFFFFFFFF;c=`SUB; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 00000000000000000000000000000000  1  1  0", a, b, c, result, carryout, zero, overflow);
+
+    $display("testing XOR");
+
+    a=32'hAA550055;b=32'hAAFF55AA;c=`XOR; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 00000000101010100101010111111111  0  0  0", a, b, c, result, carryout, zero, overflow);
+
+    a=32'hFFFF0000;b=32'h00FF00FF;c=`XOR; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 11111111000000000000000011111111  0  0  0", a, b, c, result, carryout, zero, overflow);
+
+    $display("testing SLT");
+
+    a=32'h555555AA;b=32'h55AA55AA;c=`SLT; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 00000000000000000000000000000001  0  0  0", a, b, c, result, carryout, zero, overflow);
+
+    a=32'h555555AA;b=32'h555555AA;c=`SLT; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 00000000000000000000000000000000  0  0  0", a, b, c, result, carryout, zero, overflow);
+
+    a=32'h00FF00FF;b=32'hFF00FF00;c=`SLT; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 00000000000000000000000000000000  0  0  0", a, b, c, result, carryout, zero, overflow);
+
+    a=32'hFFFFFF00;b=32'h0000FFFF;c=`SLT; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 00000000000000000000000000000001  0  0  0", a, b, c, result, carryout, zero, overflow);
+
+    a=32'hAAAA55AA;b=32'hAA5555AA;c=`SLT; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 00000000000000000000000000000000  0  0  0", a, b, c, result, carryout, zero, overflow);
+
+    a=32'hFF55FF00;b=32'hFFFF5500;c=`SLT; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 00000000000000000000000000000001  0  0  0", a, b, c, result, carryout, zero, overflow);
+
+    $display("testing AND");
+
+    a=32'hFFFF0000;b=32'h00FF00FF;c=`AND; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 00000000111111110000000000000000  0  0  0", a, b, c, result, carryout, zero, overflow);
+
+    a=32'hFF00AA55;b=32'hAAAA55AA;c=`AND; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 10101010000000000000000000000000  0  0  0", a, b, c, result, carryout, zero, overflow);
+
+    $display("testing NAND");
+
+    a=32'hFFFF0000;b=32'h00FF00FF;c=`NAND; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 11111111000000001111111111111111  0  0  0", a, b, c, result, carryout, zero, overflow);
+
+    a=32'hFF00AA55;b=32'hAAAA55AA;c=`NAND; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 01010101111111111111111111111111  0  0  0", a, b, c, result, carryout, zero, overflow);
+
+    $display("testing NOR");
+
+    a=32'h55550055;b=32'hAAFF55AA;c=`NOR; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 00000000000000000101010100000000  0  0  0", a, b, c, result, carryout, zero, overflow);
+
+    a=32'hFFFF0000;b=32'h00FF00FF;c=`NOR; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 00000000000000001111111100000000  0  0  0", a, b, c, result, carryout, zero, overflow);
+
+    $display("testing OR");
+
+    a=32'h55FFAA00;b=32'hAAAA55AA;c=`OR; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 11111111111111111111111110101010  0  0  0", a, b, c, result, carryout, zero, overflow);
+
+    a=32'hFFFF0000;b=32'h00FF00FF;c=`OR; #2000
+    $display("%h %h %h       | %b    %b     %b   %b       | 11111111111111110000000011111111  0  0  0", a, b, c, result, carryout, zero, overflow);
+    end
+endmodule

alu.v

@@ -0,0 +1,163 @@
+`define NANDgate nand #10
+`define ANDgate and #20
+`define NORgate nor #10
+`define ORgate 	or  #20
+`define NOTgate not #10
+`define XORgate xor #30
+
+`define ADD  3'd0
+`define SUB  3'd1
+`define XOR  3'd2
+`define SLT  3'd3
+`define AND  3'd4
+`define NAND 3'd5
+`define NOR  3'd6
+`define OR   3'd7
+
+`include "adder.v"
+`include "3bitMux.v"
+
+
+module ALUcontrolLUT // control Lookup Table within ALU unit
+(
+	output reg[2:0] muxindex,
+	output reg		invertB, 
+
+	input[2:0]		ALUcommand
+);
+
+	always @(ALUcommand) begin
+	    case (ALUcommand)
+	    	`ADD:  begin muxindex = 0; invertB=0; end    
+	      	`SUB:  begin muxindex = 0; invertB=1; end
+	     	`XOR:  begin muxindex = 2; invertB=0; end    
+		    `SLT:  begin muxindex = 3; invertB=1; end
+		    `AND:  begin muxindex = 4; invertB=0; end    
+		    `NAND: begin muxindex = 5; invertB=0; end
+		    `NOR:  begin muxindex = 6; invertB=0; end    
+		    `OR:   begin muxindex = 7; invertB=0; end
+	    endcase
+	end
+endmodule
+
+module ALUunit // The bitslice ALU unit
+(
+	output bitR, // each bit of result
+	output carryout, // carryout flag for ADD, SUB, SLT
+
+	input bitA, 	// each bit of operandA
+	input bitB, 	// each bit of operandB
+	input carryin, 	// carryin input for ADD, SUB, SLT
+	input less, 	// a result bit in SLT command.
+	input[2:0] muxindex,
+	input invertBflag
+);
+
+	wire inputB;		// B input for adder
+	wire[7:0] muxinput;
+
+	`XORgate inputB_xorgate(inputB, bitB, invertBflag);
+
+	fullAdder1bit adder(muxinput[`ADD], carryout, bitA, inputB, carryin); // 1 bit adder for ADD, SUB, SLT
+
+	assign muxinput[`SLT] = less;
+	`XORgate nand_xor_gate(muxinput[`XOR], bitA, bitB);
+	`NOTgate not_and_gate(muxinput[`AND], muxinput[`NAND]);
+	`NANDgate nandgate(muxinput[`NAND], bitA, bitB);
+	`NORgate norgate(muxinput[`NOR], bitA, bitB);
+	`NOTgate not_or_gate(muxinput[`OR], muxinput[`NOR]);
+
+	threeBitMux mux(bitR, muxindex, muxinput);
+
+
+endmodule
+
+module lastALUunit // last ALU unit, which has an ALU unit with outputs of SLT value and overflow flag.
+(
+	output bitR,
+	output carryout,
+	output overflow,
+	output slt, // signal for less signal of the first ALU unit
+
+	input bitA,
+	input bitB,
+	input carryin,
+	input less,
+	input[2:0] muxindex,
+	input invertBflag
+);
+
+	ALUunit basic_unit(bitR, carryout, bitA, bitB, carryin, less, muxindex, invertBflag);
+	`XORgate overflowxorgate(overflow, carryin, carryout);
+
+	wire slt_result;  //sum of A, ~B and carryin, used when the command is SLT because bitR is always 0 for SLT.
+	wire slt_carryout;//not used variable
+	wire notB;//inverted B, used when the command is SLT 
+
+	`NOTgate invert_b_notgate(notB, bitB);
+	fullAdder1bit slt_adder(slt_result, add_carryout, bitA, notB, carryin);
+	`XORgate slt_xorgate(slt, slt_result, overflow);
+
+endmodule
+
+
+module ALU // total ALU which has 32 basic ALU units and control unit.
+(
+	output[31:0]  result,
+	output 	 	  carryout,
+	output        zero,
+	output        overflow,
+
+	input[31:0]   operandA,
+	input[31:0]   operandB,
+	input[2:0]    command
+);
+
+	wire[30:0]	internal_carryout; //carryout of each ALU unit except the last one
+	wire[2:0] 	muxindex;	//input address of MUX for every ALU unit
+	wire 		invertBflag;//invertB flag input for every ALU unit
+	wire 		set_SLT;	//less input for the first ALU unit
+
+	ALUcontrolLUT controlLUT(muxindex, invertBflag, command);
+
+	ALUunit firstunit(
+		result[0], internal_carryout[0], // output: result, carryout
+		operandA[0], operandB[0], invertBflag, set_SLT, muxindex, invertBflag
+	);
+
+	//// construct 32 ALU units
+	genvar i;
+	generate // 2nd to 31st adder instantiation 
+		for(i=1; i<31; i=i+1) begin: generate_alu_unit
+			ALUunit unit(
+				result[i],
+				internal_carryout[i],//carryout
+				operandA[i],
+				operandB[i],
+				internal_carryout[i-1],//carryin
+				0, 			//result for SLT command
+				muxindex,
+				invertBflag
+			);
+		end
+	endgenerate
+	lastALUunit lastunit(
+		result[31], carryout, overflow, set_SLT, // output: result, carryout, overflow, slt
+		operandA[31], operandB[31], internal_carryout[30], 0, muxindex, invertBflag
+	);
+
+	/// make logic for zero flag
+	wire[30:0] wire_for_zero;
+	wire[31:0] inverted_result;
+	`NORgate norgate0(wire_for_zero[0], result[0], result[1]);
+	generate
+		for(i=2; i<32; i=i+1) begin: generate_inverted_result
+			`NOTgate notgate(inverted_result[i], result[i]);
+		end
+		for(i=1; i<31; i=i+1) begin: generate_zero_flag
+			`ANDgate norgate(wire_for_zero[i], inverted_result[i+1], wire_for_zero[i-1]);
+		end
+	endgenerate
+	assign zero = wire_for_zero[30];
+
+endmodule