Submission

.gitignore

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+*~
+*.out
+*.vcd

ALUcontrolLUT.v

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+// `define ADD  3'd0
+// `define SUB  3'd1
+// `define XOR  3'd2
+// `define SLT  3'd3
+// `define AND  3'd4
+// `define NAND 3'd5
+// `define NOR  3'd6
+// `define OR   3'd7
+
+module ALUcontrolLUT
+(
+output reg ADD, SUB, XOR, SLT, AND, NAND, NOR, OR,
+input[2:0] ALUcommand
+);
+
+  always @(ALUcommand) begin
+    case (ALUcommand)
+      3'd0: begin {ADD, SUB, XOR, SLT, AND, NAND, NOR, OR} = 8'b10000000; end
+      3'd1: begin {ADD, SUB, XOR, SLT, AND, NAND, NOR, OR} = 8'b01000000; end
+      3'd2: begin {ADD, SUB, XOR, SLT, AND, NAND, NOR, OR} = 8'b00100000; end
+      3'd3: begin {ADD, SUB, XOR, SLT, AND, NAND, NOR, OR} = 8'b00010000; end
+      3'd4: begin {ADD, SUB, XOR, SLT, AND, NAND, NOR, OR} = 8'b00001000; end
+      3'd5: begin {ADD, SUB, XOR, SLT, AND, NAND, NOR, OR} = 8'b00000100; end
+      3'd6: begin {ADD, SUB, XOR, SLT, AND, NAND, NOR, OR} = 8'b00000010; end
+      3'd7: begin {ADD, SUB, XOR, SLT, AND, NAND, NOR, OR} = 8'b00000001; end
+    endcase
+  end
+endmodule

BitSlice.t.v

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+//Test harness for exhaustively testing individual bit_slice modules
+
+`include "BitSlice.v"
+
+module BitSliceTestHarness ();
+
+    // Declare registers for inputs
+    reg ADD, SUB, XOR, SLT, AND, NAND, NOR, OR, A, B, CIN;
+
+    // Declare output wires
+    wire cout, sum, res;
+
+    // Instantiate DUT
+    BitSlice bit_slice (cout, sum, res, ADD, SUB, XOR, SLT, AND, NAND, NOR, OR, A, B, CIN);
+
+    // Declare helper variable registers
+    reg[3:0] inputs;
+    reg testfailed;
+
+    initial begin
+    // Test bench code here.
+    $dumpfile("BitSlice.vcd");
+    $dumpvars(0,bit_slice);
+
+    // Initialize test failed to 0
+    testfailed = 0;
+
+    // Test simpler gates, OR, NOR, NAND, AND, XOR
+    // OR
+    {ADD, SUB, XOR, SLT, AND, NAND, NOR, OR} = 8'b00000001; // Set OR flag
+    for (inputs=4'b0; inputs<4'b1000; inputs=inputs+4'b1) begin
+        {CIN, A, B} = inputs; #1000 // Set inputs and wait
+        // $display( "%b %b %b", index, A, B); //
+        if (res != (A|B)) begin
+            testfailed = testfailed+1;
+            $display("Test Case OR Cin:%b A:%b B:%b Failed, Got %b Expected %b", CIN, A, B, res, (A|B));
+        end
+    end
+
+    // NOR
+    {ADD, SUB, XOR, SLT, AND, NAND, NOR, OR} = 8'b00000010; // Set NOR flag
+    for (inputs=4'b0; inputs<4'b1000; inputs=inputs+4'b1) begin
+        {CIN, A, B} = inputs; #1000 // Set inputs and wait
+        // $display( "%b %b %b", index, A, B); //
+        if (res != (A~|B)) begin
+            testfailed = testfailed+1;
+            $display("Test Case NOR Cin:%b A:%b B:%b Failed, Got %b Expected %b", CIN, A, B, res, (A~|B));
+        end
+    end
+
+    // NAND
+    {ADD, SUB, XOR, SLT, AND, NAND, NOR, OR} = 8'b00000100; // Set NAND flag
+    for (inputs=4'b0; inputs<4'b1000; inputs=inputs+4'b1) begin
+        {CIN, A, B} = inputs; #1000 // Set inputs and wait
+        // $display( "%b %b %b", index, A, B); //
+        if (res != (A~&B)) begin
+            testfailed = testfailed+1;
+            $display("Test Case NAND Cin:%b A:%b B:%b Failed, Got %b Expected %b", CIN, A, B, res, (A~&B));
+        end
+    end
+
+    // AND
+    {ADD, SUB, XOR, SLT, AND, NAND, NOR, OR} = 8'b00001000; // Set AND flag
+    for (inputs=4'b0; inputs<4'b1000; inputs=inputs+4'b1) begin
+        {CIN, A, B} = inputs; #1000 // Set inputs and wait
+        // $display( "%b %b %b", index, A, B); //
+        if (res != (A&B)) begin
+            testfailed = testfailed+1;
+            $display("Test Case AND Cin:%b A:%b B:%b Failed, Got %b Expected %b", CIN, A, B, res, (A&B));
+        end
+    end
+
+    // XOR
+    {ADD, SUB, XOR, SLT, AND, NAND, NOR, OR} = 8'b00100000; // Set XOR flag
+    for (inputs=4'b0; inputs<4'b1000; inputs=inputs+4'b1) begin
+        {CIN, A, B} = inputs; #1000 // Set inputs and wait
+        // $display( "%b %b %b", index, A, B); //
+        if (res != (A^B)) begin
+            testfailed = testfailed+1;
+            $display("Test Case XOR Cin:%b A:%b B:%b Failed, Got %b Expected %b", CIN, A, B, res, (A^B));
+        end
+    end
+
+    // Test more complicated gates: ADD and SUB
+    // ADD
+    {ADD, SUB, XOR, SLT, AND, NAND, NOR, OR} = 8'b10000000; // Set ADD flag
+    for (inputs=4'b0; inputs<4'b1000; inputs=inputs+4'b1) begin
+        {CIN, A, B} = inputs; #1000 // Set inputs and wait
+        // $display( "%b %b %b", index, A, B); //
+        if (sum != (A^B^CIN)) begin
+            testfailed = testfailed+1;
+            $display("Test Case ADD Cin:%b A:%b B:%b Failed, Got Sum:%b Expected Sum:%b", CIN, A, B, sum, A^B^CIN);
+        end
+        if (res != (A^B^CIN)) begin
+            testfailed = testfailed+1;
+            $display("Test Case ADD Cin:%b A:%b B:%b Failed, Got Res:%b Expected Res:%b", CIN, A, B, res, A^B^CIN);
+        end
+        if (cout != ((A&B)|((A^B)&CIN))) begin // (A&B)|((A^B)&CIN) is the correct carryout logic
+            testfailed = testfailed+1;
+            $display("Test Case ADD Cin:%b A:%b B:%b Failed, Got Cout:%b Expected Cout:%b", CIN, A, B, cout, (A&B)|((A^B)&CIN));
+        end
+    end
+
+    // SUB is identical to ADD but all of the B inputs to the test cases are inverted.
+    {ADD, SUB, XOR, SLT, AND, NAND, NOR, OR} = 8'b01000000; // Set SUB flag
+    for (inputs=4'b0; inputs<4'b1000; inputs=inputs+4'b1) begin
+        {CIN, A, B} = inputs; #1000 // Set inputs and wait
+        // $display( "%b %b %b", index, A, B); //
+        if (sum != (A^(!B)^CIN)) begin
+            testfailed = testfailed+1;
+            $display("Test Case SUB Cin:%b A:%b B:%b Failed, Got Sum:%b Expected Sum:%b", CIN, A, B, sum, A^(!B)^CIN);
+        end
+        if (res != (A^(!B)^CIN)) begin
+            testfailed = testfailed+1;
+            $display("Test Case SUB Cin:%b A:%b B:%b Failed, Got Res:%b Expected Res:%b", CIN, A, B, res, A^(!B)^CIN);
+        end
+        if (cout != ((A&(!B))|((A^(!B))&CIN))) begin // (A&(!B))|((A^(!B))&CIN) is the correct carryout logic
+            testfailed = testfailed+1;
+            $display("Test Case SUB Cin:%b A:%b B:%b Failed, Got Cout:%b Expected Cout:%b", CIN, A, B, cout, (A&(!B))|((A^(!B))&CIN));
+        end
+    end
+
+    // SLT is identical to SUB but all of the res outputs should be 0
+    {ADD, SUB, XOR, SLT, AND, NAND, NOR, OR} = 8'b00010000; // Set SLT flag
+    for (inputs=4'b0; inputs<4'b1000; inputs=inputs+4'b1) begin
+        {CIN, A, B} = inputs; #1000 // Set inputs and wait
+        // $display( "%b %b %b", index, A, B); //
+        if (sum != (A^(!B)^CIN)) begin
+            testfailed = testfailed+1;
+            $display("Test Case SLT Cin:%b A:%b B:%b Failed, Got Sum:%b Expected Sum:%b", CIN, A, B, sum, A^(!B)^CIN);
+        end
+        if (res != 0) begin
+            testfailed = testfailed+1;
+            $display("Test Case SLT Cin:%b A:%b B:%b Failed, Got Res:%b Expected Res:%b", CIN, A, B, res, 0);
+        end
+        if (cout != ((A&(!B))|((A^(!B))&CIN))) begin // (A&(!B))|((A^(!B))&CIN) is the correct carryout logic
+            testfailed = testfailed+1;
+            $display("Test Case SLT Cin:%b A:%b B:%b Failed, Got Cout:%b Expected Cout:%b", CIN, A, B, cout, (A&(!B))|((A^(!B))&CIN));
+        end
+    end
+
+    if(testfailed == 0) begin
+        $display("Tests Passed");
+    end
+    else begin
+        $display("%d Test Failures", testfailed);
+    end
+
+    end
+
+endmodule

BitSlice.v

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+//Single bit slice module for ALU
+`define NAND nand #20
+`define NOR nor #20
+`define NOT not #10
+`define XOR xor #30
+`define OR or #30
+`define NAND7 nand #70
+
+`include "adder.v"
+
+module BitSlice
+(
+    output cout, sum, res,
+    input ADD, SUB, XOR, SLT, AND, NAND, NOR, OR, A, B, CIN
+);
+    // internal wires
+    wire sum, sub_slt, b_inv, xor_ab, and_ab, nand_ab, nor_ab, or_ab;
+    // individual outputs into nand collector
+    wire add_out, sub_out, xor_out, and_out, nand_out, nor_out, or_out;
+
+    // individual operator blocks
+    `OR or_sub_slt (sub_slt, SUB, SLT);
+    `XOR inv_input (b_inv, B, sub_slt);
+    fullAdder adder (sum, cout, A, b_inv, CIN);
+    `XOR xor_operator (xor_ab, A, B);
+    `NAND nand_operator (nand_ab, A, B);
+    `NOR nor_operator (nor_ab, A, B);
+    `NOT not_nand (and_ab, nand_ab);
+    `NOT not_nor (or_ab, nor_ab);
+
+    // nand control line selectors
+    `NAND add_switch (add_out, sum, ADD);
+    `NAND sub_switch (sub_out, sum, SUB);
+    `NAND xor_switch (xor_out, xor_ab, XOR);
+    `NAND and_switch (and_out, and_ab, AND);
+    `NAND nand_switch (nand_out, nand_ab, NAND);
+    `NAND nor_switch (nor_out, nor_ab, NOR);
+    `NAND or_switch (or_out, or_ab, OR);
+
+    // collector for all individual outputs
+    `NAND7 collector (res, add_out, sub_out, xor_out, and_out, nand_out, nor_out, or_out);
+
+endmodule