Finished the Work Plan

Test_Sequence.txt

@@ -0,0 +1,27 @@
+Test Sequence
+
+Controls:
+
+Button0: Parallel Data In  
+Button1: Show Last 4 Bits
+Button2: Show First 4 Bits
+
+Switch0: Serial Data In
+Switch1: Serial Data In CLk Edge
+
+To begin testing first press Button0, then Button1. 
+You should see the following sequence in the 4 LEDS: 0011
+Press Button2 to see the first 4 bits which should be: 1100
+
+Now to test the serial data in functionality set switch0 to HIGH and toggle Switch1 to high
+This should write a 1 bit to the back of the shift register and you should see the following:
+Press Button1: 0111
+Press Button2: 1000
+
+Now set switch0 to low and toggle switch1 to high
+This should write a 0 bit to the back of the shift register and you should see the following:
+Press Button1: 1110
+Press Button2: 0000
+
+
+Now press Button0 again and the output should be 11000011 again.

datamemory.v

@@ -17,7 +17,7 @@ module datamemory
     input [addresswidth-1:0]    address,
     input                       writeEnable,
     input [width-1:0]           dataIn
-)
+);
 
 
     reg [width-1:0] memory [depth-1:0];

fsm.v

@@ -0,0 +1,156 @@
+//                MISO_BUFF            DM_WE            ADDR_WE          SR_WE
+//CS              0                    0                0                0
+//~CS             0                    0                1                1
+//shiftRegOutP[0] 1                    0                0                1
+//~shiftRegOutP[0]0                    1                0                0
+module fsm(MISO_BUFF,DM_WE,ADDR_WE,SR_WE,POS_EDGE,CS,shiftRegOutP0,clk,state,counter,relevant_shiftRegOutP0,clk_counter);
+   input POS_EDGE;
+   input CS;
+   input shiftRegOutP0;
+   input clk;
+   output MISO_BUFF;
+   output DM_WE;
+   output ADDR_WE;
+   output SR_WE;
+   output [1:0] state;
+   output [5:0] counter;
+   output [1:0] relevant_shiftRegOutP0;
+   output [5:0] clk_counter;
+
+   wire [1:0] state;
+   reg MISO_BUFF,DM_WE,ADDR_WE,SR_WE;
+   reg [1:0] next_state;
+   parameter counter_num_bits = 5;
+   reg[counter_num_bits-1:0] counter = 0;
+   reg start_counter;
+   wire [1:0] previous_state;
+   reg [1:0] counter_type;
+   reg [1:0] relevant_shiftRegOutP0;
+   reg already_counted;
+   reg [5:0] clk_counter;
+   reg [1:0] counter_flag;
+
+   assign state = next_state;
+
+   function [1:0] fsm_function;
+      input [1:0] state;
+      input CS;
+      input relevant_shiftRegOutP0;
+      case(state)
+        2'b00:if(!CS) begin
+                 fsm_function = 2'b01;
+              end
+        2'b01:if(relevant_shiftRegOutP0 == 2'b10) begin
+                 fsm_function = 2'b10;
+              end else if (relevant_shiftRegOutP0 == 2'b01) begin
+                 fsm_function = 2'b11;
+			  end else if (already_counted && counter == 0 && CS) begin
+			     fsm_function = 2'b00;
+              end
+        2'b10:if(CS) begin
+                 fsm_function = 2'b00;
+              end
+        2'b11:if(CS) begin
+                 fsm_function = 2'b00;
+              end
+        default:fsm_function = 2'b00;
+      endcase
+   endfunction
+
+   always @ (posedge clk) begin
+	if(counter == 7) begin
+		clk_counter <= 1;
+		counter_flag <= 2'b01;
+	end else if (counter == 10 && relevant_shiftRegOutP0 == 2'b10) begin
+		clk_counter <= 1;
+		counter_flag <= 2'b10;
+	end else if (counter == 18 && relevant_shiftRegOutP0 == 2'b10) begin
+		clk_counter <= 1;
+		counter_flag <= 2'b11;
+	end else if (clk_counter == 3 && counter_flag == 2'b01) begin
+		relevant_shiftRegOutP0 <= shiftRegOutP0 ? 2'b10 : 2'b01;
+		clk_counter <= 0;
+	end else if (clk_counter == 6 && counter_flag == 2'b10) begin
+		MISO_BUFF <= 1;
+		clk_counter <= 0;
+	end else if (clk_counter == 6 && counter_flag == 2'b11) begin
+		MISO_BUFF <= 0;
+		clk_counter <= 0;
+		counter <= 0;
+		relevant_shiftRegOutP0 <= 2'b00;
+	end else if (clk_counter  > 0) begin
+		clk_counter <= clk_counter + 1;
+	end
+   end
+
+   always @ (posedge POS_EDGE) begin
+	  next_state <= fsm_function(state,CS,relevant_shiftRegOutP0); 
+      if (next_state == 2'b00) begin
+         MISO_BUFF <= 0;
+         DM_WE <= 0;
+         SR_WE <= 0;
+		 ADDR_WE <= 0;
+		 already_counted <= 0;
+      end else if (next_state == 2'b01) begin
+         if(counter == 0 && !already_counted) begin
+           counter <= 1;
+		   counter_type <= 2'b01;
+		   already_counted <= 1;
+         end
+      end else if (next_state == 2'b10) begin
+         ADDR_WE <= 0;
+		 DM_WE <= 0;
+		 if(counter > 0) begin
+			SR_WE <= 1;
+			MISO_BUFF <= 1;
+		 end
+      end else if (next_state == 2'b11) begin
+         DM_WE <= 0;
+         ADDR_WE <= 0;
+         SR_WE <= 0;
+      end
+      if (counter == 7) begin
+		ADDR_WE <= 1;
+		//relevant_shiftRegOutP0 <= shiftRegOutP0 ? 2'b10 : 2'b01;
+		counter <= counter + 1;
+	  end else if (counter == 8) begin
+		ADDR_WE <= 0;
+		counter <= counter + 1;
+	  end else if (counter == 9) begin
+		if (relevant_shiftRegOutP0 == 2'b10) begin
+			SR_WE <= 1;
+		end
+		counter <= counter + 1;
+	  end else if (counter == 10) begin
+	    SR_WE <= 0;
+		counter <= counter + 1;
+	  //end else if (counter == ) begin
+		//if (next_state == 2'b10) begin
+			//MISO_BUFF <= 1;
+		//end
+		//counter <= counter + 1;
+	  //end else if (counter == 10) begin
+		//if (relevant_shiftRegOutP0 == 2'b10) begin
+		//	MISO_BUFF <= 1;
+		//end
+	  end else if (counter == 15) begin
+		if (relevant_shiftRegOutP0 == 2'b01) begin
+			DM_WE <= 1;
+		end 
+		counter <= counter + 1;
+	  end else if (counter == 16) begin
+		DM_WE <= 0;
+		SR_WE <= 0;
+		//counter <= 0;
+		if (relevant_shiftRegOutP0 == 2'b01) begin
+			MISO_BUFF <= 0;
+			counter <= 0;
+			relevant_shiftRegOutP0 <= 2'b00;
+		end else if (relevant_shiftRegOutP0 == 2'b10) begin
+			counter <= counter + 1;
+		end
+	  end else if (counter > 0) begin
+		counter <= counter + 1;
+	  end
+   end
+endmodule

inputconditioner.t.v

@@ -1,10 +1,11 @@
 //------------------------------------------------------------------------
 // Input Conditioner test bench
 //------------------------------------------------------------------------
+`include "inputconditioner.v"
 
 module testConditioner();
 
-    reg clk;
+    reg clk = 0;
     reg pin;
     wire conditioned;
     wire rising;
@@ -14,16 +15,23 @@ module testConditioner();
     			 .noisysignal(pin),
 			 .conditioned(conditioned),
 			 .positiveedge(rising),
-			 .negativeedge(falling))
-
+			 .negativeedge(falling));
 
     // Generate clock (50MHz)
-    initial clk=0;
-    always #10 clk=!clk;    // 50MHz Clock
+    initial begin
+       forever begin
+          clk = !clk; #10;
+       end
+    end
 
     initial begin
-    // Your Test Code
-    // Be sure to test each of the three conditioner functions:
-    // Synchronization, Debouncing, Edge Detection
+       pin = 0; #50;
+       pin = 1; #100;
+       pin = 0; #100;
+       pin = 1; #150;
+       pin = 0; #30;
+       pin = 1; #60;
+       pin = 0; #30;
+    end
 
 endmodule

inputconditioner.v

@@ -6,33 +6,46 @@
 //------------------------------------------------------------------------
 
 module inputconditioner
-(
-input 	    clk,            // Clock domain to synchronize input to
-input	    noisysignal,    // (Potentially) noisy input signal
-output reg  conditioned,    // Conditioned output signal
-output reg  positiveedge,   // 1 clk pulse at rising edge of conditioned
-output reg  negativeedge    // 1 clk pulse at falling edge of conditioned
-);
+(clk,noisysignal,conditioned,positiveedge,negativeedge);
 
     parameter counterwidth = 3; // Counter size, in bits, >= log2(waittime)
     parameter waittime = 3;     // Debounce delay, in clock cycles
+
+    input clk;
+    input noisysignal;
+    output reg conditioned;
+    output reg positiveedge;
+    output reg negativeedge;
 
     reg[counterwidth-1:0] counter = 0;
     reg synchronizer0 = 0;
     reg synchronizer1 = 0;
+    reg conditioned1 = 0;
 
     always @(posedge clk ) begin
-        if(conditioned == synchronizer1)
+		if(conditioned1 == 0 && conditioned == 1) begin
+			negativeedge = 1;
+		end else if (conditioned1 == 1 && conditioned == 0) begin
+			positiveedge = 1;
+        end else if (positiveedge == 1 || negativeedge == 1) begin
+            positiveedge = 0;
+            negativeedge = 0;
+        end
+        if(conditioned1 == synchronizer1)
             counter <= 0;
         else begin
             if( counter == waittime) begin
                 counter <= 0;
-                conditioned <= synchronizer1;
+                conditioned1 <= synchronizer1;
             end
             else 
                 counter <= counter+1;
         end
         synchronizer0 <= noisysignal;
         synchronizer1 <= synchronizer0;
+		conditioned <= conditioned1;
     end
 endmodule
+
+
+