Lab 2 submission

finiteStateMachine.v

@@ -0,0 +1,117 @@
+`define WAIT 3'd0
+`define READADDRESS 3'd1
+`define WRITE 3'd3
+`define READ 3'd4
+`define READORWRITE 3'd2
+
+
+module fsm 
+(
+    output reg MISObuff,
+    output reg memWE,
+    output reg addrWE,
+    output reg srWE,
+
+    //input posclkedge,
+    input spi_clk,
+    input spi_falling,
+    input cs_falling,
+    input rw_select
+);
+    reg [3:0] count;
+    reg [2:0] state;
+
+    initial count = 4'd0;
+    initial state = `WAIT;
+    initial MISObuff = 0;
+    initial memWE = 0;
+    initial addrWE = 0;
+    initial srWE = 0;
+
+    always @(posedge cs_falling) begin
+	state <= `READADDRESS;
+    end
+    //always @(posedge cs) begin
+//	state <= `WAIT;
+  //  end
+
+    always @(posedge spi_clk) begin
+        case (state)
+            `WAIT: begin
+                MISObuff <= 0;
+		memWE <= 0;
+		addrWE <= 0;
+		srWE <= 0;
+            end
+
+            `READADDRESS: begin
+                if (count == 4'd6) begin
+                    state <= `READORWRITE;
+                    addrWE <= 1;
+                    count <= 0;
+		    @(posedge spi_falling) begin
+			addrWE <= 0;
+		    end
+                end
+                else
+                    count = count + 1;
+
+            end
+
+            `READORWRITE: begin
+                if (rw_select == 0) begin
+                    state <= `WRITE;
+                end
+		else begin
+		    srWE <= 1;
+		    MISObuff <= 1;
+		    state <= `READ;
+		    @(posedge spi_falling) begin
+			srWE <= 0;
+		    end
+		end
+            end
+
+            `WRITE: begin
+                if (count == 4'd7) begin
+                    count <= 0;
+                    memWE <= 1;
+                    state <= `WAIT;
+		    @(posedge spi_falling) begin
+			memWE <= 0;
+		    end
+                end
+                else
+                    count <= count + 1;
+
+            end
+
+            `READ: begin
+		srWE <= 0;
+                if (count == 4'd7) begin
+                    count <= 0;
+                    state <= `WAIT;
+                end
+                else
+                    count <= count + 1;
+            end
+
+            default:  begin end
+        endcase
+    end
+/*
+    always @(posedge negclkedge) begin
+        case (state)
+            `READORWRITE: begin
+                if (wr_enable == 1) begin
+                    state <= `READ;
+                    q3 <= 1;
+                    buffer <=1;
+                end
+            end
+            default: begin end
+        endcase
+    end
+*/
+
+endmodule

fsmTest.t.v

@@ -0,0 +1,78 @@
+// 32-bit alu testbench
+
+//`timescale 1 ns / 1 ps
+`include "finiteStateMachine.v"
+
+module testFSM();
+
+    reg clk, clk_fall;
+    reg chipSelect;
+    reg rw_select;
+
+    wire MISObuff, memWE, addrWE, srWE;
+
+    wire csFalling;
+    not(csFalling, chipSelect);
+    initial chipSelect = 1;
+    fsm test(MISObuff, memWE, addrWE, srWE, clk, clk_fall, csFalling, rw_select);
+
+    // generate clock
+    initial clk = 0;
+    always begin
+	#10;
+	clk = !clk; //50 MHz clock
+	clk_fall = !clk;
+    end
+
+    initial
+	#10000 $finish;
+
+    initial begin
+	$dumpfile("fsm.vcd");
+	$dumpvars();
+
+        $display(" chip select | read/write | MISObuff | memWE | addrWE | srWE | state");
+	$display();
+	$display("Chip Not Selected -------------------------------------------------------------------------------------");
+	chipSelect=1; rw_select=0;
+        #30;
+        $display("|     %b      |     %b      |     %b    |   %b   |    %b   |  %b   |   %b", chipSelect, rw_select, MISObuff, memWE, addrWE, srWE, test.state);
+	$display("Chip Not Selected -------------------------------------------------------------------------------------");
+	chipSelect=1; rw_select=1;
+        #20;
+        $display("|     %b      |     %b      |     %b    |   %b   |    %b   |  %b   |   %b", chipSelect, rw_select, MISObuff, memWE, addrWE, srWE, test.state);
+	$display("Chip Selected: 1 clk cycle read -------------------------------------------------------------------------------------");
+	chipSelect=0; rw_select=1;
+        #30;
+        $display("|     %b      |     %b      |     %b    |   %b   |    %b   |  %b   |   %b", chipSelect, rw_select, MISObuff, memWE, addrWE, srWE, test.state);
+	$display("Chip Selected: 7 clk cycles read -------------------------------------------------------------------------------------");
+        #120;
+        $display("|     %b      |     %b      |     %b    |   %b   |    %b   |  %b   |   %b", chipSelect, rw_select, MISObuff, memWE, addrWE, srWE, test.state);
+	$display("Chip Selected: 9 clk cycles read -------------------------------------------------------------------------------------");
+        #40;
+        $display("|     %b      |     %b      |     %b    |   %b   |    %b   |  %b   |   %b", chipSelect, rw_select, MISObuff, memWE, addrWE, srWE, test.state);
+	$display("Chip Not Selected -------------------------------------------------------------------------------------");
+	#130;
+	chipSelect=1; rw_select=0;
+        #20;
+        $display("|     %b      |     %b      |     %b    |   %b   |    %b   |  %b   |   %b", chipSelect, rw_select, MISObuff, memWE, addrWE, srWE, test.state);
+	$display("Chip Selected: 1 clk cycle write -------------------------------------------------------------------------------------");
+	chipSelect=0; rw_select=0;
+        #30;
+        $display("|     %b      |     %b      |     %b    |   %b   |    %b   |  %b   |   %b", chipSelect, rw_select, MISObuff, memWE, addrWE, srWE, test.state);
+	$display("Chip Selected: 7 clk cycles write -------------------------------------------------------------------------------------");
+        #120;
+        $display("|     %b      |     %b      |     %b    |   %b   |    %b   |  %b   |   %b", chipSelect, rw_select, MISObuff, memWE, addrWE, srWE, test.state);
+	$display("Chip Selected: 9 clk cycles write -------------------------------------------------------------------------------------");
+        #40;
+        $display("|     %b      |     %b      |     %b    |   %b   |    %b   |  %b   |   %b", chipSelect, rw_select, MISObuff, memWE, addrWE, srWE, test.state);
+	$display("Chip Selected: 16 clk cycles write -------------------------------------------------------------------------------------");
+        #140;
+        $display("|     %b      |     %b      |     %b    |   %b   |    %b   |  %b   |   %b", chipSelect, rw_select, MISObuff, memWE, addrWE, srWE, test.state);
+	$display("Chip Selected: 20 clk cycles write -------------------------------------------------------------------------------------");
+        #220;
+        $display("|     %b      |     %b      |     %b    |   %b   |    %b   |  %b   |   %b", chipSelect, rw_select, MISObuff, memWE, addrWE, srWE, test.state);
+    end
+
+endmodule
+

inputconditioner.v

@@ -1,9 +1,11 @@
+// TAKEN FROM LISA'S 2016 REPOSITORY
 //------------------------------------------------------------------------
 // Input Conditioner
 //    1) Synchronizes input to clock domain
 //    2) Debounces input
 //    3) Creates pulses at edge transitions
 //------------------------------------------------------------------------
+`timescale 1 ns / 1 ps
 
 module inputconditioner
 (
@@ -14,25 +16,41 @@ output reg  positiveedge,   // 1 clk pulse at rising edge of conditioned
 output reg  negativeedge    // 1 clk pulse at falling edge of conditioned
 );
 
+    initial positiveedge = 0;
+    initial negativeedge = 0;
+    initial conditioned = 0;
+
     parameter counterwidth = 3; // Counter size, in bits, >= log2(waittime)
     parameter waittime = 3;     // Debounce delay, in clock cycles
-    
-    reg[counterwidth-1:0] counter = 0;
+
+    reg[counterwidth-1:0] counter = 0; //not sure what this syntax is
     reg synchronizer0 = 0;
     reg synchronizer1 = 0;
-    
+
     always @(posedge clk ) begin
-        if(conditioned == synchronizer1)
+        if(conditioned == synchronizer1) begin //if conditioned is same as we thought
             counter <= 0;
-        else begin
-            if( counter == waittime) begin
-                counter <= 0;
-                conditioned <= synchronizer1;
+            positiveedge <= 0; //not sure if this should be nonblockingit
+            negativeedge <= 0;
+	end
+        else begin //if conditioned has changed
+            if( counter == waittime) begin //when debouncing is done
+                counter <= 0; //reset counter
+                conditioned <= synchronizer1; //save conditioned in synchronizer1
+                positiveedge <= synchronizer1; //set negativeedge opposite
+                negativeedge <= !synchronizer1; //set positiveedge opposite
             end
-            else 
-                counter <= counter+1;
+            else begin
+                counter <= counter+1; //wait for debouncing
+	    end
+        end
+        if (counter == 0) begin
+            synchronizer0 <= noisysignal;
+            synchronizer1 <= synchronizer0;
         end
-        synchronizer0 <= noisysignal;
-        synchronizer1 <= synchronizer0;
     end
+
+    //max glitch is 6 clock cycles
+
+
 endmodule

shiftregister.v

@@ -1,10 +1,13 @@
+// USING SHIFT REGISTER FROM LISA'S 2016 REPOSITORY
 //------------------------------------------------------------------------
 // Shift Register
 //   Parameterized width (in bits)
 //   Shift register can operate in two modes:
 //      - serial in, parallel out
 //      - parallel in, serial out
 //------------------------------------------------------------------------
+`timescale 1 ns / 1 ps
+//`include "inputconditioner.v"
 
 module shiftregister
 #(parameter width = 8)
@@ -14,12 +17,35 @@ input               peripheralClkEdge,  // Edge indicator
 input               parallelLoad,       // 1 = Load shift reg with parallelDataIn
 input  [width-1:0]  parallelDataIn,     // Load shift reg in parallel
 input               serialDataIn,       // Load shift reg serially
-output [width-1:0]  parallelDataOut,    // Shift reg data contents
-output              serialDataOut       // Positive edge synchronized
+output reg [width-1:0]  parallelDataOut,    // Shift reg data contents
+output reg             serialDataOut       // Positive edge synchronized
 );
 
-    reg [width-1:0]      shiftregistermem;
+    reg [width-1:0] shiftregistermem;
+    //wire conditioned;
+    //wire positiveedge;
+    //wire negativeedge;
+    //inputconditioner inputc(clk, peripheralClkEdge, conditioned, positiveedge, negativeedge);
+
+
     always @(posedge clk) begin
-        // Your Code Here
+        // Parallel load will happen if parallel load is high.
+        // this takes priority over the serial shift
+        if (parallelLoad) begin // Parallel
+            shiftregistermem <= parallelDataIn;
+        end
+        //the shift register advances one position: serialDataIn is loaded into the LSB (Least Significant Bit), and the rest of the bits shift up by one
+        else begin
+            if (peripheralClkEdge) begin
+        	shiftregistermem <= {{shiftregistermem[width-2:0]}, {serialDataIn}};
+            end
+        end
+
+
+        //serialDataOut always presents the Most Significant Bit of the shift register.
+        serialDataOut <= shiftregistermem[width-1];
+        //parallelDataOut always presents the entirety of the contents of the shift register.
+        parallelDataOut <= shiftregistermem;
+
     end
 endmodule