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Submitting workplan.txt#2

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xiaozhengxu wants to merge 5 commits intoCompArchFA17:masterfrom

judycomparch:master

Commits on Oct 23, 2017

Create workplan.txt
xiaozhengxu
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Commits on Oct 25, 2017

inputconditioner logic seems to work, but the test bench is not complete and doesn't stop by itself.
Xiaozheng Xu
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Stopped infinite clock with finish. Test bench is almost complete. Can test more debouncing
Xiaozheng Xu
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Adding seemingly working shift register and midpoint

Xiaozheng Xu
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Xiaozheng Xu
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Commits on Oct 26, 2017

working midpoint on FPGA, modified input conditioner

Xiaozheng Xu
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Xiaozheng Xu
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