Skip to content
This repository was archived by the owner on Aug 21, 2023. It is now read-only.

Logan & Maggie Final Submission #4

Open
mjakus wants to merge 42 commits into
base: master
Choose a base branch
from
Open

Logan & Maggie Final Submission #4

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
42 commits
Select commit Hold shift + click to select a range
010aed9
create workplan
LoganSweet Oct 20, 2017
b2bdf82
inputconditioner done maybe
LoganSweet Oct 20, 2017
3a596b4
inputconditioner
LoganSweet Oct 22, 2017
06ed41e
falling and rising edge done
LoganSweet Oct 22, 2017
88bd116
shift register comments and structure added
LoganSweet Oct 23, 2017
9e0498a
checking GTKwave and relized conditioned signal is broken
LoganSweet Oct 23, 2017
e615071
Never fear, GTKWave is fine
mjakus Oct 24, 2017
cde4edc
git debacle part 3
LoganSweet Oct 24, 2017
70552fe
debacle again
LoganSweet Oct 24, 2017
527ff5b
Delete inputconditioner.t.v
LoganSweet Oct 24, 2017
d180dcb
Delete inputconditioner.v
LoganSweet Oct 24, 2017
6702a9d
Delete inputconditioner.vcd
LoganSweet Oct 24, 2017
ef065f8
Delete shiftregister.t.v
LoganSweet Oct 24, 2017
33aa4cb
Delete shiftregister.v
LoganSweet Oct 24, 2017
abc52fd
debacle attempt
LoganSweet Oct 24, 2017
5759222
no idea
LoganSweet Oct 24, 2017
a6f6d64
wow Maggie and I really need to learn to git
LoganSweet Oct 24, 2017
9c03c63
cleaned up inputconditioned code for readbility
LoganSweet Oct 24, 2017
c66f060
minior formatting
LoganSweet Oct 24, 2017
051f031
messed with shift register, still confused
LoganSweet Oct 24, 2017
9e47438
comments added for thoughts
LoganSweet Oct 24, 2017
5997218
Shift register works, adding midpoint.v
mjakus Oct 24, 2017
ebc3ebb
merging
mjakus Oct 24, 2017
b82cead
Editing tests and GTKWave
mjakus Oct 25, 2017
21a8d83
Added wrapper, maybe working
mjakus Oct 26, 2017
6010eff
some of this is meaningless but the rest is the midpoint being done
mjakus Oct 26, 2017
60d6b88
Added writeup for midpoint
mjakus Oct 26, 2017
84fb010
finite state machine framework added
LoganSweet Oct 29, 2017
e62f6bf
file cleanup
LoganSweet Oct 29, 2017
151e7c3
Worked on FSM, don't want to lose everything if my computer randomly …
mjakus Oct 30, 2017
636d577
adding FSM test bench, still missing thing to reset chip select to 1 …
mjakus Oct 30, 2017
3479bff
Working on spimemory
mjakus Oct 31, 2017
fdd0ed6
Working on SPI
mjakus Oct 31, 2017
c36f834
added counters to spi memory
mjakus Oct 31, 2017
4a2515c
yolo
mjakus Oct 31, 2017
ea57fe1
everything is dumb
mjakus Oct 31, 2017
85d4efb
fixing problems with spi
mjakus Oct 31, 2017
5b07c6f
SPI module in progress
LoganSweet Oct 31, 2017
c756bbf
this will have to be fine
LoganSweet Oct 31, 2017
cea153d
In case this explodes
mjakus Oct 31, 2017
36fd72e
Done!
mjakus Oct 31, 2017
43d5d93
Adding the writeup
mjakus Nov 1, 2017
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
281 changes: 281 additions & 0 deletions -Wall
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,281 @@
#! /usr/bin/vvp
:ivl_version "0.9.7 " "(v0_9_7)";
:vpi_time_precision + 0;
:vpi_module "system";
:vpi_module "v2005_math";
:vpi_module "va_math";
S_0xf3d8d0 .scope module, "FSM" "FSM" 2 8;
.timescale 0 0;
P_0xf16e58 .param/l "counterwidth" 2 23, +C4<0101>;
P_0xf16e80 .param/l "width" 2 22, +C4<01000>;
v0xf15020_0 .var "ADDR_WE", 0 0;
v0xf683a0_0 .net "ChipSelCond", 0 0, C4<z>; 0 drivers
v0xf68440_0 .var "DM_WE", 0 0;
v0xf684e0_0 .var "MISO_BUFE", 0 0;
v0xf68590_0 .net "SCLKEdge", 0 0, C4<z>; 0 drivers
v0xf68630_0 .var "SR_WE", 0 0;
v0xf68710_0 .var "WriteController", 0 0;
v0xf687b0_0 .net "clk", 0 0, C4<z>; 0 drivers
v0xf688a0_0 .var "counter", 4 0;
v0xf68940_0 .net "shiftRegOutPZero", 0 0, C4<z>; 0 drivers
E_0xf3db00 .event posedge, v0xf687b0_0;
S_0xf51110 .scope module, "inputconditioner" "inputconditioner" 3 9;
.timescale 0 0;
P_0xf51208 .param/l "counterwidth" 3 18, +C4<011>;
P_0xf51230 .param/l "waittime" 3 19, +C4<011>;
v0xf68a80_0 .net "clk", 0 0, C4<z>; 0 drivers
v0xf68b40_0 .var "conditioned", 0 0;
v0xf68be0_0 .var "counter", 2 0;
v0xf68c80_0 .var "negativeedge", 0 0;
v0xf68d30_0 .net "noisysignal", 0 0, C4<z>; 0 drivers
v0xf68dd0_0 .var "positiveedge", 0 0;
v0xf68e70_0 .var "synchronizer0", 0 0;
v0xf68f10_0 .var "synchronizer1", 0 0;
E_0xf68560 .event posedge, v0xf68a80_0;
S_0xf51260 .scope module, "shiftregister" "shiftregister" 4 9;
.timescale 0 0;
P_0xf4eb58 .param/l "width" 4 10, +C4<01000>;
L_0xf69570 .functor BUFZ 8, v0xf69480_0, C4<00000000>, C4<00000000>, C4<00000000>;
v0xf68ff0_0 .net "clk", 0 0, C4<z>; 0 drivers
v0xf690b0_0 .net "parallelDataIn", 7 0, C4<zzzzzzzz>; 0 drivers
v0xf69150_0 .net "parallelDataOut", 7 0, L_0xf69570; 1 drivers
v0xf691f0_0 .net "parallelLoad", 0 0, C4<z>; 0 drivers
v0xf692a0_0 .net "peripheralClkEdge", 0 0, C4<z>; 0 drivers
v0xf69340_0 .net "serialDataIn", 0 0, C4<z>; 0 drivers
v0xf693e0_0 .net "serialDataOut", 0 0, L_0xf69620; 1 drivers
v0xf69480_0 .var "shiftregistermem", 7 0;
E_0xf68d00 .event posedge, v0xf68ff0_0;
L_0xf69620 .part v0xf69480_0, 7, 1;
.scope S_0xf3d8d0;
T_0 ;
%set/v v0xf688a0_0, 0, 5;
%end;
.thread T_0;
.scope S_0xf3d8d0;
T_1 ;
%set/v v0xf68710_0, 0, 1;
%end;
.thread T_1;
.scope S_0xf3d8d0;
T_2 ;
%wait E_0xf3db00;
%load/v 8, v0xf68590_0, 1;
%mov 9, 0, 2;
%cmpi/u 8, 1, 3;
%jmp/0xz T_2.0, 4;
%load/v 8, v0xf683a0_0, 1;
%mov 9, 0, 1;
%cmpi/u 8, 0, 2;
%jmp/0xz T_2.2, 4;
%load/v 8, v0xf688a0_0, 5;
%mov 13, 0, 27;
%addi 8, 1, 32;
%ix/load 0, 5, 0;
%assign/v0 v0xf688a0_0, 0, 8;
%load/v 8, v0xf688a0_0, 5;
%mov 13, 0, 2;
%cmpi/u 8, 7, 7;
%jmp/0xz T_2.4, 4;
%ix/load 0, 1, 0;
%assign/v0 v0xf15020_0, 0, 1;
T_2.4 ;
%load/v 8, v0xf688a0_0, 5;
%mov 13, 0, 1;
%cmpi/u 8, 8, 6;
%jmp/0xz T_2.6, 4;
%ix/load 0, 1, 0;
%assign/v0 v0xf15020_0, 0, 0;
%load/v 8, v0xf68940_0, 1;
%mov 9, 0, 1;
%cmpi/u 8, 0, 2;
%jmp/0xz T_2.8, 4;
%ix/load 0, 1, 0;
%assign/v0 v0xf68710_0, 0, 1;
%jmp T_2.9;
T_2.8 ;
%load/v 8, v0xf68940_0, 1;
%mov 9, 0, 2;
%cmpi/u 8, 1, 3;
%jmp/0xz T_2.10, 4;
%ix/load 0, 1, 0;
%assign/v0 v0xf68630_0, 0, 1;
%ix/load 0, 1, 0;
%assign/v0 v0xf684e0_0, 0, 1;
T_2.10 ;
T_2.9 ;
%jmp T_2.7;
T_2.6 ;
%movi 8, 7, 7;
%load/v 15, v0xf688a0_0, 5;
%mov 20, 0, 2;
%cmp/u 8, 15, 7;
%jmp/0xz T_2.12, 5;
%ix/load 0, 1, 0;
%assign/v0 v0xf15020_0, 0, 0;
%jmp T_2.13;
T_2.12 ;
%load/v 8, v0xf688a0_0, 5;
%mov 13, 0, 1;
%cmpi/u 8, 15, 6;
%jmp/0xz T_2.14, 4;
%ix/load 0, 5, 0;
%assign/v0 v0xf688a0_0, 0, 0;
%load/v 8, v0xf68710_0, 1;
%mov 9, 0, 2;
%cmpi/u 8, 1, 3;
%jmp/0xz T_2.16, 4;
%ix/load 0, 1, 0;
%assign/v0 v0xf68440_0, 0, 1;
T_2.16 ;
T_2.14 ;
T_2.13 ;
T_2.7 ;
%jmp T_2.3;
T_2.2 ;
%load/v 8, v0xf683a0_0, 1;
%mov 9, 0, 2;
%cmpi/u 8, 1, 3;
%jmp/0xz T_2.18, 4;
%ix/load 0, 5, 0;
%assign/v0 v0xf688a0_0, 0, 0;
%ix/load 0, 1, 0;
%assign/v0 v0xf68440_0, 0, 0;
%ix/load 0, 1, 0;
%assign/v0 v0xf15020_0, 0, 0;
%ix/load 0, 1, 0;
%assign/v0 v0xf68630_0, 0, 0;
%ix/load 0, 1, 0;
%assign/v0 v0xf684e0_0, 0, 0;
T_2.18 ;
T_2.3 ;
T_2.0 ;
%jmp T_2;
.thread T_2;
.scope S_0xf51110;
T_3 ;
%set/v v0xf68be0_0, 0, 3;
%end;
.thread T_3;
.scope S_0xf51110;
T_4 ;
%set/v v0xf68e70_0, 0, 1;
%end;
.thread T_4;
.scope S_0xf51110;
T_5 ;
%set/v v0xf68f10_0, 0, 1;
%end;
.thread T_5;
.scope S_0xf51110;
T_6 ;
%wait E_0xf68560;
%load/v 8, v0xf68b40_0, 1;
%load/v 9, v0xf68f10_0, 1;
%cmp/u 8, 9, 1;
%jmp/0xz T_6.0, 4;
%ix/load 0, 3, 0;
%assign/v0 v0xf68be0_0, 0, 0;
%jmp T_6.1;
T_6.0 ;
%load/v 8, v0xf68be0_0, 3;
%mov 11, 0, 1;
%cmpi/u 8, 3, 4;
%jmp/0xz T_6.2, 4;
%ix/load 0, 3, 0;
%assign/v0 v0xf68be0_0, 0, 0;
%load/v 8, v0xf68f10_0, 1;
%ix/load 0, 1, 0;
%assign/v0 v0xf68b40_0, 0, 8;
%load/v 8, v0xf68b40_0, 1;
%mov 9, 0, 1;
%cmpi/u 8, 0, 2;
%mov 8, 4, 1;
%load/v 9, v0xf68f10_0, 1;
%mov 10, 0, 2;
%cmpi/u 9, 1, 3;
%mov 9, 4, 1;
%and 8, 9, 1;
%jmp/0xz T_6.4, 8;
%ix/load 0, 1, 0;
%assign/v0 v0xf68dd0_0, 0, 1;
T_6.4 ;
%load/v 8, v0xf68b40_0, 1;
%mov 9, 0, 2;
%cmpi/u 8, 1, 3;
%mov 8, 4, 1;
%load/v 9, v0xf68f10_0, 1;
%mov 10, 0, 1;
%cmpi/u 9, 0, 2;
%mov 9, 4, 1;
%and 8, 9, 1;
%jmp/0xz T_6.6, 8;
%ix/load 0, 1, 0;
%assign/v0 v0xf68c80_0, 0, 1;
T_6.6 ;
%jmp T_6.3;
T_6.2 ;
%load/v 8, v0xf68be0_0, 3;
%mov 11, 0, 29;
%addi 8, 1, 32;
%ix/load 0, 3, 0;
%assign/v0 v0xf68be0_0, 0, 8;
T_6.3 ;
T_6.1 ;
%load/v 8, v0xf68dd0_0, 1;
%mov 9, 0, 2;
%cmpi/u 8, 1, 3;
%jmp/0xz T_6.8, 4;
%ix/load 0, 1, 0;
%assign/v0 v0xf68dd0_0, 0, 0;
T_6.8 ;
%load/v 8, v0xf68c80_0, 1;
%mov 9, 0, 2;
%cmpi/u 8, 1, 3;
%jmp/0xz T_6.10, 4;
%ix/load 0, 1, 0;
%assign/v0 v0xf68c80_0, 0, 0;
T_6.10 ;
%load/v 8, v0xf68d30_0, 1;
%ix/load 0, 1, 0;
%assign/v0 v0xf68e70_0, 0, 8;
%load/v 8, v0xf68e70_0, 1;
%ix/load 0, 1, 0;
%assign/v0 v0xf68f10_0, 0, 8;
%jmp T_6;
.thread T_6;
.scope S_0xf51260;
T_7 ;
%wait E_0xf68d00;
%load/v 8, v0xf691f0_0, 1;
%mov 9, 0, 2;
%cmpi/u 8, 1, 3;
%jmp/0xz T_7.0, 4;
%load/v 8, v0xf690b0_0, 8;
%ix/load 0, 8, 0;
%assign/v0 v0xf69480_0, 0, 8;
%jmp T_7.1;
T_7.0 ;
%load/v 8, v0xf691f0_0, 1;
%mov 9, 0, 1;
%cmpi/u 8, 0, 2;
%jmp/0xz T_7.2, 4;
%load/v 8, v0xf692a0_0, 1;
%mov 9, 0, 2;
%cmpi/u 8, 1, 3;
%jmp/0xz T_7.4, 4;
%load/v 8, v0xf69340_0, 1;
%load/v 9, v0xf69480_0, 7; Select 7 out of 8 bits
%ix/load 0, 8, 0;
%assign/v0 v0xf69480_0, 0, 8;
T_7.4 ;
T_7.2 ;
T_7.1 ;
%jmp T_7;
.thread T_7;
# The file index is used to find the file name in the following table.
:file_names 5;
"N/A";
"<interactive>";
"FSM.v";
"./inputconditioner.v";
"./shiftregister.v";
Binary file added CompArch_Lab_2_FinalWriteup.pdf
View file
Open in desktop
Binary file not shown.
59 changes: 59 additions & 0 deletions FSM.t.v
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,59 @@
//`timescale 1 ns/ 1 ps
`include "FSM.v"

module FSMtest();

reg clk;
reg SCLKEdge;
reg ChipSelCond;
reg shiftRegOutPZero;
wire MISO_BUFE;
wire DM_WE;
wire ADDR_WE;
wire SR_WE;
// wire counter;

FSM trial1(clk, SCLKEdge, ChipSelCond, shiftRegOutPZero, MISO_BUFE, DM_WE, ADDR_WE, SR_WE);

initial clk=0;
always #10 clk=!clk; // 50MHz Clock



initial begin

$dumpfile("FSM.vcd");
$dumpvars();

// trial 1. Chip Sel = 1, SCLKEdge = 1, everything else should be zero.
$display("CS | MISO_BUFE | DM_WE | ADDR_WE | SR_WE");
ChipSelCond = 1; SCLKEdge = 1; #200
$display("%b | %b | %b | %b | %b ", ChipSelCond, MISO_BUFE, DM_WE, ADDR_WE, SR_WE);


// trial 2. Chip Sel = 0, SCLKEdge = 1, shiftRegOutPZero = 0 (write), everything else is zero
ChipSelCond = 0; SCLKEdge = 1; shiftRegOutPZero = 0; #200
$display("%b | %b | %b | %b | %b ", ChipSelCond, MISO_BUFE, DM_WE, ADDR_WE, SR_WE);

// intermediate. Chip Sel = 1, SCLKEdge = 1, shiftRegOutPZero = 1 (read), everything else is zero
ChipSelCond = 1; SCLKEdge = 1; shiftRegOutPZero = 1; #200
$display("%b | %b | %b | %b | %b ", ChipSelCond, MISO_BUFE, DM_WE, ADDR_WE, SR_WE);


// trial 3. Chip Sel = 0, SCLKEdge = 1, shiftRegOutPZero = 1 (read), everything else is zero
ChipSelCond = 0; SCLKEdge = 1; shiftRegOutPZero = 1; #200
$display("%b | %b | %b | %b | %b ", ChipSelCond, MISO_BUFE, DM_WE, ADDR_WE, SR_WE);

// intermediate. Chip Sel = 1, SCLKEdge = 1, shiftRegOutPZero = 1 (read), everything else is zero
ChipSelCond = 1; SCLKEdge = 1; shiftRegOutPZero = 1; #200
$display("%b | %b | %b | %b | %b ", ChipSelCond, MISO_BUFE, DM_WE, ADDR_WE, SR_WE);

// trial 3. Chip Sel = 0, SCLKEdge = 1, shiftRegOutPZero = 1 (write), DM_WE should turn on, everything else is zero
ChipSelCond = 0; SCLKEdge = 1; shiftRegOutPZero = 0; #600
$display("%b | %b | %b | %b | %b ", ChipSelCond, MISO_BUFE, DM_WE, ADDR_WE, SR_WE);

$finish;
end


endmodule
Loading