Submit Lab2

datamemory.v

@@ -17,7 +17,7 @@ module datamemory
     input [addresswidth-1:0]    address,
     input                       writeEnable,
     input [width-1:0]           dataIn
-)
+);
 
 
     reg [width-1:0] memory [depth-1:0];

fsm.t.v

@@ -0,0 +1,27 @@
+//Finite state machine test bench
+`timescale 1 ns / 1 ps
+`include "fsm.v"
+module testFSM();
+
+    reg lsb;
+    reg chipSelect;
+    reg clk;
+    wire sr_we;
+    wire addr_we;
+    wire dm_we;
+    wire[4:0] currentState;
+
+    fsm dut(lsb, chipSelect, clk, sr_we, addr_we, dm_we, currentState); 
+    initial clk=0;
+    always #10 clk=!clk;
+
+    initial begin
+        $dumpfile("fsm.vcd");
+        $dumpvars(0, testFSM);    
+        lsb=1;chipSelect=1; #350
+        $display("testing chip select");
+        chipSelect=0; #10
+
+        lsb=0;chipSelect=1;
+    end
+endmodule 

fsm.v

@@ -0,0 +1,196 @@
+//Finite state machine
+module fsm
+(
+input lsb,  //Least significant bit
+input chipSelect, //Chip select
+input clk,  //Serial clock
+output reg sr_we,
+output reg addr_we,
+output reg dm_we,
+output reg[4:0] currentState
+);
+    parameter beg = 0;
+    parameter loadA6 = 1;
+    parameter loadA5 = 2;
+    parameter loadA4 = 3;
+    parameter loadA3 = 4;
+    parameter loadA2 = 5;
+    parameter loadA1 = 6;
+    parameter loadA0 = 7;
+    parameter loadRW = 8;
+
+    parameter readD7 = 9;
+    parameter readD6 = 10;
+    parameter readD5 = 11;
+    parameter readD4 = 12;
+    parameter readD3 = 13;
+    parameter readD2 = 14;
+    parameter readD1 = 15;
+    parameter readD0 = 16;
+
+    parameter writeD7 = 17;
+    parameter writeD6 = 18;
+    parameter writeD5 = 19;
+    parameter writeD4 = 20;
+    parameter writeD3 = 21;
+    parameter writeD2 = 22;
+    parameter writeD1 = 23;
+    parameter writeD0 = 24;
+
+    initial currentState = beg;
+    always @(posedge clk) begin
+        if (!chipSelect && currentState == beg) begin
+            currentState <= loadA6;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == loadA6) begin
+            currentState <= loadA5;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == loadA5) begin
+            currentState <= loadA4;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == loadA4) begin
+            currentState <= loadA3;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == loadA3) begin
+            currentState <= loadA2;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == loadA2) begin
+            currentState <= loadA1;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == loadA1) begin
+            currentState <= loadA0;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == loadA0) begin
+            currentState <= loadRW;
+            sr_we <= 0;
+            addr_we <= 1;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == loadRW) begin
+            if (lsb == 1) begin
+                currentState <= readD7;
+                sr_we <= 1;
+                addr_we <= 0;
+                dm_we <= 0;
+            end
+            else begin
+                currentState <= writeD7;
+                sr_we <= 0;
+                addr_we <= 0;
+                dm_we <= 0;
+            end
+        end
+        else if (!chipSelect && currentState == readD7) begin
+            currentState <= readD6;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == readD6) begin
+            currentState <= readD5;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == readD5) begin
+            currentState <= readD4;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == readD4) begin
+            currentState <= readD3;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == readD3) begin
+            currentState <= readD2;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == readD2) begin
+            currentState <= readD1;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == readD1) begin
+            currentState <= readD0;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == writeD7) begin
+            currentState <= writeD6;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == writeD6) begin
+            currentState <= writeD5;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == writeD5) begin
+            currentState <= writeD4;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == writeD4) begin
+            currentState <= writeD3;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == writeD3) begin
+            currentState <= writeD2;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == writeD2) begin
+            currentState <= writeD1;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0;
+        end
+        else if (!chipSelect && currentState == writeD1) begin
+            currentState <= writeD0;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 1;
+        end
+        else begin
+            //Reset to begin state
+            currentState <= beg;
+            sr_we <= 0;
+            addr_we <= 0;
+            dm_we <= 0; 
+        end
+    end
+endmodule

inputconditioner.t.v

@@ -1,6 +1,8 @@
 //------------------------------------------------------------------------
 // Input Conditioner test bench
 //------------------------------------------------------------------------
+`timescale 1 ns / 1 ps
+`include "inputconditioner.v"
 
 module testConditioner();
 
@@ -11,19 +13,55 @@ module testConditioner();
     wire falling;
 
     inputconditioner dut(.clk(clk),
-    			 .noisysignal(pin),
+    		 .noisysignal(pin),
 			 .conditioned(conditioned),
 			 .positiveedge(rising),
-			 .negativeedge(falling))
+			 .negativeedge(falling));
 
 
     // Generate clock (50MHz)
     initial clk=0;
     always #10 clk=!clk;    // 50MHz Clock
 
     initial begin
+    $dumpfile("inputconditioner.vcd");
+    $dumpvars(0,testConditioner);
     // Your Test Code
     // Be sure to test each of the three conditioner functions:
     // Synchronization, Debouncing, Edge Detection
+
+    $display("clk  noisysignal  | conditioned  posedge  negedge | expected output");  
+    // initial condition
+    pin=0; #5 //Offsetting signal
+    pin=1; #100
+
+    // test input synchronization
+    pin=0; #100
+
+    // test debouncing & edge detection
+    pin=0; #100
+    pin=1; #20
+    pin=0; #30
+    pin=1; #150
+
+    pin=0; #10
+    pin=1; #20
+    pin=0; #100
+
+    // test maximum glitch
+    pin=1; #50
+    pin=0; #30
+    pin=1; #60
+    pin=0; #30
+    pin=1; #70
+    pin=0; #30
+    pin=1; #80
+    pin=0; #30
+    pin=1; #150
+    pin=0;
+
+    //Take a look at sync.png file for the waveform and confirm the proper behaviors
+
 
+    end    
 endmodule

inputconditioner.v

@@ -22,12 +22,21 @@ output reg  negativeedge    // 1 clk pulse at falling edge of conditioned
     reg synchronizer1 = 0;
 
     always @(posedge clk ) begin
-        if(conditioned == synchronizer1)
+        if(conditioned == synchronizer1) begin
             counter <= 0;
+            positiveedge <= 0;
+            negativeedge <= 0;
+        end
         else begin
             if( counter == waittime) begin
                 counter <= 0;
                 conditioned <= synchronizer1;
+                if (synchronizer1 == 1) begin
+                    positiveedge <= 1;
+                end
+                else begin
+                    negativeedge <= 1;
+                end
             end
             else 
                 counter <= counter+1;

midpoint.md

@@ -0,0 +1,11 @@
+Midpoint
+
+Since there are 4 leds on FPGA board, I put a MUX to control led by Switch 2. If Switch 2 is off, 0-3 bits are shown on LED. Otherwise, 4-7 bits are shown on LED.
+
+I tested the followings.
+1. Check the initial value(xA5 = 10100101). When Switch 2 is off, LED 0 and 2 are on and LED 1 and 3 are off.(x5 = 0101) When Switch 2 is on, LED 1 and 3 are on and LED 0 and 2 are off.(xA = 1010)
+2. When I turn Switch 1 on, if Switch 0 is off the bits shift up by one and 0 is loaded to the LSB(Least Significant Bit).
+3. Otherwise, if Switch 1 is on, then 1 is loaded to the LSB. 
+4. If I click Button 0, the value is reseted to the initial value.
+
+The test video is [here](https://drive.google.com/open?id=0BwRWdLa3OOtLUC1XQm1iU0lKaEU)