Ariana and Prava Lab 2 Submission

.gitignore

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+# Ignore compiled binaries
+*
+!/**/
+!*.*
+!makefile
+
+# Ignore gtkwave files
+*.vcd
+
+# Ignore vivado-related files and directories
+midpoint_testing
+*vivado*

MidpointTestSequence.txt

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+Midpoint Test Instructions
+
+
+PIPO:
+1. Press button 0 (parallelLoad) to load parallelDataIn (specified as 0xA5, or b10100101).
+2. Press button 1 to display the least significant bits. An LED ‘on’ state represents when a bit is 1 (and when it is off, it represents when a bit is 0). LEDs 0 and 2 should be on and LEDs 1 and 3 should be off in order to represent least significant bits ‘0101’.
+3. Press button 2 to display the most significant bits. LEDs 0 and 2 should be off and LEDs 1 and 3 should be on in order to represent the most significant bits ‘1010’.
+
+
+SIPO:
+1. Place switch 0 in the “low” position. This represents a 0 value bit. When switch 2 is toggled from low to high, the 0 bit will be serially loaded, and the bits in the shift register will shift up one degree from their previous places. 
+2. Press button 1. LEDs 0 and 2 will now be off, and LEDs 1 and 3 will be on.
+3. Press button 2. LEDs 0, 1, and 3 will be off, and LED 2 will be on.
+4. Place switch 0 in the high position, which represents a 1 value bit. Toggle switch 1 from low to high to serially load a 1 into the shift register.
+5. Press button 1. LEDs 0 and 2 will now be on, and LEDs 1 and 3 will be of.
+6. Press button 2. LEDs 1 and 2 will be off, and LEDs 0 and 4 will be on.

Work Plan.txt

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+Prava Dhulipalla, Ariana Olson
+Lab 2 Work Plan
+October 23, 2017
+
+
+Input Conditioning (6 hours - Finish by 10/24/17)
+* Complete inputconditioner.v        (1 hour)
+* Test bench demonstrates the 3 functions of the input conditioner (2.5 hours)
+* Test script executes testbench and makes gtkwave file (0.75 hours)
+* Circuit diagram (1 hour)
+* Analysis of max input glitch length at 50MHz that will be suppressed by a waittime of 10 (0.75 hours)
+Shift Register (4.25 hours - Finish by 10/24/17)
+* Complete shiftregister.v (1.5 hours)
+* Test bench demonstrating both modes of operation for shift register (2 hours)
+* Description of test bench strategy (0.75 hours)
+Midpoint Check-in (4 hours - Finish by 10/24/17)
+* Top-level module of given structure (0.5 hours)
+* Loading to FPGA (0.75 hours)
+   * Writing wrapper class (0.75 hours)
+* Design a test sequence demonstrating successful operation of this portion of lab (1 hour)
+   * Write a short, written description (0.75 hours)
+* Demonstrate to a Ninja (0.25 hours)
+SPI Memory (3.5 hours - Finish by 10/27/17)
+* Design and implement Finite State Machine (2.5 hours)
+* Implement SPI memory meeting specifications defined by waveform (1 hour)
+SPI Memory Testing (3.5 hours - Finish by 10/28/17)
+* Create a test bench (2 hours)
+* Have detailed analysis of testing strategy in report (1.5 hours)
+* External testing with Arduino (optional) (+ 1.5 hours if we decide to pursue)
+Debugging (4+ hours - Finish by 11/1/17)
+* Make appointments with Ben and/or NINJAS
+Make it Pretty (1.5 hours - Finish by 11/1/17)
+* Makefile, run test script (0.5 hours)
+* Clean code and comments (1 hours)
+Final Report (0.25 hours - Finish by 11/2/17)
+* All analysis and information requested in previous sections (should already be done)
+* Reflection of work plan vs reality (0.25 hours)
+
+
+Total time spent: 27.5 hours

addresslatch.v

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+//------------------------------------------------------------------------
+// Address Latch
+//   Positive edge triggered
+//   If writeEnable is true, addressOut is equal to addressIn 
+//   otherwise, addressOut holds its previous value
+//------------------------------------------------------------------------
+
+module addresslatch
+#(
+    parameter width  = 7
+)
+(
+    input [width-1:0] addressIn,
+    input writeEnable,
+    input clk,
+    output reg [width-1:0] addressOut
+);
+
+    always @(posedge clk) begin
+        if(writeEnable) begin
+            addressOut[width-1:0] <= addressIn[width-1:0];
+        end
+    end
+
+endmodule

datamemory.v

@@ -17,7 +17,7 @@ module datamemory
     input [addresswidth-1:0]    address,
     input                       writeEnable,
     input [width-1:0]           dataIn
-)
+);
 
 
     reg [width-1:0] memory [depth-1:0];

dflipflop.v

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+//------------------------------------------------------------------------
+// D Flip Flop
+//   Positive edge triggered
+//   If writeEnable is true, q is equal to d 
+//   otherwise, q holds its previous value
+//------------------------------------------------------------------------
+
+module dflipflop
+(
+    input d,
+    input writeEnable,
+    input clk,
+    output reg q
+);
+
+    always @(posedge clk) begin
+        if(writeEnable) begin
+            q <= d;
+        end
+    end
+
+endmodule

fsm.filter

@@ -0,0 +1,8 @@
+# Filter file for GTKWave
+
+000001	START
+000010	RECEIVE
+000100	WRITE
+001000	READ0
+010000	READ1
+100000  END

fsm.t.v

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+`timescale 1ns / 1ps
+
+`include "fsm.v"
+
+module fsm_test ();
+	reg sclk, chip_sel, shift_reg_out;
+	wire miso_buff, dm_we, addr_we, sr_we;
+
+	fsm dut (.sclk(sclk), .chip_sel(chip_sel), .shift_reg_out(shift_reg_out),
+		.miso_buff(miso_buff), .dm_we(dm_we), .addr_we(addr_we), .sr_we(sr_we));
+
+
+		always begin
+        	#5 sclk = ~sclk;
+  	  	end
+
+	initial begin
+		$dumpfile("fsm.vcd");
+		$dumpvars();
+
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// chip_sel = 1; shift_reg_out = 1; #10
+		// $displayb("miso_buff: %b", miso_buff);
+		// $displayb("dm_we: %b", dm_we);
+		// $displayb("addr_we: %b", addr_we);
+		// $displayb("sr_we: %b", sr_we);
+
+		// chip_sel = 0;
+		// shift_reg_out = 0; #70
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// shift_reg_out = 0; #10
+		// sclk = 1; #5
+		// sclk = 0; #5
+
+		// shift_reg_out = 0; #80
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+
+		// chip_sel = 1; #5
+
+
+
+		sclk = 0;
+		chip_sel = 0;
+		shift_reg_out = 0; #80
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0;
+
+		shift_reg_out = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+		// sclk = 1; #5
+		// sclk = 0; #5
+
+		$displayb("miso_buff: %b", miso_buff);
+		$displayb("dm_we: %b", dm_we);
+		$displayb("addr_we: %b", addr_we);
+		$displayb("sr_we: %b", sr_we);
+
+		$finish();
+	end
+
+endmodule