Turn in Lab

Makefile

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+test: build
+	echo "Running ALU test bench"
+	./alu
+	echo -e "\n\nRunning memory test bench"
+	./memory
+	echo -e "\n\nRunning register file test bench"
+	./registerFile
+	echo -e "\n\nRunning CPU test bench"
+	./cpu
+
+build: alu.t.v alu.v cpu.t.v cpu.v memory.t.v memory.v registerFile.t.v registerFile.v
+	iverilog alu.t.v -o alu
+	iverilog cpu.t.v -o cpu
+	iverilog memory.t.v -o memory
+	iverilog registerFile.t.v -o registerFile
+
+clean:
+	rm alu cpu memory registerFile

alu.t.v

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+`include "alu.v"
+
+module aluTestBench();
+  reg signed [31:0] A;
+  reg signed [31:0] B;
+  reg        [1:0]  op;
+  wire signed[31:0] out;
+  wire eq;
+  reg dutPassed;
+  alu dut(out, eq, op, A, B);
+  initial begin
+    dutPassed = 1;
+    A = 32'd10;
+    B = 32'd14;
+    op = `addOp;
+    #1;
+    if(out != 24 || ^out === 1'bx) begin
+      $display("Add test failed");
+      dutPassed = 0;
+    end
+
+    A = 32'd10;
+    B = 32'd14;
+    op = `subOp;
+    #1;
+    if(out != -4 || ^out === 1'bx) begin
+      $display("Sub test failed");
+      dutPassed = 0;
+    end
+
+    A = 32'b00001111000011110000111100001111;
+    B = 32'b10101010101010101010101010101010;
+    op = `xorOp;
+    #1;
+    if(out != 32'b10100101101001011010010110100101 || ^out === 1'bx) begin
+      $display("Xor test failed");
+      dutPassed = 0;
+    end
+
+    A = 14;
+    B = 32;
+    op = `sltOp;
+    #1;
+    if(out != 1 || ^out === 1'bx) begin
+      $display("Slt test failed");
+      $display("14 >= 32");
+      dutPassed = 0;
+    end
+
+    A = 32;
+    B = 14;
+    op = `sltOp;
+    #1;
+    if(out != 0 || ^out === 1'bx) begin
+      $display("Slt test failed");
+      $display("32 < 14");
+      dutPassed = 0;
+    end
+
+    A = -14;
+    B = -32;
+    op = `sltOp;
+    #1;
+    if(out != 0 || ^out === 1'bx) begin
+      $display("Slt test failed");
+      $display("-14 < -32");
+      dutPassed = 0;
+    end
+
+    A = -32;
+    B = -14;
+    op = `sltOp;
+    #1;
+    if(out != 1 || ^out === 1'bx) begin
+      $display("Slt test failed");
+      $display("-32 >= -14");
+      dutPassed = 0;
+    end
+
+    A = 14;
+    B = -32;
+    op = `sltOp;
+    #1;
+    if(out != 0 || ^out === 1'bx) begin
+      $display("Slt test failed");
+      $display("14 < -32");
+      dutPassed = 0;
+    end
+
+    A = -32;
+    B = 14;
+    op = `sltOp;
+    #1;
+    if(out != 1 || ^out === 1'bx) begin
+      $display("Slt test failed");
+      $display("-32 >= 14");
+      dutPassed = 0;
+    end
+
+    A = 14;
+    B = 14;
+    op = `sltOp;
+    #1;
+    if(out != 0 || ^out === 1'bx) begin
+      $display("Slt test failed");
+      $display("14 < 14");
+      dutPassed = 0;
+    end
+
+    A = -14;
+    B = -14;
+    op = `sltOp;
+    #1;
+    if(out != 0 || ^out === 1'bx) begin
+      $display("Slt test failed");
+      $display("-14 < -14");
+      dutPassed = 0;
+    end
+
+    if(!eq || eq === 1'bx) begin
+      $display("eq tes failed");
+      $display("-14 != -14");
+    end
+    A = -14;
+    B = 14;
+    #1;
+    if(eq || eq === 1'bx) begin
+      $display("eq tes failed");
+      $display("-14 == 14");
+    end
+
+    if(dutPassed) begin
+      $display("DUT passed!");
+    end
+  end
+
+endmodule

alu.v

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+//ops: XOR, ADD, SUB, SLT
+`define xorOp 2'b00
+`define addOp 2'b01
+`define subOp 2'b10
+`define sltOp 2'b11
+
+module alu
+  #(
+  parameter width = 32
+  )
+  (output signed [width-1:0] out,
+   output eq,
+   input[1:0] op,
+   input signed [width-1:0] A,
+   input signed [width-1:0] B);
+
+  wire[width-1:0] outputs[4];
+
+  assign outputs[`xorOp] = A^B;
+  assign outputs[`addOp] = A+B;
+  assign outputs[`subOp] = A-B;
+  assign outputs[`sltOp][0] = A<B;
+  assign outputs[`sltOp][width-1:1] = {width{1'b0}};
+  assign eq = (A==B);
+  assign out[width-1:0] = outputs[op][width-1:0];
+
+
+endmodule

asmtest/ackermann.asm

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+#ackermann function: calculates A($t0, $t1)
+#https://en.wikipedia.org/wiki/Ackermann_function
+#will stackoverflow if m or n is greater than 4
+
+addi $t0, $zero, 3 #m = t0
+addi $t1, $zero, 3 #n = t1
+sw   $t0, 4($sp)         #push m
+sw   $t1  8($sp)         #push n
+addi $sp, $sp, 8
+jal ackermann             #ackermann(m, n);
+lw   $t2,   ($sp)         #pop the return value
+addi $sp, $sp, -4
+end:
+j end
+
+ackermann:
+lw   $t0, -4($sp)         # m = arg1
+lw   $t1,  0($sp)         # n = arg2
+addi $sp, $sp, -8              # pop two words
+
+bne  $t0, $zero, continue1# if m != 0 goto continue1
+addi $t2, $t1, 1          # t2 = n + 1
+sw   $t2, 4($sp)          # push return value
+addi $sp, $sp, 4          #push one word
+jr   $ra                  #return t2
+
+continue1:
+bne $t1, $zero, continue2
+#push locals
+sw   $ra,  4($sp)         #push our return address
+addi $t0, $t0, -1         # m = m -1;
+addi $t1, $zero, 1        # n = 1;
+sw   $t0, 8($sp)         #push m
+sw   $t1  12($sp)         #push n
+addi $sp, $sp, 12
+jal ackermann             #ackermann(m, n);
+lw   $t2,   ($sp)         #pop the return value
+lw   $ra, -4($sp)         #pop the return address
+addi $sp, $sp, -8         #pop 2 words
+sw   $t2, 4($sp)          #push return value
+addi $sp, $sp, 4          #push one word
+jr   $ra                  #return 
+continue2:
+#push locals
+sw   $t0,  4($sp)
+sw   $ra,  8($sp)         #push our return address
+addi $t1, $t1, -1         # n = n -1;
+sw   $t0, 12($sp)         #push m
+sw   $t1  16($sp)         #push n
+addi $sp, $sp, 16
+jal ackermann             #ackermann(m, n);
+lw   $t1,   ($sp)         #pop the return value
+lw   $ra, -4($sp)         #pop the return address
+lw   $t0, -8($sp)         #pop m
+addi $sp, $sp, -12        #pop 2 words
+addi $t0, $t0, -1         # n = n -1
+sw   $ra,  4($sp)         #push our return address
+sw   $t0, 8($sp)         #push m
+sw   $t1  12($sp)         #push n
+addi $sp, $sp, 12
+jal ackermann             #ackermann(m, n);
+lw   $t2,   ($sp)         #pop the return value
+lw   $ra, -4($sp)         #pop the return address
+addi $sp, $sp, -8         #pop 2 words
+sw   $t2, 4($sp)          #push return value
+addi $sp, $sp, 4          #push one word
+jr   $ra                  #return 
+

cpu.t.v

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+`include "cpu.v"
+
+module cpuTestBench();
+  reg clk;
+  reg[4:0] regAddr;
+  reg[13:0] memAddr;
+  wire[31:0] regTest;
+  wire[31:0] memTest;
+  wire interrupt;
+  reg[31:0] currentTest;
+  reg[31:0] expectedVals[12];
+  reg[31:0] i;
+  reg dutPassed = 1;
+
+  cpu dut(clk, regAddr, regTest,
+               memAddr, memTest,
+               interrupt);
+  initial begin
+     currentTest = 0;
+     //list of expected test values
+     //For the "source" of the program this test runs on the cpu
+     //see fullTest.asm
+     expectedVals[0] = 15;
+     expectedVals[1] = 20;
+     expectedVals[2] = 25;
+     expectedVals[3] = 30;
+     expectedVals[4] = 35;
+     expectedVals[5] = 40;
+     expectedVals[6] = 45;
+     expectedVals[7] = 9;
+     expectedVals[8] = 27;
+     expectedVals[9] = 3;
+     expectedVals[10] = 1;
+     expectedVals[11] = 0;
+     clk = 0;
+     memAddr = 100;
+     regAddr = 25; //t9
+     i = 0;
+     #5;
+     for(i = 0; i<10000; i = i + 1) begin
+     clk = 1; #5;
+     clk = 0; #5;
+     end
+     #25;
+     if(currentTest != 12) begin
+       $display("Didn't run enough tests!");
+       dutPassed = 0;
+     end
+     if(dutPassed) begin
+       $display("DUT passed!");
+     end
+     $finish();
+  end
+
+  //cpu interrupts every time it is ready to be tested
+  //we use syscall to fire interrupts
+  always @(posedge interrupt) begin
+    if(regTest != expectedVals[currentTest]) begin
+      $display("Failed test %d", currentTest);
+      $display("%d != %d", regTest, expectedVals[currentTest]);
+      dutPassed = 0;
+    end
+    currentTest = currentTest + 1;
+  end
+
+endmodule