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Submit Lab 3 report #19

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c183fb4
revise CPU design
ailuropoda0 Nov 15, 2017
ee1e8d6
update cpu control signal location
SungwooPark Nov 15, 2017
f3102e2
add signExtended module and fix error on CPU
ailuropoda0 Nov 16, 2017
0a7f860
revise CPU design
ailuropoda0 Nov 17, 2017
a5b5e27
submit lab report
ailuropoda0 Nov 17, 2017
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172 changes: 29 additions & 143 deletions cpu.v
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Original file line number Diff line number Diff line change
Expand Up @@ -4,32 +4,33 @@
`include "programCounter.v"
`include "regfile.v"
`include "alu.v"
`include "signExtended.v"

module cpu
(
input clk
);

//PCSel mux
reg[1:0] PCSel;
wire[1:0] PCSel;

//Program counter
wire[31:0] PCInput;
wire[31:0] PCOutput;
wire[3:0] PCLastFour;

//AdderMux
wire[31:0] adderMux1Out;
wire[31:0] adderMux2Out;
reg AdderValControl;
wire[31:0] adderMuxOut;

//Adder
wire[31:0] adderOut1;
wire[31:0] adderOut;

//instruction memory
wire[31:0] instrMemOut;
wire[25:0] jumpAddress;
wire[15:0] instrMemImm;
wire[31:0] extendedInstrMemImm;
wire[5:0] opCode;
wire[4:0] rs;
wire[4:0] rt;
Expand All @@ -46,166 +47,51 @@ assign functionCode = instrMemOut[5:0];
//registerMux
wire[31:0] registerMux1Out;
wire[4:0] registerMux2Out;
reg[1:0] RegDataWrSel;
reg[1:0] RegAddrWrSel;
wire[1:0] RegDataWrSel;
wire[1:0] RegAddrWrSel;

//register
wire[31:0] regOut1;
wire[31:0] regOut2;
reg RegWrEn;
wire RegWrEn;

//branchControlMux
wire branchControlOut;
reg BranchControl;
wire BranchControl;

//alu Mux
reg ALUImm;
wire ALUImm;
wire[31:0] aluMuxOut;

//alu
wire[31:0] aluOut;
wire carryout;
wire zero;
wire overflow;
reg[2:0] command;
wire[2:0] command;

//Data Memory
wire[31:0] dataMemOut;
reg MemWrEn;
wire MemWrEn;

mux4input PCSelMux(PCInput, PCSel, {PCLastFour, jumpAddress, 2'b00}, regOut1, adderOut, adderOut);
mux4input CSelMux(PCInput, PCSel, {PCLastFour, jumpAddress, 2'b00}, regOut1, adderOut, adderOut);
programCounter PC(PCOutput, PCLastFour, PCInput, 1, clk);
mux2input adderMux1(adderMux1Out, branchControlOut, instrMemImm, PCOutput);
mux2input adderMux2(adderMux2Out, AdderValControl, 32'd4, 32'd8);
ALU adder(.result(adderOut), .operandA(adderMux1Out), .operandB(adderMux2Out), .command(3'd0));
instrMemory instrMem(.clk(clk), .Addr(PCOutput), .DataOut(instrMemOut), .regWE(0));
signExtended extend(extendedInstrMemImm, instrMemImm);
mux2input adderMux(adderMuxOut, branchControlOut, extendedInstrMemImm[29:0]<<2, 0);
ALU pcAdder1(.result(adderOut1), .operandA(PCOutput), .operandB(32'd4), .command(3'd0));
ALU pcAdder2(.result(adderOut), .operandA(adderMuxOut), .operandB(adderOut1), .command(3'd0));
instrMemory instrMem(.clk(clk), .Addr(PCOutput[9:0]), .DataOut(instrMemOut),
.regWE(0), .RegWrEn(RegWrEn), .MemWrEn(MemWrEn), .PCSel(PCSel), .RegDataWrSel(RegDataWrSel),
.RegAddrWrSel(RegAddrWrSel), .BranchControl(BranchControl), .ALUImm(ALUImm), .command(command));
mux4input registerMux1(.out(registerMux1Out), .address(RegDataWrSel), .in0(aluOut), .in1(dataMemOut), .in3(adderOut));
mux4input registerMux2(.out(registerMux2Out), .address(RegAddrWrSel), .in0(rd), .in1(rt), .in3(5'd31));
regfile register(.ReadData1(regOut1), .ReadData2(regOut2), .WriteData(registerMux1Out), .ReadRegister1(rs), .ReadRegister2(rt), .WriteRegister(registerMux2Out), .RegWrite(RegWrEn), .Clk(clk));
mux2input aluMux(aluMuxOut, ALUImm, regOut2, instrMemImm);

always @(posedge clk) begin
//Decoding op code to alu operation command
if (opCode == 6'h23) begin //lw
RegWrEn <= 1'b1;
MemWrEn <= 1'b0;
PCSel <= 2'b10;
AdderValControl <= 1'b0;
RegDataWrSel <= 2'b01;
RegAddrWrSel <= 2'b01;
BranchControl <= 1'b1;
ALUImm <= 1'b1;
end
if (opCode == 6'h2b) begin //sw
RegWrEn <= 1'b0;
MemWrEn <= 1'b1;
PCSel <= 2'b10;
AdderValControl <= 1'b0;
RegDataWrSel <= 2'b01;
RegAddrWrSel <= 2'b01;
BranchControl <= 1'b1;
ALUImm <= 1'b1;
end
if (opCode == 6'h2) begin //j
RegWrEn <= 1'b0;
MemWrEn <= 1'b0;
PCSel <= 2'b00;
AdderValControl <= 1'b0;
RegDataWrSel <= 2'b01;
RegAddrWrSel <= 2'b01;
BranchControl <= 1'b1;
ALUImm <= 1'b1;
end
if (opCode == 6'h0 && functionCode == 6'h08) begin //jr
RegWrEn <= 1'b0;
MemWrEn <= 1'b0;
PCSel <= 2'b01;
AdderValControl <= 1'b0;
RegDataWrSel <= 2'b01;
RegAddrWrSel <= 2'b01;
BranchControl <= 1'b1;
ALUImm <= 1'b1;
end
if (opCode == 6'h3) begin //jal
RegWrEn <= 1'b1;
MemWrEn <= 1'b0;
PCSel <= 2'b00;
AdderValControl <= 1'b1;
RegDataWrSel <= 2'b11;
RegAddrWrSel <= 2'b11;
BranchControl <= 1'b1;
ALUImm <= 1'b1;
end
if (opCode == 6'd5) begin //bne
RegWrEn <= 1'b0;
MemWrEn <= 1'b0;
PCSel <= 2'b10;
AdderValControl <= 1'b0;
RegDataWrSel <= 2'b01;
RegAddrWrSel <= 2'b01;
BranchControl <= 1'b0;
ALUImm <= 1'b1;
command <= 3'd1;
end
if (opCode == 6'd14) begin //xori
command <= 3'd2;
RegWrEn <= 1'b1;
MemWrEn <= 1'b0;
PCSel <= 2'b10;
AdderValControl <= 1'b0;
RegDataWrSel <= 2'b00;
RegAddrWrSel <= 2'b01;
BranchControl <= 1'b1;
ALUImm <= 1'b1;
end
if (opCode == 6'd8) begin //addi
command <= 3'd0;
RegWrEn <= 1'b1;
MemWrEn <= 1'b0;
PCSel <= 2'b10;
AdderValControl <= 1'b0;
RegDataWrSel <= 2'b00;
RegAddrWrSel <= 2'b01;
BranchControl <= 1'b1;
ALUImm <= 1'b1;
end
if (opCode == 6'd0 && functionCode == 6'h20) begin //add
command <= 3'd0;
RegWrEn <= 1'b1;
MemWrEn <= 1'b0;
PCSel <= 2'b10;
AdderValControl <= 1'b0;
RegDataWrSel <= 2'b00;
RegAddrWrSel <= 2'b00;
BranchControl <= 1'b1;
ALUImm <= 1'b0;
end
if (opCode == 6'd0 && functionCode == 6'h22) begin //sub
command <= 3'd1;
RegWrEn <= 1'b1;
MemWrEn <= 1'b0;
PCSel <= 2'b10;
AdderValControl <= 1'b0;
RegDataWrSel <= 2'b00;
RegAddrWrSel <= 2'b00;
BranchControl <= 1'b1;
ALUImm <= 1'b0;
end
if (opCode == 6'd0 && functionCode == 6'h2a) begin //slt
command <= 3'd3;
RegWrEn <= 1'b1;
MemWrEn <= 1'b0;
PCSel <= 2'b10;
AdderValControl <= 1'b0;
RegDataWrSel <= 2'b00;
RegAddrWrSel <= 2'b00;
BranchControl <= 1'b1;
ALUImm <= 1'b0;
end
end

ALU alu(.result(aluOut), .carryout(carryout), .zero(zero), .overflow(overflow), .operandA(regOut1), .operandB(aluMuxOut), .command(command));
mux2input branchControlMux(branchControlOut, BranchControl, zero, 1'b0);
dataMemory dataMem(.clk(clk), .regWE(MemWrEn), .Addr(aluOut), .DataIn(regOut2), .DataOut(dataMemOut));
mux4input #(5) registerMux2(.out(registerMux2Out), .address(RegAddrWrSel), .in0(rd), .in1(rt), .in3(5'd31));
regfile register(.ReadData1(regOut1), .ReadData2(regOut2), .WriteData(registerMux1Out), .ReadRegister1(rs), .ReadRegister2(rt),
.WriteRegister(registerMux2Out), .RegWrite(RegWrEn), .Clk(clk));
mux2input aluMux(aluMuxOut, ALUImm, regOut2, extendedInstrMemImm);

ALU alu(.result(aluOut), .carryout(carryout), .zero(zero), .overflow(overflow),
.operandA(regOut1), .operandB(aluMuxOut), .command(command));
mux2input #(1) branchControlMux(branchControlOut, BranchControl, zero, 1'b1);
dataMemory dataMem(.clk(clk), .regWE(MemWrEn), .Addr(aluOut[9:0]), .DataIn(regOut2), .DataOut(dataMemOut));

endmodule
2 changes: 1 addition & 1 deletion dataMemory.v
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Expand Up @@ -14,7 +14,7 @@ module dataMemory
end
end

initial $readmemh("dataMemory.dat", mem);
//initial $readmemh("dataMemory.dat", mem);

assign DataOut = mem[Addr];
endmodule
133 changes: 128 additions & 5 deletions instrMemory.v
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Original file line number Diff line number Diff line change
@@ -1,10 +1,19 @@
//Instruction memory
module instrMemory
(
input clk, regWE,
input clk, regWE, // clock, register Write Enable
input[9:0] Addr,
input[31:0] DataIn,
output[31:0] DataOut
output[31:0] DataOut,
// control signal
output reg RegWrEn,
output reg MemWrEn,
output reg[1:0] PCSel,
output reg[1:0] RegDataWrSel,
output reg[1:0] RegAddrWrSel,
output reg BranchControl,
output reg ALUImm,
output reg[2:0] command
);

reg [31:0] mem[1023:0];
Expand All @@ -15,7 +24,121 @@ module instrMemory
end
end

initial $readmemh("instrMemory.dat", mem);

assign DataOut = mem[Addr];
initial $readmemh("subTest.dat", mem);

initial begin
BranchControl = 1'b1;
PCSel = 2'b10;
end

assign DataOut = mem[Addr>>2];

always @(negedge clk) begin
//Decoding op code to alu operation command
if (DataOut[31:26] == 6'h23) begin //lw
RegWrEn <= 1'b1;
MemWrEn <= 1'b0;
PCSel <= 2'b10;
RegDataWrSel <= 2'b01;
RegAddrWrSel <= 2'b01;
BranchControl <= 1'b1;
ALUImm <= 1'b1;
end
if (DataOut[31:26] == 6'h2b) begin //sw
RegWrEn <= 1'b0;
MemWrEn <= 1'b1;
PCSel <= 2'b10;
RegDataWrSel <= 2'b01;
RegAddrWrSel <= 2'b01;
BranchControl <= 1'b1;
ALUImm <= 1'b1;
end
if (DataOut[31:26] == 6'h2) begin //j
RegWrEn <= 1'b0;
MemWrEn <= 1'b0;
PCSel <= 2'b00;
RegDataWrSel <= 2'b01;
RegAddrWrSel <= 2'b01;
BranchControl <= 1'b1;
ALUImm <= 1'b1;
end
if (DataOut[31:26] == 6'h0 && DataOut[5:0] == 6'h08) begin //jr
RegWrEn <= 1'b0;
MemWrEn <= 1'b0;
PCSel <= 2'b01;
RegDataWrSel <= 2'b01;
RegAddrWrSel <= 2'b01;
BranchControl <= 1'b1;
ALUImm <= 1'b1;
end
if (DataOut[31:26] == 6'h3) begin //jal
RegWrEn <= 1'b1;
MemWrEn <= 1'b0;
PCSel <= 2'b00;
RegDataWrSel <= 2'b11;
RegAddrWrSel <= 2'b11;
BranchControl <= 1'b1;
ALUImm <= 1'b1;
end
if (DataOut[31:26] == 6'd5) begin //bne
command <= 3'd1;
RegWrEn <= 1'b0;
MemWrEn <= 1'b0;
PCSel <= 2'b10;
RegDataWrSel <= 2'b01;
RegAddrWrSel <= 2'b01;
BranchControl <= 1'b0;
ALUImm <= 1'b0;
end
if (DataOut[31:26] == 6'd14) begin //xori
command <= 3'd2;
RegWrEn <= 1'b1;
MemWrEn <= 1'b0;
PCSel <= 2'b10;
RegDataWrSel <= 2'b00;
RegAddrWrSel <= 2'b01;
BranchControl <= 1'b1;
ALUImm <= 1'b1;
end
if (DataOut[31:26] == 6'd8) begin //addi
command <= 3'd0;
RegWrEn <= 1'b1;
MemWrEn <= 1'b0;
PCSel <= 2'b10;
RegDataWrSel <= 2'b00;
RegAddrWrSel <= 2'b01;
BranchControl <= 1'b1;
ALUImm <= 1'b1;
end
if (DataOut[31:26] == 6'd0 && DataOut[5:0] == 6'h20) begin //add
command <= 3'd0;
RegWrEn <= 1'b1;
MemWrEn <= 1'b0;
PCSel <= 2'b10;
RegDataWrSel <= 2'b00;
RegAddrWrSel <= 2'b00;
BranchControl <= 1'b1;
ALUImm <= 1'b0;
end
if (DataOut[31:26] == 6'd0 && DataOut[5:0] == 6'h22) begin //sub
command <= 3'd1;
RegWrEn <= 1'b1;
MemWrEn <= 1'b0;
PCSel <= 2'b10;
RegDataWrSel <= 2'b00;
RegAddrWrSel <= 2'b00;
BranchControl <= 1'b1;
ALUImm <= 1'b0;
end
if (DataOut[31:26] == 6'd0 && DataOut[5:0] == 6'h2a) begin //slt
command <= 3'd3;
RegWrEn <= 1'b1;
MemWrEn <= 1'b0;
PCSel <= 2'b10;
RegDataWrSel <= 2'b00;
RegAddrWrSel <= 2'b00;
BranchControl <= 1'b1;
ALUImm <= 1'b0;
end
end
endmodule
3 changes: 3 additions & 0 deletions programCounter.v
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Expand Up @@ -7,6 +7,9 @@ input[31:0] newCount,
input wrenable,
input clk
);
initial begin
currentCount = -4;
end

always @(posedge clk) begin
if(wrenable) begin
Expand Down
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