Rocco, Kaitlyn, Kim, David Lab 3 submission

Makefile

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+# Assembly simulation in Verilog unified Makefile example
+
+include settings.mk
+
+GTKWAVE := gtkwave
+SIM     := vvp
+
+# Final waveform to produce is the combination of machine and program
+WAVEFORM := $(TOPLEVEL)-$(PROGRAM).vcd
+WAVEOPTS := filters/$(WAVEFORM:vcd=gtkw)
+
+
+# Build memory image, compile Verilog, run simulation to produce VCD trace
+$(WAVEFORM): settings.mk
+	$(MAKE) -C asm $(MEMDUMP)
+	$(MAKE) -C verilog $(TOPLEVEL).vvp
+	$(SIM) verilog/$(TOPLEVEL).vvp +mem_fn=asm/$(MEMDUMP) +dump_fn=$@
+
+
+# Open waveform with saved formatting and filter options
+scope: $(WAVEFORM) $(WAVEOPTS)
+	$(GTKWAVE) $(WAVEOPTS)
+
+
+# Remove generated files, including from subdirectories
+clean: 
+	$(MAKE) -C asm clean
+	$(MAKE) -C verilog clean
+	rm -f $(WAVEFORM)
+
+.PHONY: scope clean

add32bit.t.v

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+// Test bench for 32 bit adder
+
+`timescale 1 ns / 1 ps
+`include "add32bit.v"
+
+module test32bitAdder();
+
+reg[31:0] a;
+reg[31:0] b;
+wire[31:0] c;
+wire overflow;
+
+add32bit test(a, b, c, overflow); 
+
+initial begin
+  // Add some numbers with no overflow
+  a = 32'd7;
+  b = 32'd6;
+  #50;
+  $display("6 + 7 = %d", c);
+  $display("overlow: %b", overflow);
+  a = 32'd657;
+  b = 32'd912;
+  #50;
+  $display("657 + 912 = %d", c);
+  $display("overlow: %b", overflow);
+  a = 32'd700;
+  b = 32'd900;
+  #50;
+  $display("700 + 900 = %d", c);
+  $display("overlow: %b", overflow);
+  // Add some numbers with overflow
+  a = 32'd2**31-5;
+  b = 32'd2**31-10;
+  #50;
+  $display("overflow: %d", c);
+  $display("overlow: %b", overflow);
+  a = -32'sd2**31-5;
+  b = -32'sd2**31-10;
+  #50;
+  $display("overflow %d", c);
+  $display("overlow: %b", overflow);
+  // add a positive and a negative
+  a = -32'sd700;	
+  b = 32'd900;
+  #50;
+  $display("-700 + 900 = %d", c);
+  $display("overlow: %b", overflow);
+end
+endmodule

add32bit.v

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+// 32 bit adder
+
+module add32bit (
+  input[31:0] a,
+  input[31:0] b,
+  output reg[31:0] c,
+  output overflow
+);
+
+reg carry;
+wire carryXorSign;
+wire sameSign;
+
+  xnor signTest(sameSign, a[31], b[31]);
+  xor adder(carryXorSign, carry, c[31]);
+  and ovrflTest(overflow, carryXorSign, sameSign);
+
+always @(a or b) begin
+  {carry, c} = a + b;
+end
+endmodule

adder.v

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+// Adder circuit
+
+module behavioralFullAdder
+(
+    output sum, 
+    output carryout,
+    input a, 
+    input b, 
+    input carryin
+);
+    // Uses concatenation operator and built-in '+'
+    assign {carryout, sum}=a+b+carryin;
+endmodule
+
+module structuralFullAdder
+(
+    output sum, 
+    output carryout,
+    input a, 
+    input b, 
+    input carryin
+);
+    wire ab;    //setting up wires
+    wire acarryin;
+    wire bcarryin;
+    wire orpairintermediate;
+    wire orsingleintermediate;
+    wire orall;
+    wire andsumintermediate;
+    wire andsingleintermediate;
+    wire andall;
+    wire invcarryout;
+    and andab(ab, a, b);  // a and b
+    and andacarryin(acarryin, a, carryin);    // a and carryin
+    and andbcarryin(bcarryin, b, carryin);    // b and carryin
+    or orpair(orpairintermediate, ab, acarryin);  // (a and b) or (a and carryin)
+    or orcarryout(carryout, orpairintermediate, bcarryin);    // ((a and b) or (a and carryin)) or (b and carryin)
+    or orintermediate(orsingleintermediate, a, b);    // a or b
+    or orallinputs(orall, orsingleintermediate, carryin); // (a or b) or carryin
+    not inv(invcarryout, carryout);   // not carryout
+    and sumintermediate(andsumintermediate, invcarryout, orall);  // (a or b or carryin) and not carryout
+    and andintermediate(andsingleintermediate, a, b); // a and b
+    and andallinputs(andall, andsingleintermediate, carryin); // (a and b) and carryin
+    or adder(sum, andsumintermediate, andall);    // ((a or b or carryin) and not carryout) or (a and b and c)
+endmodule
+
+module FullAdder4bit
+(
+  output[3:0] sum,  // 2's complement sum of a and b
+  output carryout,  // Carry out of the summation of a and b
+  output overflow,  // True if the calculation resulted in an overflow
+  input[3:0] a,     // First operand in 2's complement format
+  input[3:0] b,      // Second operand in 2's complement format
+  input carryin
+);
+    wire carryout1; // wire setup for carryouts from each adder
+    wire carryout2;
+    wire carryout3;
+    wire aandb;
+    wire anorb;
+    wire bandsum;
+    wire bnorsum;
+    wire abandnoror;
+    wire bsumandnornor;
+    structuralFullAdder  adder1(sum[0], carryout1, a[0], b[0], carryin);   // first adder to handle the first added bits
+    structuralFullAdder  adder2(sum[1], carryout2, a[1], b[1], carryout1);   // second adder to take the carryout from the first adder and the next added bits
+    structuralFullAdder  adder3(sum[2], carryout3, a[2], b[2], carryout2);   // third adder to take the second carryout and the third added bits
+    structuralFullAdder  adder4(sum[3], carryout, a[3], b[3], carryout3);    // fourth adder to take the third carryout and the fourth bits
+    and  andinputs(aandb, a[3], b[3]);   // logic to determine overflow (overflow occurs when two positives result in a negative or two negatives result in a positive, the larges bit in both inputs are equal and the largest bit in the output is not the same)
+    nor  norinputs(anorb, a[3], b[3]);
+    and  andsum(bandsum, b[3], sum[3]);
+    nor  norsum(bnorsum, b[3], sum[3]);
+    or  orinputcombs(abandnoror, aandb, anorb);
+    nor  norsumcombs(bsumandnornor, bandsum, bnorsum);
+    and  finaland(overflow, abandnoror, bsumandnornor);
+endmodule

adder1bit.v

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+`define AND and #30
+`define OR or #30
+`define NOT not #10
+`define XOR xor #30
+`define NOR nor #20
+`define NAND nand #20
+
+module Adder1bit
+(
+    output sum,
+    output carryout,
+    input a,
+    input b,
+    input carryin
+);
+    wire aandb, aorb;
+    wire s, _carryin;
+    wire outputIfCarryin, outputIf_Carryin;
+    `XOR(s, a, b);
+    `XOR(sum, s, carryin);
+    `AND(aandb, a, b);
+    `OR(aorb, a, b);
+    `NOT(_carryin, carryin);
+    `AND(outputIfCarryin, aandb, _carryin);
+    `AND(outputIf_Carryin, aorb, carryin);
+    `OR(carryout, outputIfCarryin, outputIf_Carryin);
+endmodule