Pull request

HOW_TO_RUN.md

@@ -0,0 +1,23 @@
+# How to Run Test Benches
+
+```shell
+$ make run
+```
+
+## To run CPU tests
+
+```shell
+$ make cpu
+```
+
+## To run submodule test benches
+
+```shell
+$ make tests
+```
+
+## To clean directory
+
+```shell
+$ make clean
+```

Makefile

@@ -0,0 +1,30 @@
+cpu: cpu_test_addN.t.v cpu_test_fib.t.v cpu_test_xor_sub_slt.t.v
+	iverilog -o cpu_test_addN.o cpu_test_addN.t.v
+	iverilog -o cpu_test_fib.o cpu_test_fib.t.v
+	iverilog -o cpu_test_xor_sub_slt.o cpu_test_xor_sub_slt.t.v
+	./cpu_test_addN.o
+	./cpu_test_fib.o
+	./cpu_test_xor_sub_slt.o
+
+tests: alu.t.v basicbuildingblocks.t.v instructiondecoder.t.v lut.t.v memory.t.v regfile.t.v
+	iverilog -o alu.o alu.t.v
+	iverilog -o basicbuildingblocks.o basicbuildingblocks.t.v
+	iverilog -o instructiondecoder.o instructiondecoder.t.v
+	iverilog -o lut.o lut.t.v
+	iverilog -o memory.o memory.t.v
+	iverilog -o regfile.o regfile.t.v
+	./alu.o
+	./basicbuildingblocks.o
+	./instructiondecoder.o
+	./lut.o
+	./memory.o
+	./regfile.o
+
+clean:
+	rm *.o
+	rm *.vcd
+
+run:
+	make cpu
+	make tests
+	make clean

alu.t.v

@@ -0,0 +1,246 @@
+//------------------------------------------------------------------------
+// Test Bench for ALU Module
+//------------------------------------------------------------------------
+
+`timescale 1 ns / 1 ps
+`include "alu.v"
+
+module testALU();
+    reg  [31:0] operandA, operandB;
+    reg  [2:0]  command;
+    wire [31:0] result;
+    wire carryout, zero, overflow;
+
+    ALU aluer (result, carryout, zero, overflow, operandA, operandB, command);
+
+    initial begin
+        $display("--------------------------------------------------");
+        $display("ALU tests starting...");
+
+        $display("Starting ADD tests...");
+        // ADD test 1
+        command=`ADD; operandA=32'h000A0000; operandB=32'h00000070; #5000   // carryout = 0
+        if(result != 32'h000A0070)
+        $display("ADD test 1 - result: %h, expected: 000A0070", result);
+        if(carryout != 1'b0)
+        $display("ADD test 1 - carryout: %h, expected: 0", carryout);
+        if(zero != 1'b0)
+        $display("ADD test 1 - zero: %h, expected: 0", zero);
+        if(overflow != 1'b0)
+        $display("ADD test 1 - overflow: %h, expected: 0", overflow);
+        // ADD test 2
+        command=`ADD; operandA=32'h7FFFFFFF; operandB=32'h7FFFFFFF; #5000
+        if(result != 32'hFFFFFFFE)
+        $display("ADD test 2 - result: %h, expected: FFFFFFFE", result);
+        if(carryout != 1'b0)
+        $display("ADD test 2 - carryout: %h, expected: 0", carryout);
+        if(zero != 1'b0)
+        $display("ADD test 2 - zero: %h, expected: 0", zero);
+        if(overflow != 1'b1)
+        $display("ADD test 2 - overflow: %h, expected: 1", overflow);
+        // ADD test 3
+        command=`ADD; operandA=32'h00000001; operandB=32'hFFFFFFFF; #5000
+        if(result != 32'h00000000)
+        $display("ADD test 3 - result: %h, expected: 00000000", result);
+        if(carryout != 1'b1)
+        $display("ADD test 3 - carryout: %h, expected: 1", carryout);
+        if(zero != 1'b1)
+        $display("ADD test 3 - zero: %h, expected: 1", zero);
+        if(overflow != 1'b0)
+        $display("ADD test 3 - overflow: %h, expected: 0", overflow);
+        // ADD test 4
+        command=`ADD; operandA=32'h80000000; operandB=32'h80000000; #5000
+        if(result != 32'h00000000)
+        $display("ADD test 4 - result: %h, expected: 00000000", result);
+        if(carryout != 1'b1)
+        $display("ADD test 4 - carryout: %h, expected: 1", carryout);
+        if(zero != 1'b1)
+        $display("ADD test 4 - zero: %h, expected: 1", zero);
+        if(overflow != 1'b1)
+        $display("ADD test 4 - overflow: %h, expected: 1", overflow);
+
+        $display("Starting SUB tests...");
+        // SUB test 1
+        command=`SUB; operandA=32'h000A0000; operandB=32'hFFFFFF90; #5000
+        if(result != 32'h000A0070)
+        $display("SUB test 1 - result: %h, expected: 000A0070", result);
+        if(carryout != 1'b0)
+        $display("SUB test 1 - carryout: %h, expected: 0", carryout);
+        if(zero != 1'b0)
+        $display("SUB test 1 - zero: %h, expected: 0", zero);
+        if(overflow != 1'b0)
+        $display("SUB test 1 - overflow: %h, expected: 0", overflow);
+        // SUB test 2
+        command=`SUB; operandA=32'h7FFFFFFF; operandB=32'h80000001; #5000
+        if(result != 32'hFFFFFFFE)
+        $display("SUB test 2 - result: %h, expected: FFFFFFFE", result);
+        if(carryout != 1'b0)
+        $display("SUB test 2 - carryout: %h, expected: 0", carryout);
+        if(zero != 1'b0)
+        $display("SUB test 2 - zero: %h, expected: 0", zero);
+        if(overflow != 1'b1)
+        $display("SUB test 2 - overflow: %h, expected: 1", overflow);
+        // SUB test 3
+        command=`SUB; operandA=32'h00000001; operandB=32'h00000001; #5000
+        if(result != 32'h00000000)
+        $display("SUB test 3 - result: %h, expected: 00000000", result);
+        if(carryout != 1'b1)
+        $display("SUB test 3 - carryout: %h, expected: 1", carryout);
+        if(zero != 1'b1)
+        $display("SUB test 3 - zero: %h, expected: 1", zero);
+        if(overflow != 1'b0)
+        $display("SUB test 3 - overflow: %h, expected: 0", overflow);
+        //SUB test 4
+        command=`SUB; operandA=32'h80000000; operandB=32'h70000000; #5000
+        if(result != 32'h10000000)
+        $display("SUB test 4 - result: %h, expected: 10000000", result);
+        if(carryout != 1'b1)
+        $display("SUB test 4 - carryout: %h, expected: 1", carryout);
+        if(zero != 1'b0)
+        $display("SUB test 4 - zero: %h, expected: 0", zero);
+        if(overflow != 1'b1)
+        $display("SUB test 4 - overflow: %h, expected: 1", overflow);
+
+        $display("Starting XOR tests...");
+        // XOR test 1
+        command=`Xor; operandA=32'h88888888; operandB=32'h11111111; #5000
+        if(result != 32'h99999999)
+        $display("XOR test 1 - result: %h, expected: 99999999", result);
+        if(zero != 1'b0)
+        $display("XOR test 1 - zero: %h, expected: 0", zero);
+        // XOR test 2
+        command=`Xor; operandA=32'hCCCCCCCC; operandB=32'hCCCCCCCC; #5000
+        if(result != 32'h00000000)
+        $display("XOR test 2 - result: %h, expected: 00000000", result);
+        if(zero != 1'b1)
+        $display("XOR test 2 - zero: %h, expected: 1", zero);
+        // XOR test 3
+        command=`Xor; operandA=32'hBBBBBBBB; operandB=32'h55555555; #5000
+        if(result != 32'hEEEEEEEE)
+        $display("XOR test 3 - result: %h, expected: EEEEEEEE", result);
+        if(zero != 1'b0)
+        $display("XOR test 3 - zero: %h, expected: 0", zero);
+
+        $display("Starting SLT tests...");
+        // SLT test 1
+        command=`SLT; operandA=32'h00000001; operandB=32'h05000000; #5000                                   //positive numbers
+        if(result != 32'h00000001)
+        $display("SLT test 1 - result: %h, expected: 00000001", result);
+        // SLT test a
+        command=`SLT; operandA=32'h7FFFFFFF; operandB=32'h80000001; #5000
+        if(result != 32'h00000000)
+        $display("SLT test 2 - result: %h, expected: 00000000", result);
+        // SLT test b
+        command=`SLT; operandA=32'h00000001; operandB=32'h00000001; #5000
+        if(result != 32'h00000000)
+        $display("SLT test 2 - result: %h, expected: 00000000", result);
+        // SLT test 2
+        command=`SLT; operandA=32'h05000000; operandB=32'h00000001; #5000
+        if(result != 32'h00000000)
+        $display("SLT test 2 - result: %h, expected: 00000000", result);
+        // SLT test 3
+        command=`SLT; operandA=32'h80000000; operandB=32'hF0000000; #5000                                   //negative numbers
+        if(result != 32'h00000001)
+        $display("SLT test 3 - result: %h, expected: 00000001", result);
+        // SLT test 4
+        command=`SLT; operandA=32'hF0000000; operandB=32'h80000000; #5000
+        if(result != 32'h00000000)
+        $display("SLT test 4 - result: %h, expected: 00000000", result);
+        // SLT test 5
+        command=`SLT; operandA=32'h80000000; operandB=32'h05000000; #5000                                   //positive and negative numbers
+         if(result != 32'h00000001)
+        $display("SLT test 5 - result: %h, expected: 00000001", result);
+        // SLT test 6
+        command=`SLT; operandA=32'h05000000; operandB=32'h80000000; #5000
+         if(result != 32'h00000000)
+        $display("SLT test 6 - result: %h, expected: 00000000", result);
+        // SLT test 7
+        command=`SLT; operandA=32'h00000000; operandB=32'h00000000; #5000                                   //zeros
+         if(result != 32'h00000000)
+        $display("SLT test 7 - result: %h, expected: 00000000", result);
+
+        $display("Starting AND tests...");
+        // AND test 1
+        command=`And; operandA=32'h88888888; operandB=32'h11111111; #5000
+         if(result != 32'h00000000)
+        $display("AND test 1 - result: %h, expected: 00000000", result);
+         if(zero != 1'b1)
+        $display("AND test 1 - zero: %h, expected: 1", zero);
+        // AND test 2
+        command=`And; operandA=32'hCCCCCCCC; operandB=32'hCCCCCCCC; #5000
+         if(result != 32'hCCCCCCCC)
+        $display("AND test 2 - result: %h, expected: CCCCCCCC", result);
+         if(zero != 1'b0)
+        $display("AND test 2 - zero: %h, expected: 0", zero);
+        // AND test 3
+        command=`And; operandA=32'hBBBBBBBB; operandB=32'h55555555; #5000
+         if(result != 32'h11111111)
+        $display("AND test 3 - result: %h, expected: 11111111", result);
+         if(zero != 1'b0)
+        $display("AND test 3 - zero: %h, expected: 0", zero);
+
+        $display("Starting NAND tests...");
+        // NAND test 1
+        command=`Nand; operandA=32'h88888888; operandB=32'h11111111; #5000
+         if(result != 32'hFFFFFFFF)
+        $display("NAND test 1 - result: %h, expected: FFFFFFFF", result);
+         if(zero != 1'b0)
+        $display("NAND test 1 - zero: %h, expected: 0", zero);
+        // NAND test 2
+        command=`Nand; operandA=32'hCCCCCCCC; operandB=32'hCCCCCCCC; #5000
+         if(result != 32'h33333333)
+        $display("NAND test 2 - result: %h, expected: 33333333", result);
+         if(zero != 1'b0)
+        $display("NAND test 2 - zero: %h, expected: 0", zero);
+        // NAND test 3
+        command=`Nand; operandA=32'hBBBBBBBB; operandB=32'h55555555; #5000
+         if(result != 32'hEEEEEEEE)
+        $display("NAND test 3 - result: %h, expected: EEEEEEEE", result);
+         if(zero != 1'b0)
+        $display("NAND test 3 - zero: %h, expected: 0", zero);
+
+        $display("Starting NOR tests...");
+        // NOR test 1
+        command=`Nor; operandA=32'h88888888; operandB=32'h11111111; #5000
+         if(result != 32'h66666666)
+        $display("NOR test 1 - result: %h, expected: 66666666", result);
+         if(zero != 1'b0)
+        $display("NOR test 1 - zero: %h, expected: 0", zero);
+        // NOR test 2
+        command=`Nor; operandA=32'hCCCCCCCC; operandB=32'hCCCCCCCC; #5000
+         if(result != 32'h33333333)
+        $display("NOR test 2 - result: %h, expected: 33333333", result);
+         if(zero != 1'b0)
+        $display("NOR test 2 - zero: %h, expected: 0", zero);
+        // NOR test 3
+        command=`Nor; operandA=32'hBBBBBBBB; operandB=32'h55555555; #5000
+         if(result != 32'h00000000)
+        $display("NOR test 3 - result: %h, expected: 00000000", result);
+         if(zero != 1'b1)
+        $display("NOR test 3 - zero: %h, expected: 1", zero);
+
+        $display("Starting OR tests...");
+        // OR test 1
+        command=`Or; operandA=32'h88888888; operandB=32'h11111111; #5000
+         if(result != 32'h99999999)
+        $display("OR test 1 - result: %h, expected: 99999999", result);
+         if(zero != 1'b0)
+        $display("OR test 1 - zero: %h, expected: 0", zero);
+        // OR test 2
+        command=`Or; operandA=32'hCCCCCCCC; operandB=32'hCCCCCCCC; #5000
+         if(result != 32'hCCCCCCCC)
+        $display("OR test 2 - result: %h, expected: CCCCCCCC", result);
+         if(zero != 1'b0)
+        $display("OR test 2 - zero: %h, expected: 0", zero);
+        // OR test 3
+        command=`Or; operandA=32'hBBBBBBBB; operandB=32'h55555555; #5000
+         if(result != 32'hFFFFFFFF)
+        $display("OR test 3 - result: %h, expected: FFFFFFFF", result);
+         if(zero != 1'b0)
+        $display("OR test 3 - zero: %h, expected: 0", zero);
+
+        $display("ALU tests done!");
+        $display("--------------------------------------------------");
+        $finish();
+    end
+endmodule

alu.v

@@ -0,0 +1,97 @@
+//------------------------------------------------------------------------
+// ALU Module
+//------------------------------------------------------------------------
+
+`define ADD  3'd0
+`define SUB  3'd1
+`define Xor  3'd2
+`define SLT  3'd3
+`define And  3'd4
+`define Nand 3'd5
+`define Nor  3'd6
+`define Or   3'd7
+`include "alu_function.v"
+`define NOR32 nor  //32 input NOR
+
+module ALU
+(
+output[31:0]  result,
+output        carryout,
+output        zero,
+output        overflow,
+input[31:0]   operandA,
+input[31:0]   operandB,
+input[2:0]    command
+);
+  //declare wires
+	wire[31:0] out0, out1, out2, out3, out4;
+	wire 			 cout0, cout1, cout2, cout3, cout4;
+	wire 			 over0, over1, over2, over3, over4;
+	wire 			 invert;
+	wire[2:0]  muxindex;
+	wire[32:0] carryin0;
+
+  //use LUT to get variable assignments for muxindex and invert depending on the input command
+	ALUcontrolLUT lut(.muxindex(muxindex), .invert(invert), .ALUcommand(command));
+  //first carryin of add-subtract module is identical to the invert signal
+	assign carryin0[0] = invert;
+
+  //bit slice approach, generate 32 of each module for full capability
+	genvar i;
+	generate for (i = 0; i < 32; i = i + 1) begin
+			AddSubN adder(.sum(out0[i]), .carryout(carryin0[i+1]), .a(operandA[i]), .b(operandB[i]), .carryin(carryin0[i]), .subtract(invert));
+
+			XORmod xorer(.out(out1[i]), .carryout(cout1), .overflow(over1), .a(operandA[i]), .b(operandB[i]));
+
+			NANDmod nander(.out(out3[i]), .carryout(cout3), .overflow(over3), .a(operandA[i]), .b(operandB[i]), .invert(invert));
+
+			NORmod norer(.out(out4[i]), .carryout(cout4), .overflow(over4), .a(operandA[i]), .b(operandB[i]), .invert(invert));
+  end
+	endgenerate
+
+	SLTmod slter (.slt(out2), .carryout(cout2), .overflow(over2), .a(operandA), .b(operandB));
+
+	//set carryout for adder, equivalent to the "carryin" of the 33rd bit
+  assign cout0 = carryin0[32];
+	//calculate overflow for adder; overflow if final carryout is not equal to carryin of most significant bit
+	`XOR OVERFLOW(over0, cout0, carryin0[31]);
+
+  //mux between generated outputs depending on muxindex given by ALUcommand
+	genvar n;
+	generate for (n = 0; n < 32; n = n + 1) begin
+			structuralMultiplexer5 resultmux (.out(result[n]), .command(muxindex), .in0(out0[n]), .in1(out1[n]), .in2(out2[n]), .in3(out3[n]), .in4(out4[n]));
+  end
+	endgenerate
+
+	//mux between carryouts
+	structuralMultiplexer5 coutmux (.out(carryout), .command(muxindex), .in0(cout0), .in1(cout1), .in2(cout2), .in3(cout3), .in4(cout4));
+	//mux between overflows
+	structuralMultiplexer5 overmux (.out(overflow), .command(muxindex), .in0(over0), .in1(over1), .in2(over2), .in3(over3), .in4(over4));
+
+  //if all bits of the result are zero, the output zero should return zero
+	`NOR32 norgate(zero, result[0], result[1], result[2], result[3], result[4], result[5], result[6], result[7], result[8], result[9], result[10],
+		result[11], result[12], result[13], result[14], result[15], result[16], result[17], result[18], result[19], result[20], result[21], result[22],
+		result[23], result[24], result[25], result[26], result[27], result[28], result[29], result[30], result[31]);
+
+endmodule
+
+
+module ALUcontrolLUT
+(
+output reg[2:0] muxindex,
+output reg	invert,
+input[2:0]	ALUcommand
+);
+  always @(ALUcommand) begin
+    case (ALUcommand)
+      `ADD:  begin muxindex = 0; invert=0; end
+      `SUB:  begin muxindex = 0; invert=1; end
+      `Xor:  begin muxindex = 1; invert=0; end
+      `SLT:  begin muxindex = 2; invert=0; end
+      `Nand: begin muxindex = 3; invert=0; end
+      `And:  begin muxindex = 3; invert=1; end
+      `Nor:  begin muxindex = 4; invert=0; end
+      `Or:   begin muxindex = 4; invert=1; end
+    endcase
+  end
+endmodule