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Finished ASM test file#14

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ppfenninger wants to merge 26 commits intoCompArchFA18:masterfrom

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Commits on Oct 23, 2018

added workplan
ppfenninger
authored

Commits on Oct 25, 2018

Added mux + testbench
ccellis
committed
Added CPU.v with opcode and funct defines
ccellis
committed
Added and verified register write LUT.
ccellis
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Added regfile and testbench
ccellis
committed

Commits on Oct 28, 2018

Finished adder and adder test
ppfenninger
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Mostly finished ALU
ppfenninger
committed

Commits on Oct 30, 2018

Finished first version of CPU
ppfenninger
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Commits on Nov 3, 2018

Created an asm test
ccellis
committed
Made testbench work
ccellis
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fixed some logic
ppfenninger
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Merge branch 'master' of https://github.com/ppfenninger/Lab3
ppfenninger
committed
Beginning the long process of debugging
ccellis
committed
fixed is Jump select
ppfenninger
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fixed is Jump select
ppfenninger
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got rid of extra CPU inputs
ppfenninger
committed

Commits on Nov 4, 2018

fixed most of the MUX warnings in CPU
ppfenninger
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actually stuff in CPU.t.v
ppfenninger
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Merge branch 'master' of https://github.com/ppfenninger/Lab3
ppfenninger
committed

Commits on Nov 7, 2018

Updated alu with correct SLT logic.
ccellis
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Continued bugfixes for CPU
ccellis
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Bugfix for memReg I think?
ccellis
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Finalized CPU testbench
ccellis
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Final polishing of test benches, added script to run them all
ccellis
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added README for asmtests
ccellis
committed

Commits on Nov 9, 2018

Add files via upload
ppfenninger
authored