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@jerenkrantz jerenkrantz commented Dec 26, 2025

Implements up_flush_dcache_all for litex / vexriscv boards.

This duplicates up_invalidate_dcache_all as vexriscv's DBUS cache
does not distinguish between flushing and invalidation.

This was discussed earlier in #17493 and it was felt that this code fix might be better than removing the CONFIG_ARCH_DCACHE definitions.

Summary

Currently, litex / vexriscv boards do not compile as up_flush_dcache_all is not defined.

Impact

Allows compilation of arty_a7:nsh.

Testing

compilation succeeds with arty_a7:nsh builds and runs successfully on a vexriscv linux variant.

…s defined.

This duplicates the up_invalidate_dcache_all as vexriscv's DBUS cache
does not distinguish between flushing and invalidation.

Signed-off-by: Justin Erenkrantz <justin@erenkrantz.com>
@github-actions github-actions bot added Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Size: S The size of the change in this PR is small labels Dec 26, 2025
@jerenkrantz jerenkrantz marked this pull request as ready for review December 26, 2025 14:47
@acassis acassis merged commit f10cf58 into apache:master Dec 27, 2025
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Arch: risc-v Issues related to the RISC-V (32-bit or 64-bit) architecture Size: S The size of the change in this PR is small

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3 participants