Skip to content

Pull requests: diffblue/hw-cbmc

New pull request New
45 Open 1,466 Closed
45 Open 1,466 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

KNOWNBUGs for loop index declaration and smv conversion with buechi
#1575 opened Jan 7, 2026 by Romy15200 Loading…
1
Verilog: elaboration per compilation unit Verilog
#1561 opened Jan 3, 2026 by kroening • Draft
SMV: remove legacy grammar rules cleanup SMV
#1503 opened Dec 20, 2025 by kroening • Draft
Verilog: use instance_array for width of primitive gates cleanup Verilog
#1501 opened Dec 20, 2025 by kroening Loading…
1
Generate vcd for all cover statements
#1493 opened Dec 16, 2025 by ShashankVM Loading…
1
2
SystemVerilog: sequence and property ports Verilog
#1436 opened Nov 24, 2025 by kroening • Draft
Make the counter synthesizable, update comment
#1414 opened Nov 15, 2025 by ShashankVM • Draft
1
SMV: pre-traversal identifier conversion SMV
#1409 opened Nov 12, 2025 by kroening • Draft
SMV output: use IVAR
#1396 opened Nov 9, 2025 by kroening • Draft
SMV: use NuSMV's operator precedence SMV
#1382 opened Nov 2, 2025 by kroening • Draft
netlist conversion: replace recursion by explicit stack engines
#1373 opened Oct 29, 2025 by kroening • Draft
bump CBMC dependency to release 6.8.0 dependencies Pull requests that update a dependency file
#1364 opened Oct 26, 2025 by kroening • Draft
Verilog: fix semantics of cover disable iff Verilog
#1346 opened Oct 20, 2025 by kroening • Draft
split up ltl_sva_to_stringt::rec cleanup engines
#1171 opened Jun 27, 2025 by kroening • Draft
SVA: strengthen typing of sva_sequence_concatenation_exprt cleanup
#1161 opened Jun 17, 2025 by kroening • Draft
1
NeurIPS 2025 SystemVerilog benchmarks
#1147 opened Jun 6, 2025 by kroening Loading…
SMV: bit selection operator SMV
#1113 opened May 18, 2025 by kroening • Draft
SMV: expression typechecker now post-traversal SMV
#1040 opened Mar 28, 2025 by kroening Loading…
2
SVA monitor engines Verilog
#1011 opened Feb 25, 2025 by kroening • Draft
SystemVerilog: interface instantiation Verilog
#972 opened Feb 6, 2025 by kroening • Draft
SystemVerilog: declarations in named blocks in tasks/functions Verilog
#970 opened Feb 6, 2025 by kroening • Draft
1
SystemVerilog: preserve scopes between compilation units Verilog
#963 opened Feb 4, 2025 by kroening • Draft
SystemVerilog: create identifier expressions in scanner Verilog
#953 opened Jan 29, 2025 by kroening • Draft
Add chipsalliance/sv-tests to CI
#939 opened Jan 17, 2025 by kroening • Draft
vlindex: fix parsing for constraint_block
#924 opened Jan 6, 2025 by kroening • Draft
ProTip! Exclude everything labeled bug with -label:bug.