AES in Hardware: N-Studies

This is a series of studies of AES implementations in VHDL.

License

This work is licensed under AGPL. Commercial license is available upon request.

Building

If you want to use the provided makefiles, there are the following prerequisites:

• GHDL
• GTKWave

Use the following command to install those on Debian:

$ apt install ghdl gtkwave

To build a core, (e.g. 001_AES_128_Simple) use:

cd 001_AES_128_Simple/
make
gtkwave sim/AES_TB.ghw

OR import the VHDL-files directly into your design. The testbench is compatible with ModelSim.

Inteface

Almost every AES core has interface of the following form:

entity AES__ is
  port (
    clk         : in  std_logic;
    -- management
    input_valid : in  std_logic;
    done        : out std_logic;
    -- data
    key         : in  std_logic_vector(127 downto 0);
    input       : in  std_logic_vector(127 downto 0);
    output      : out std_logic_vector(127 downto 0));
end entity AES__;

To start an encryption, each core expects that the signals done and input_valid equal to 1, and that the signals key and input are valid. Once done, the core sets a valid output and asserts done for one clock cycle. Once done is asserted, the core is ready to start another encryption.

001_AES_128_Simple

A straightforward implementation to the AES-128 encryption. This core needs 11 clock cycles to perform one AES-128 encryption.

002_AES_128_Pipelined

This is the pipelined version of the 001_AES_128_Simple implementation.